Apple Microarchitecture Research by Dougall Johnson M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions M1/A14 E-core (Icestorm): Overview | Base Instructions | SIMD and FP Instructions
Code:
ldp s0, s1, [x6, #0x10]
mov x0, 1 mov x1, 2 mov x8, 0
(no loop instructions)
Retires: 2.000
Issues: 1.000
Integer unit issues: 0.000
Load/store unit issues: 1.000
SIMD/FP unit issues: 0.000
| retire uop (01) | cycle (02) | 03 | l1d tlb fill (05) | mmu table walk instruction (07) | mmu table walk data (08) | 09 | l2 tlb miss instruction (0a) | l2 tlb miss data (0b) | 0e | 0f | 1e | 22 | 3a | 3f | 43 | 46 | 49 | 4f | 51 | schedule uop (52) | schedule ldst uop (55) | dispatch ldst uop (58) | simd uops in schedulers (5a) | 60 | 69 | 6d | 6e | map stall dispatch (70) | map rewind (75) | map stall (76) | dispatch uop (78) | map ldst uop (7d) | map ldst uop inputs (80) | 82 | 83 | flush restart other nonspec (84) | 85 | inst all (8c) | 92 | inst simd load (98) | inst ldst (9b) | 9d | l1d tlb access (a0) | l1d tlb miss (a1) | l1d cache miss ld (a3) | ld unit uop (a6) | st unit uop (a7) | l1d cache writeback (a8) | a9 | ac | af | b5 | b6 | bb | l1d cache miss ld nonspec (bf) | l1d tlb miss nonspec (c1) | c2 | cf | d5 | map dispatch bubble (d6) | dd | fetch restart (de) | e0 | ea | eb | ec | ? ldst retires (ed) | ? simd retires (ee) | f5 | f6 | f7 | f8 | fd |
| 2005 | 408 | 2 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 81 | 1 | 3 | 393 | 15 | 7 | 20 | 25 | 25 | 1000 | 1000 | 1000 | 15803 | 1 | 363 | 408 | 408 | 106 | 3 | 141 | 1000 | 2000 | 1000 | 389 | 408 | 1 | 1 | 1001 | 4 | 1000 | 1000 | 0 | 1019 | 21 | 58 | 1073 | 0 | 0 | 0 | 75 | 1039 | 6 | 1 | 42 | 0 | 19 | 0 | 76 | 5 | 16 | 6 | 6 | 406 | 10 | 10 | 5 | 1000 | 1000 | 409 | 409 | 409 | 390 | 409 |
| 2004 | 388 | 2 | 1 | 1 | 1 | 0 | 1 | 1 | 0 | 0 | 81 | 0 | 2 | 393 | 16 | 0 | 19 | 25 | 25 | 1000 | 1000 | 1000 | 15800 | 1 | 383 | 408 | 408 | 86 | 3 | 141 | 1000 | 2000 | 1000 | 408 | 408 | 1 | 1 | 1001 | 4 | 1000 | 1000 | 0 | 1020 | 19 | 56 | 1042 | 0 | 0 | 0 | 76 | 1022 | 0 | 1 | 72 | 45 | 19 | 0 | 75 | 6 | 16 | 6 | 6 | 405 | 0 | 10 | 0 | 1000 | 1000 | 409 | 409 | 409 | 409 | 390 |
| 2004 | 408 | 3 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 43 | 0 | 2 | 393 | 22 | 0 | 20 | 27 | 25 | 1000 | 1000 | 1000 | 14906 | 1 | 383 | 408 | 408 | 86 | 3 | 141 | 1000 | 2000 | 1000 | 389 | 408 | 1 | 1 | 1001 | 4 | 1000 | 1000 | 0 | 1021 | 19 | 0 | 1042 | 1 | 0 | 0 | 75 | 1055 | 6 | 1 | 73 | 45 | 19 | 1 | 75 | 6 | 16 | 6 | 6 | 405 | 10 | 10 | 0 | 1000 | 1000 | 390 | 389 | 390 | 409 | 409 |
| 2004 | 408 | 3 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 88 | 1 | 2 | 374 | 15 | 7 | 0 | 6 | 25 | 1000 | 1000 | 1000 | 14853 | 1 | 383 | 389 | 408 | 106 | 3 | 121 | 1000 | 2000 | 1000 | 408 | 408 | 1 | 1 | 1001 | 0 | 1000 | 1000 | 0 | 1020 | 21 | 58 | 1073 | 0 | 0 | 0 | 44 | 1055 | 0 | 1 | 73 | 45 | 19 | 0 | 76 | 6 | 16 | 6 | 5 | 405 | 10 | 10 | 5 | 1000 | 1000 | 390 | 409 | 409 | 409 | 409 |
| 2004 | 389 | 3 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 84 | 1 | 1 | 374 | 15 | 0 | 20 | 25 | 25 | 1000 | 1000 | 1000 | 15765 | 1 | 383 | 408 | 408 | 106 | 3 | 141 | 1000 | 2000 | 1000 | 408 | 408 | 1 | 1 | 1001 | 4 | 1000 | 1000 | 0 | 1021 | 20 | 58 | 1041 | 1 | 1 | 1 | 44 | 1054 | 6 | 0 | 73 | 0 | 19 | 0 | 75 | 6 | 16 | 5 | 5 | 405 | 10 | 10 | 5 | 1000 | 1000 | 409 | 409 | 409 | 409 | 390 |
| 2004 | 408 | 3 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 1 | 44 | 0 | 2 | 393 | 23 | 7 | 20 | 6 | 25 | 1000 | 1000 | 1000 | 14837 | 1 | 364 | 408 | 408 | 106 | 3 | 141 | 1000 | 2000 | 1000 | 409 | 408 | 1 | 1 | 1001 | 4 | 1000 | 1000 | 0 | 1019 | 20 | 0 | 1042 | 1 | 0 | 1 | 74 | 1054 | 6 | 1 | 73 | 45 | 19 | 0 | 75 | 6 | 16 | 5 | 5 | 405 | 0 | 0 | 5 | 1000 | 1000 | 389 | 409 | 409 | 409 | 409 |
| 2004 | 389 | 3 | 1 | 1 | 0 | 0 | 1 | 1 | 0 | 1 | 43 | 0 | 3 | 374 | 15 | 7 | 20 | 25 | 25 | 1000 | 1000 | 1000 | 15800 | 1 | 383 | 391 | 389 | 106 | 3 | 141 | 1000 | 2000 | 1000 | 388 | 389 | 1 | 1 | 1001 | 4 | 1000 | 1000 | 0 | 1019 | 19 | 58 | 1073 | 0 | 1 | 2 | 75 | 1054 | 0 | 1 | 42 | 0 | 19 | 0 | 75 | 5 | 16 | 6 | 6 | 405 | 10 | 0 | 0 | 1000 | 1000 | 409 | 409 | 409 | 409 | 409 |
| 2004 | 408 | 3 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 81 | 1 | 4 | 393 | 16 | 7 | 20 | 25 | 25 | 1000 | 1000 | 1000 | 14856 | 1 | 383 | 408 | 388 | 86 | 3 | 122 | 1000 | 2000 | 1000 | 388 | 389 | 1 | 1 | 1001 | 4 | 1000 | 1000 | 0 | 1019 | 21 | 58 | 1073 | 2 | 0 | 1 | 75 | 1054 | 6 | 1 | 71 | 0 | 19 | 0 | 75 | 6 | 16 | 6 | 6 | 405 | 0 | 0 | 5 | 1000 | 1000 | 409 | 409 | 409 | 390 | 390 |
| 2004 | 408 | 2 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 0 | 82 | 1 | 2 | 393 | 15 | 7 | 20 | 25 | 25 | 1000 | 1000 | 1000 | 14796 | 1 | 383 | 408 | 408 | 106 | 3 | 122 | 1000 | 2000 | 1000 | 408 | 409 | 1 | 1 | 1001 | 4 | 1000 | 1000 | 1 | 1017 | 20 | 58 | 1073 | 0 | 0 | 0 | 44 | 1055 | 6 | 1 | 73 | 45 | 19 | 0 | 75 | 5 | 16 | 5 | 5 | 405 | 10 | 10 | 5 | 1000 | 1000 | 409 | 390 | 409 | 409 | 409 |
| 2004 | 408 | 3 | 1 | 1 | 0 | 0 | 1 | 1 | 0 | 0 | 81 | 0 | 2 | 393 | 22 | 0 | 20 | 25 | 25 | 1000 | 1000 | 1000 | 14839 | 1 | 383 | 408 | 388 | 106 | 3 | 141 | 1000 | 2000 | 1000 | 388 | 408 | 1 | 1 | 1001 | 4 | 1000 | 1000 | 0 | 1020 | 20 | 58 | 1042 | 0 | 0 | 0 | 75 | 1054 | 6 | 1 | 72 | 45 | 19 | 2 | 75 | 5 | 16 | 5 | 6 | 386 | 0 | 10 | 5 | 1000 | 1000 | 390 | 409 | 409 | 409 | 409 |
Chain cycles: 3
Code:
ldp s0, s1, [x6, #0x10] fmov x0, d0 eor x8, x8, x0 eor x8, x8, x0 add x6, x6, x8
mov x0, 1 mov x1, 2 mov x8, 0
(fused SUBS/B.cc loop)
Result (median cycles for code, minus 3 chain cycles): 9.0054
| retire uop (01) | cycle (02) | 03 | 0e | 0f | 1e | 22 | 23 | 3f | 4d | 4f | 51 | schedule uop (52) | schedule int uop (53) | schedule simd uop (54) | schedule ldst uop (55) | dispatch int uop (56) | dispatch simd uop (57) | dispatch ldst uop (58) | int uops in schedulers (59) | simd uops in schedulers (5a) | ldst uops in schedulers (5b) | 60 | 69 | 6d | 6e | map stall dispatch (70) | map rewind (75) | map stall (76) | dispatch uop (78) | map int uop (7c) | map ldst uop (7d) | map simd uop (7e) | map int uop inputs (7f) | map ldst uop inputs (80) | map simd uop inputs (81) | 82 | 83 | flush restart other nonspec (84) | 85 | inst all (8c) | inst branch (8d) | inst branch taken (90) | inst branch cond (94) | inst int alu (97) | inst simd load (98) | inst ldst (9b) | 9d | 9f | l1d tlb access (a0) | l1d cache miss ld (a3) | ld unit uop (a6) | st unit uop (a7) | l1d cache writeback (a8) | ac | af | b5 | l1d cache miss ld nonspec (bf) | branch cond mispred nonspec (c5) | branch mispred nonspec (cb) | cd | cf | d5 | map dispatch bubble (d6) | dd | fetch restart (de) | e0 | ? int output thing (e9) | ea | eb | ec | ? ldst retires (ed) | ? simd retires (ee) | ? int retires (ef) | f5 | f6 | f7 | f8 | fd |
| 60205 | 120051 | 899 | 1 | 0 | 1 | 0 | 0 | 120039 | 119509 | 109461 | 25 | 60103 | 40100 | 10000 | 10000 | 30100 | 10000 | 10000 | 1079396 | 5736230 | 6118285 | 1 | 120030 | 120054 | 120054 | 111881 | 3 | 112407 | 50100 | 30200 | 20000 | 10000 | 60200 | 10000 | 10000 | 120035 | 120035 | 1 | 1 | 50201 | 100 | 99 | 100 | 40100 | 10000 | 10000 | 1 | 100 | 10000 | 0 | 10000 | 0 | 0 | 0 | 10000 | 1 | 1 | 0 | 0 | 0 | 3210 | 1 | 121 | 1 | 1 | 119666 | 40002 | 10 | 10 | 0 | 10000 | 10000 | 40100 | 120055 | 120055 | 120055 | 120055 | 120055 |
| 60204 | 120054 | 899 | 0 | 0 | 1 | 1 | 0 | 120036 | 119509 | 109461 | 25 | 60106 | 40102 | 10001 | 10000 | 30100 | 10000 | 10000 | 1079396 | 5736470 | 6118285 | 1 | 120030 | 120054 | 120035 | 111900 | 3 | 112417 | 50100 | 30200 | 20000 | 10000 | 60200 | 10000 | 10000 | 120054 | 120051 | 1 | 1 | 50201 | 100 | 99 | 100 | 40100 | 10000 | 10000 | 0 | 100 | 10000 | 1 | 10000 | 0 | 0 | 0 | 10000 | 1 | 1 | 0 | 0 | 1 | 3210 | 1 | 121 | 1 | 1 | 119666 | 40002 | 13 | 10 | 0 | 10000 | 10000 | 40100 | 120055 | 120055 | 120055 | 120055 | 120055 |
| 60204 | 120054 | 899 | 0 | 0 | 1 | 0 | 0 | 120039 | 119509 | 109461 | 25 | 60103 | 40102 | 10001 | 10000 | 30100 | 10000 | 10000 | 1079552 | 5735293 | 6118285 | 1 | 120030 | 120054 | 120051 | 111900 | 3 | 112407 | 50100 | 30200 | 20000 | 10000 | 60200 | 10000 | 10000 | 120035 | 120051 | 1 | 1 | 50201 | 100 | 99 | 100 | 40100 | 10000 | 10000 | 1 | 100 | 10000 | 0 | 10000 | 0 | 0 | 0 | 10000 | 1 | 1 | 0 | 0 | 0 | 3210 | 1 | 121 | 1 | 1 | 119646 | 40002 | 13 | 10 | 9 | 10000 | 10000 | 40100 | 120055 | 120055 | 120061 | 120055 | 120055 |
| 60204 | 120054 | 899 | 0 | 0 | 1 | 0 | 0 | 120039 | 119509 | 109459 | 25 | 60103 | 40102 | 10001 | 10000 | 30100 | 10000 | 10049 | 1079552 | 5736084 | 6118285 | 1 | 120496 | 120051 | 120054 | 111900 | 3 | 112407 | 50100 | 30200 | 20000 | 10000 | 60200 | 10000 | 10000 | 120145 | 120051 | 3 | 1 | 50201 | 100 | 99 | 100 | 40100 | 10000 | 10000 | 1 | 100 | 10000 | 1 | 10000 | 2 | 2 | 0 | 10000 | 1 | 1 | 1 | 0 | 0 | 3210 | 1 | 108 | 1 | 1 | 119666 | 40002 | 13 | 10 | 9 | 10000 | 10000 | 40100 | 120055 | 120055 | 120058 | 120055 | 120055 |
| 60204 | 120054 | 899 | 0 | 0 | 1 | 0 | 0 | 120036 | 119495 | 109461 | 25 | 60103 | 40102 | 10000 | 10000 | 30100 | 10000 | 10000 | 1079552 | 5736230 | 6118285 | 1 | 120090 | 120054 | 120054 | 111900 | 3 | 112407 | 50100 | 30200 | 20000 | 10000 | 60200 | 10000 | 10000 | 120057 | 120051 | 1 | 1 | 50201 | 100 | 99 | 100 | 40100 | 10000 | 10000 | 0 | 100 | 10000 | 1 | 10000 | 0 | 0 | 0 | 10000 | 1 | 1 | 0 | 0 | 0 | 3210 | 1 | 121 | 1 | 1 | 119666 | 40002 | 10 | 10 | 9 | 10000 | 10000 | 40100 | 120036 | 120055 | 120055 | 120055 | 120055 |
| 60204 | 120035 | 899 | 0 | 0 | 1 | 0 | 0 | 120036 | 119509 | 109459 | 25 | 60103 | 40102 | 10001 | 10000 | 30100 | 10000 | 10000 | 1079396 | 5736230 | 6117599 | 1 | 120011 | 120054 | 120054 | 111900 | 3 | 112407 | 50100 | 30200 | 20000 | 10000 | 60200 | 10000 | 10000 | 120146 | 120038 | 1 | 1 | 50201 | 100 | 99 | 100 | 40100 | 10000 | 10000 | 0 | 100 | 10000 | 0 | 10000 | 0 | 0 | 3 | 10000 | 1 | 1 | 0 | 0 | 0 | 3210 | 1 | 108 | 1 | 1 | 119666 | 40002 | 13 | 10 | 9 | 10000 | 10000 | 40100 | 120055 | 120055 | 120055 | 120055 | 120036 |
| 60204 | 120054 | 899 | 0 | 0 | 7 | 0 | 0 | 120039 | 119509 | 109461 | 25 | 60103 | 40102 | 10001 | 10000 | 30100 | 10000 | 10000 | 1079405 | 5736374 | 6118285 | 1 | 120028 | 120054 | 120051 | 111900 | 3 | 112407 | 50100 | 30200 | 20000 | 10000 | 60200 | 10000 | 10000 | 120054 | 120051 | 1 | 1 | 50201 | 100 | 99 | 100 | 40100 | 10000 | 10000 | 1 | 100 | 10000 | 1 | 10000 | 0 | 0 | 1 | 10000 | 1 | 1 | 1 | 0 | 0 | 3210 | 1 | 121 | 1 | 1 | 119666 | 40002 | 13 | 10 | 12 | 10000 | 10000 | 40100 | 120055 | 120036 | 120055 | 120055 | 120036 |
| 60204 | 120051 | 899 | 0 | 0 | 1 | 0 | 0 | 120036 | 119495 | 109461 | 25 | 60103 | 40102 | 10001 | 10000 | 30100 | 10000 | 10000 | 1079396 | 5736230 | 6117599 | 1 | 120027 | 120051 | 120054 | 111900 | 3 | 112417 | 50100 | 30200 | 20000 | 10000 | 60200 | 10000 | 10000 | 120035 | 120051 | 1 | 1 | 50201 | 100 | 99 | 100 | 40100 | 10000 | 10000 | 1 | 100 | 10000 | 0 | 10000 | 0 | 0 | 3 | 10000 | 1 | 1 | 0 | 0 | 0 | 3210 | 1 | 108 | 1 | 1 | 119666 | 40002 | 10 | 10 | 9 | 10000 | 10000 | 40100 | 120052 | 120055 | 120055 | 120055 | 120052 |
| 60204 | 120051 | 899 | 1 | 0 | 0 | 0 | 0 | 120039 | 119495 | 109443 | 25 | 60103 | 40100 | 10000 | 10000 | 30100 | 10000 | 10000 | 1079552 | 5736230 | 6118285 | 1 | 120027 | 120051 | 120051 | 111900 | 3 | 112407 | 50100 | 30200 | 20000 | 10000 | 60200 | 10000 | 10000 | 120054 | 120051 | 1 | 1 | 50201 | 100 | 99 | 100 | 40100 | 10000 | 10000 | 1 | 100 | 10000 | 1 | 10000 | 0 | 0 | 0 | 10000 | 1 | 1 | 0 | 0 | 0 | 3210 | 1 | 108 | 1 | 1 | 119656 | 40002 | 0 | 10 | 9 | 10000 | 10000 | 40100 | 120052 | 120052 | 120055 | 120055 | 120055 |
| 60204 | 120035 | 899 | 0 | 0 | 7 | 0 | 0 | 120036 | 119509 | 109461 | 25 | 60103 | 40102 | 10001 | 10000 | 30100 | 10000 | 10000 | 1079396 | 5736230 | 6118285 | 1 | 120011 | 120051 | 120051 | 111900 | 3 | 112407 | 50100 | 30200 | 20000 | 10000 | 60200 | 10000 | 10000 | 120054 | 120051 | 1 | 1 | 50201 | 100 | 99 | 100 | 40100 | 10000 | 10000 | 0 | 100 | 10000 | 1 | 10000 | 0 | 0 | 0 | 10000 | 0 | 1 | 0 | 0 | 0 | 3210 | 1 | 121 | 1 | 1 | 119656 | 40002 | 13 | 10 | 9 | 10000 | 10000 | 40100 | 120036 | 120055 | 120055 | 120036 | 120055 |
Result (median cycles for code, minus 3 chain cycles): 9.0051
| retire uop (01) | cycle (02) | 03 | mmu table walk instruction (07) | mmu table walk data (08) | 09 | 0e | 0f | 18 | 19 | 1e | 1f | 22 | 23 | 3f | 4d | 4f | 51 | schedule uop (52) | schedule int uop (53) | schedule simd uop (54) | schedule ldst uop (55) | dispatch int uop (56) | dispatch simd uop (57) | dispatch ldst uop (58) | int uops in schedulers (59) | simd uops in schedulers (5a) | ldst uops in schedulers (5b) | 60 | 69 | 6d | 6e | map stall dispatch (70) | map rewind (75) | map stall (76) | dispatch uop (78) | map int uop (7c) | map ldst uop (7d) | map simd uop (7e) | map int uop inputs (7f) | map ldst uop inputs (80) | map simd uop inputs (81) | 82 | 83 | flush restart other nonspec (84) | 85 | inst all (8c) | inst branch (8d) | inst branch taken (90) | inst branch cond (94) | inst int alu (97) | inst simd load (98) | inst ldst (9b) | 9d | 9f | l1d tlb access (a0) | l1d cache miss ld (a3) | ld unit uop (a6) | l1d cache writeback (a8) | ac | af | b5 | bb | l1d cache miss ld nonspec (bf) | c2 | branch mispred nonspec (cb) | cf | d5 | map dispatch bubble (d6) | dd | fetch restart (de) | e0 | ? int output thing (e9) | ea | eb | ec | ? ldst retires (ed) | ? simd retires (ee) | ? int retires (ef) | f5 | f6 | f7 | f8 | fd |
| 60025 | 120051 | 899 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 0 | 120039 | 119484 | 109443 | 25 | 60013 | 40010 | 10000 | 10000 | 30010 | 10000 | 10000 | 1079858 | 5736230 | 6125746 | 1 | 120011 | 120054 | 120035 | 111903 | 3 | 112451 | 50271 | 30020 | 20000 | 10000 | 60020 | 10000 | 10000 | 120054 | 120051 | 1 | 1 | 50021 | 10 | 9 | 10 | 40010 | 10000 | 10000 | 1 | 10 | 10000 | 1 | 10000 | 1 | 0 | 10000 | 1 | 0 | 1 | 0 | 0 | 3140 | 1 | 99 | 1 | 1 | 119650 | 40000 | 0 | 10 | 12 | 10000 | 10000 | 40010 | 120055 | 120055 | 120036 | 120055 | 120036 |
| 60024 | 120035 | 899 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 120039 | 119484 | 109443 | 25 | 60013 | 40012 | 10000 | 10000 | 30010 | 10000 | 10000 | 1079858 | 5735293 | 6125746 | 1 | 120030 | 120054 | 120054 | 111922 | 3 | 112451 | 50010 | 30020 | 20000 | 10000 | 60020 | 10000 | 10000 | 120035 | 120051 | 1 | 1 | 50021 | 10 | 9 | 10 | 40010 | 10000 | 10000 | 1 | 10 | 10000 | 1 | 10000 | 0 | 0 | 10000 | 0 | 0 | 0 | 0 | 0 | 3140 | 1 | 99 | 1 | 1 | 119650 | 40002 | 0 | 10 | 12 | 10000 | 10000 | 40010 | 120055 | 120055 | 120052 | 120036 | 120057 |
| 60024 | 120035 | 899 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 0 | 120036 | 119484 | 109461 | 25 | 60010 | 40012 | 10000 | 10000 | 30010 | 10000 | 10000 | 1079858 | 5735293 | 6124344 | 1 | 120027 | 120035 | 120054 | 111920 | 3 | 112452 | 50010 | 30020 | 20000 | 10000 | 60020 | 10000 | 10000 | 120035 | 120051 | 1 | 1 | 50021 | 10 | 9 | 10 | 40010 | 10000 | 10000 | 0 | 10 | 10001 | 1 | 10000 | 0 | 6 | 10000 | 0 | 0 | 1 | 0 | 0 | 3140 | 1 | 99 | 1 | 1 | 119669 | 40000 | 0 | 0 | 12 | 10000 | 10000 | 40010 | 120036 | 120036 | 120052 | 120055 | 120036 |
| 60024 | 120054 | 899 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 120020 | 119489 | 109443 | 25 | 60013 | 40012 | 10001 | 10000 | 30010 | 10000 | 10000 | 1079888 | 5735293 | 6125746 | 1 | 120027 | 120054 | 120054 | 111922 | 3 | 112451 | 50010 | 30020 | 20000 | 10000 | 60020 | 10000 | 10000 | 120054 | 120051 | 1 | 1 | 50021 | 10 | 9 | 10 | 40010 | 10000 | 10000 | 1 | 10 | 10002 | 1 | 10000 | 4 | 0 | 10000 | 1 | 0 | 1 | 0 | 0 | 3140 | 1 | 94 | 1 | 1 | 119670 | 40002 | 13 | 13 | 12 | 10000 | 10000 | 40010 | 120055 | 120055 | 120055 | 120055 | 120036 |
| 60024 | 120035 | 899 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 120020 | 119487 | 109461 | 25 | 60010 | 40012 | 10001 | 10000 | 30010 | 10000 | 10000 | 1079858 | 5736084 | 6125746 | 1 | 120030 | 120054 | 120035 | 111922 | 3 | 112437 | 50010 | 30020 | 20000 | 10000 | 60020 | 10000 | 10000 | 120035 | 120051 | 1 | 1 | 50021 | 10 | 9 | 10 | 40010 | 10000 | 10000 | 0 | 10 | 10000 | 1 | 10000 | 0 | 0 | 10000 | 1 | 0 | 1 | 0 | 0 | 3140 | 1 | 94 | 1 | 1 | 119669 | 40000 | 10 | 10 | 9 | 10000 | 10000 | 40010 | 120055 | 120052 | 120052 | 120036 | 120036 |
| 60024 | 120035 | 899 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 120039 | 119487 | 109443 | 25 | 60010 | 40012 | 10001 | 10000 | 30010 | 10000 | 10000 | 1079888 | 5736230 | 6124344 | 1 | 120030 | 120054 | 120051 | 111903 | 3 | 112451 | 50010 | 30020 | 20000 | 10000 | 60020 | 10000 | 10000 | 120054 | 120051 | 1 | 1 | 50021 | 10 | 9 | 10 | 40010 | 10000 | 10000 | 1 | 10 | 10000 | 1 | 10000 | 0 | 3 | 10000 | 1 | 1 | 1 | 0 | 0 | 3140 | 1 | 99 | 1 | 1 | 119672 | 40000 | 13 | 0 | 0 | 10000 | 10000 | 40010 | 120036 | 120052 | 120036 | 120036 | 120059 |
| 60024 | 120052 | 900 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 120020 | 119489 | 109461 | 25 | 60013 | 40012 | 10001 | 10000 | 30010 | 10000 | 10000 | 1079858 | 5736230 | 6125899 | 1 | 120030 | 120051 | 120054 | 111903 | 3 | 112437 | 50010 | 30020 | 20000 | 10000 | 60020 | 10000 | 10000 | 120051 | 120051 | 1 | 1 | 50021 | 10 | 9 | 10 | 40010 | 10000 | 10000 | 0 | 10 | 10000 | 1 | 10000 | 0 | 0 | 10000 | 1 | 0 | 1 | 0 | 0 | 3140 | 1 | 94 | 1 | 1 | 119672 | 40002 | 0 | 0 | 12 | 10000 | 10000 | 40010 | 120055 | 120052 | 120055 | 120036 | 120055 |
| 60024 | 120054 | 899 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0 | 1 | 0 | 120020 | 119489 | 109443 | 25 | 60016 | 40012 | 10001 | 10000 | 30010 | 10000 | 10000 | 1079769 | 5736230 | 6125746 | 1 | 120011 | 120054 | 120054 | 111903 | 3 | 112437 | 50010 | 30020 | 20000 | 10000 | 60020 | 10000 | 10000 | 120035 | 120035 | 1 | 1 | 50021 | 10 | 9 | 10 | 40010 | 10000 | 10000 | 0 | 10 | 10000 | 0 | 10000 | 0 | 0 | 10000 | 1 | 0 | 1 | 0 | 0 | 3140 | 1 | 94 | 1 | 1 | 119672 | 40002 | 0 | 13 | 0 | 10000 | 10000 | 40010 | 120052 | 120052 | 120052 | 120055 | 120055 |
| 60024 | 120035 | 899 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 120039 | 119489 | 109459 | 25 | 60010 | 40010 | 10001 | 10000 | 30010 | 10062 | 10000 | 1079948 | 5735341 | 6124344 | 1 | 120011 | 120035 | 120051 | 111922 | 3 | 112437 | 50010 | 30020 | 20000 | 10000 | 60020 | 10000 | 10000 | 120054 | 120051 | 1 | 1 | 50021 | 10 | 9 | 10 | 40010 | 10000 | 10000 | 0 | 10 | 10000 | 1 | 10002 | 61 | 0 | 10000 | 1 | 0 | 1 | 0 | 0 | 3329 | 1 | 94 | 1 | 1 | 119672 | 40002 | 13 | 13 | 0 | 10000 | 10000 | 40010 | 120077 | 120038 | 120058 | 120055 | 120055 |
| 60024 | 120035 | 899 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 12 | 0 | 1 | 0 | 120039 | 119487 | 109461 | 25 | 60013 | 40012 | 10001 | 10000 | 30010 | 10000 | 10000 | 1079888 | 5736230 | 6124344 | 1 | 120030 | 120054 | 120035 | 111922 | 3 | 112451 | 50010 | 30020 | 20000 | 10000 | 60020 | 10000 | 10064 | 120054 | 120054 | 1 | 1 | 50021 | 10 | 9 | 10 | 40010 | 10000 | 10000 | 1 | 10 | 10000 | 1 | 10000 | 0 | 0 | 10000 | 1 | 0 | 1 | 0 | 0 | 3140 | 1 | 99 | 1 | 1 | 119672 | 40002 | 0 | 13 | 12 | 10000 | 10000 | 40010 | 120055 | 120036 | 120036 | 120036 | 120055 |
Chain cycles: 3
Code:
ldp s0, s1, [x6, #0x10] fmov x1, d1 eor x8, x8, x1 eor x8, x8, x1 add x6, x6, x8
mov x0, 1 mov x1, 2 mov x8, 0
(fused SUBS/B.cc loop)
Result (median cycles for code, minus 3 chain cycles): 9.0047
| retire uop (01) | cycle (02) | 03 | mmu table walk instruction (07) | 09 | l2 tlb miss instruction (0a) | l2 tlb miss data (0b) | 0e | 0f | 18 | 19 | 1e | 1f | 22 | 23 | 3f | 4d | 4f | 51 | schedule uop (52) | schedule int uop (53) | schedule simd uop (54) | schedule ldst uop (55) | dispatch int uop (56) | dispatch simd uop (57) | dispatch ldst uop (58) | int uops in schedulers (59) | simd uops in schedulers (5a) | ldst uops in schedulers (5b) | 60 | 69 | 6d | 6e | map stall dispatch (70) | map rewind (75) | map stall (76) | dispatch uop (78) | map int uop (7c) | map ldst uop (7d) | map simd uop (7e) | map int uop inputs (7f) | map ldst uop inputs (80) | map simd uop inputs (81) | 82 | 83 | flush restart other nonspec (84) | 85 | inst all (8c) | inst branch (8d) | inst branch taken (90) | inst branch cond (94) | inst int alu (97) | inst simd load (98) | inst ldst (9b) | 9d | 9f | l1d tlb access (a0) | l1d tlb miss (a1) | l1d cache miss ld (a3) | ld unit uop (a6) | l1d cache writeback (a8) | a9 | ac | af | b5 | l1d cache miss ld nonspec (bf) | c2 | cd | cf | d5 | map dispatch bubble (d6) | dd | fetch restart (de) | e0 | ? int output thing (e9) | ea | eb | ec | ? ldst retires (ed) | ? simd retires (ee) | ? int retires (ef) | f5 | f6 | f7 | f8 | fd |
| 60205 | 120050 | 899 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 120035 | 119538 | 109443 | 25 | 60103 | 40102 | 10001 | 10000 | 30100 | 10000 | 10000 | 1079539 | 5735293 | 6117882 | 0 | 120026 | 120047 | 120050 | 111895 | 3 | 112374 | 50100 | 30200 | 20000 | 10000 | 60200 | 10000 | 10000 | 120050 | 120035 | 1 | 1 | 50201 | 100 | 99 | 100 | 40100 | 10000 | 10000 | 1 | 100 | 10000 | 0 | 1 | 10000 | 1 | 0 | 0 | 10000 | 1 | 1 | 0 | 0 | 3210 | 3 | 135 | 2 | 3 | 119657 | 40002 | 6 | 6 | 0 | 10000 | 10000 | 40100 | 120054 | 120051 | 120036 | 120048 | 120048 |
| 60204 | 120047 | 899 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 120035 | 119503 | 109458 | 25 | 60103 | 40102 | 10001 | 10000 | 30100 | 10000 | 10000 | 1079539 | 5735888 | 6117882 | 0 | 120023 | 120047 | 120047 | 111895 | 3 | 112374 | 50100 | 30200 | 20000 | 10000 | 60200 | 10000 | 10000 | 120047 | 120047 | 1 | 1 | 50201 | 100 | 99 | 100 | 40100 | 10000 | 10000 | 1 | 100 | 10000 | 0 | 1 | 10000 | 0 | 0 | 0 | 10000 | 1 | 1 | 0 | 0 | 3210 | 3 | 135 | 3 | 3 | 119655 | 40002 | 9 | 6 | 0 | 10000 | 10000 | 40100 | 120054 | 120151 | 120053 | 120036 | 120036 |
| 60204 | 120035 | 899 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 120035 | 119494 | 109443 | 25 | 60103 | 40102 | 10001 | 10000 | 30100 | 10000 | 10000 | 1079126 | 5736035 | 6117882 | 0 | 120068 | 120050 | 120035 | 111903 | 3 | 112416 | 50100 | 30200 | 20000 | 10000 | 60200 | 10000 | 10000 | 120050 | 120047 | 1 | 1 | 50201 | 100 | 99 | 100 | 40100 | 10000 | 10000 | 1 | 100 | 10000 | 0 | 1 | 10000 | 0 | 0 | 0 | 10000 | 0 | 1 | 0 | 0 | 3210 | 2 | 108 | 3 | 3 | 119655 | 40002 | 0 | 9 | 5 | 10000 | 10000 | 40100 | 120049 | 120036 | 120073 | 120057 | 120037 |
| 60204 | 120047 | 899 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 120020 | 119494 | 109458 | 25 | 60103 | 40102 | 10001 | 10000 | 30100 | 10000 | 10000 | 1079126 | 5735293 | 6117882 | 0 | 120026 | 120050 | 120050 | 111895 | 3 | 112416 | 50100 | 30200 | 20000 | 10000 | 60200 | 10000 | 10000 | 120047 | 120047 | 1 | 1 | 50201 | 100 | 99 | 100 | 40100 | 10000 | 10000 | 1 | 100 | 10000 | 0 | 0 | 10000 | 1 | 0 | 0 | 10000 | 1 | 1 | 0 | 0 | 3210 | 2 | 135 | 3 | 3 | 119655 | 40002 | 0 | 6 | 8 | 10000 | 10000 | 40100 | 120051 | 120051 | 120048 | 120036 | 120051 |
| 60204 | 120047 | 899 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 120020 | 119538 | 109458 | 25 | 60115 | 40102 | 10001 | 10000 | 30100 | 10000 | 10000 | 1079539 | 5735293 | 6118250 | 0 | 120011 | 120035 | 120050 | 111906 | 3 | 112416 | 50100 | 30200 | 20000 | 10000 | 60200 | 10000 | 10000 | 120050 | 120047 | 1 | 1 | 50201 | 100 | 99 | 100 | 40100 | 10000 | 10000 | 1 | 100 | 10000 | 0 | 0 | 10000 | 0 | 0 | 0 | 10000 | 0 | 0 | 0 | 0 | 3210 | 3 | 108 | 3 | 3 | 119655 | 40002 | 9 | 9 | 0 | 10000 | 10000 | 40100 | 120036 | 120036 | 120048 | 120051 | 120048 |
| 60204 | 120050 | 899 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 0 | 120020 | 119494 | 109458 | 52 | 60103 | 40100 | 10001 | 10000 | 30100 | 10000 | 10000 | 1079539 | 5735293 | 6117599 | 0 | 120011 | 120050 | 120050 | 111881 | 3 | 112416 | 50100 | 30200 | 20000 | 10000 | 60200 | 10000 | 10000 | 120050 | 120035 | 1 | 1 | 50201 | 100 | 99 | 100 | 40100 | 10000 | 10000 | 1 | 100 | 10000 | 0 | 1 | 10000 | 0 | 0 | 0 | 10000 | 0 | 1 | 0 | 0 | 3210 | 3 | 135 | 3 | 3 | 119655 | 40002 | 9 | 9 | 8 | 10000 | 10000 | 40100 | 120056 | 120036 | 120036 | 120036 | 120049 |
| 60204 | 120035 | 899 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 0 | 120032 | 119503 | 109458 | 25 | 60100 | 40100 | 10001 | 10000 | 30100 | 10000 | 10000 | 1079539 | 5736035 | 6117882 | 0 | 120011 | 120050 | 120050 | 111895 | 3 | 112421 | 50100 | 30200 | 20000 | 10000 | 60200 | 10000 | 10000 | 120050 | 120047 | 1 | 1 | 50201 | 100 | 99 | 100 | 40100 | 10000 | 10000 | 1 | 100 | 10000 | 0 | 1 | 10000 | 0 | 0 | 0 | 10000 | 1 | 1 | 0 | 0 | 3210 | 3 | 135 | 2 | 3 | 119655 | 40002 | 9 | 9 | 0 | 10000 | 10000 | 40100 | 120072 | 120058 | 120051 | 120036 | 120051 |
| 60204 | 120047 | 899 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 120035 | 119494 | 109458 | 25 | 60100 | 40102 | 10001 | 10000 | 30100 | 10000 | 10000 | 1079539 | 5736035 | 6118250 | 0 | 120026 | 120047 | 120050 | 111903 | 3 | 112416 | 50100 | 31657 | 22338 | 11232 | 67278 | 11273 | 11234 | 122278 | 122312 | 25 | 1 | 50201 | 100 | 99 | 100 | 40100 | 10000 | 10000 | 1 | 100 | 10035 | 0 | 1 | 10037 | 1 | 4 | 92186 | 10033 | 1 | 1 | 4 | 0 | 3936 | 8 | 209 | 10 | 6 | 121582 | 40002 | 9 | 6 | 8 | 10000 | 10000 | 40100 | 120037 | 120048 | 120063 | 120054 | 120931 |
| 60204 | 120633 | 916 | 6 | 1 | 4 | 1 | 0 | 0 | 32 | 25 | 4225 | 2288 | 1 | 0 | 123047 | 120828 | 110411 | 1130 | 60493 | 40418 | 10075 | 10064 | 35345 | 10367 | 10098 | 1079330 | 5736035 | 6118250 | 0 | 122660 | 121480 | 120051 | 112171 | 196 | 113914 | 55944 | 34737 | 23188 | 11664 | 67374 | 11751 | 11339 | 122664 | 122058 | 26 | 1 | 50201 | 100 | 99 | 100 | 40100 | 10000 | 10000 | 1 | 100 | 10038 | 3 | 1 | 10040 | 1 | 2 | 0 | 10000 | 1 | 1 | 0 | 0 | 3210 | 3 | 108 | 3 | 4 | 119657 | 40002 | 9 | 0 | 5 | 10000 | 10000 | 40100 | 120051 | 120151 | 120144 | 120036 | 120051 |
| 60204 | 120035 | 899 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 120035 | 119494 | 109458 | 25 | 60103 | 40102 | 10001 | 10000 | 30100 | 10000 | 10000 | 1079539 | 5735293 | 6118250 | 0 | 120026 | 120047 | 120050 | 111881 | 3 | 112416 | 50100 | 30200 | 20000 | 10000 | 60200 | 10000 | 10000 | 120050 | 120035 | 1 | 1 | 50201 | 100 | 99 | 100 | 40100 | 10000 | 10000 | 0 | 100 | 10000 | 0 | 0 | 10000 | 0 | 0 | 3 | 10000 | 0 | 0 | 0 | 0 | 3210 | 3 | 110 | 3 | 3 | 119655 | 40002 | 6 | 6 | 5 | 10000 | 10000 | 40100 | 120051 | 120036 | 120151 | 120049 | 120039 |
Result (median cycles for code, minus 3 chain cycles): 9.0054
| retire uop (01) | cycle (02) | 03 | l1i tlb fill (04) | mmu table walk data (08) | 0e | 0f | 18 | 1e | 22 | 24 | 3a | 3f | 4d | 4f | 51 | schedule uop (52) | schedule int uop (53) | schedule simd uop (54) | schedule ldst uop (55) | dispatch int uop (56) | dispatch simd uop (57) | dispatch ldst uop (58) | int uops in schedulers (59) | simd uops in schedulers (5a) | ldst uops in schedulers (5b) | 60 | 69 | 6d | 6e | map stall dispatch (70) | map rewind (75) | map stall (76) | dispatch uop (78) | map int uop (7c) | map ldst uop (7d) | map simd uop (7e) | map int uop inputs (7f) | map ldst uop inputs (80) | map simd uop inputs (81) | 82 | 83 | flush restart other nonspec (84) | 85 | inst all (8c) | inst branch (8d) | inst branch taken (90) | inst branch cond (94) | inst int alu (97) | inst simd load (98) | inst ldst (9b) | 9d | 9f | l1d tlb access (a0) | l1d tlb miss (a1) | l1d cache miss ld (a3) | ld unit uop (a6) | l1d cache writeback (a8) | a9 | ac | af | b5 | l1d cache miss ld nonspec (bf) | branch cond mispred nonspec (c5) | branch mispred nonspec (cb) | cf | d5 | map dispatch bubble (d6) | dd | fetch restart (de) | e0 | ? int output thing (e9) | ea | eb | ec | ? ldst retires (ed) | ? simd retires (ee) | ? int retires (ef) | f5 | f6 | f7 | f8 | fd |
| 60025 | 120057 | 899 | 0 | 0 | 0 | 1 | 0 | 1 | 1 | 0 | 0 | 120020 | 119492 | 109460 | 25 | 60013 | 40010 | 10000 | 10000 | 30010 | 10000 | 10000 | 1079858 | 5736084 | 6125746 | 1 | 120027 | 120054 | 120054 | 111903 | 3 | 112448 | 50010 | 30020 | 20000 | 10000 | 60020 | 10000 | 10000 | 120035 | 120051 | 1 | 1 | 50021 | 10 | 9 | 10 | 40010 | 10000 | 10000 | 0 | 10 | 10002 | 1 | 1 | 10000 | 0 | 0 | 3 | 10000 | 1 | 1 | 0 | 0 | 3140 | 11 | 94 | 6 | 9 | 119669 | 40002 | 13 | 0 | 12 | 10000 | 10000 | 40010 | 120055 | 120116 | 120438 | 120055 | 120036 |
| 60024 | 120035 | 899 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 122922 | 120908 | 112383 | 891 | 60013 | 40012 | 10002 | 10002 | 32969 | 11682 | 11504 | 1137639 | 5735437 | 6124448 | 1 | 120030 | 120035 | 120035 | 111903 | 3 | 112437 | 50010 | 30020 | 20000 | 10000 | 60020 | 10000 | 10000 | 120051 | 120054 | 1 | 1 | 50021 | 10 | 9 | 10 | 40010 | 10000 | 10000 | 0 | 10 | 10000 | 0 | 1 | 10000 | 0 | 0 | 0 | 10000 | 0 | 1 | 0 | 0 | 3140 | 8 | 99 | 8 | 5 | 119672 | 40002 | 10 | 10 | 0 | 10000 | 10000 | 40010 | 120054 | 120130 | 120075 | 120056 | 120055 |
| 60024 | 120054 | 899 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 120020 | 119563 | 109461 | 25 | 60013 | 40010 | 10001 | 10000 | 30010 | 10000 | 10000 | 1079888 | 5735293 | 6125746 | 1 | 120011 | 120054 | 120035 | 111922 | 3 | 112437 | 50010 | 30020 | 20000 | 10000 | 60020 | 10000 | 10000 | 120054 | 120035 | 1 | 1 | 50021 | 10 | 9 | 10 | 40010 | 10000 | 10000 | 0 | 10 | 10000 | 0 | 1 | 10000 | 0 | 0 | 0 | 10000 | 1 | 1 | 0 | 0 | 3140 | 6 | 99 | 5 | 8 | 119650 | 40002 | 13 | 13 | 12 | 10000 | 10000 | 40010 | 120060 | 120052 | 120125 | 120036 | 120055 |
| 60024 | 120054 | 899 | 0 | 0 | 0 | 0 | 0 | 6 | 0 | 0 | 0 | 120039 | 119586 | 109459 | 25 | 60013 | 40012 | 10001 | 10000 | 30010 | 10000 | 10000 | 1079888 | 5736780 | 6124344 | 1 | 120030 | 120035 | 120035 | 111919 | 3 | 112437 | 50010 | 30020 | 20000 | 10000 | 60020 | 10000 | 10000 | 120035 | 120051 | 1 | 1 | 50021 | 10 | 9 | 10 | 40010 | 10000 | 10000 | 0 | 10 | 10000 | 0 | 1 | 10000 | 0 | 0 | 0 | 10000 | 0 | 0 | 0 | 0 | 3140 | 7 | 94 | 6 | 4 | 119650 | 40002 | 0 | 13 | 9 | 10000 | 10000 | 40010 | 120055 | 120104 | 120049 | 120060 | 120055 |
| 60024 | 120035 | 899 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 120020 | 119520 | 109465 | 25 | 60013 | 40012 | 10001 | 10000 | 30155 | 10000 | 10000 | 1079888 | 5736230 | 6124344 | 1 | 120011 | 120035 | 120054 | 111922 | 3 | 112451 | 50010 | 30020 | 20000 | 10000 | 60020 | 10000 | 10000 | 120054 | 120051 | 1 | 1 | 50021 | 10 | 9 | 10 | 40010 | 10000 | 10000 | 0 | 10 | 10000 | 0 | 1 | 10000 | 0 | 0 | 0 | 10000 | 1 | 1 | 0 | 0 | 3140 | 8 | 99 | 8 | 5 | 119672 | 40000 | 0 | 10 | 9 | 10000 | 10000 | 40010 | 120055 | 120052 | 120141 | 120037 | 120055 |
| 60024 | 120035 | 899 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 120039 | 119576 | 109550 | 45 | 60013 | 40010 | 10001 | 10000 | 30010 | 10000 | 10000 | 1079769 | 5735293 | 6125879 | 1 | 120035 | 120054 | 120054 | 111903 | 3 | 112437 | 50010 | 30020 | 20000 | 10000 | 60020 | 10000 | 10000 | 120054 | 120035 | 1 | 1 | 50021 | 10 | 9 | 10 | 40010 | 10000 | 10000 | 0 | 10 | 10000 | 0 | 1 | 10000 | 0 | 0 | 0 | 10000 | 1 | 0 | 0 | 0 | 3140 | 6 | 99 | 5 | 7 | 119672 | 40002 | 13 | 13 | 0 | 10000 | 10000 | 40010 | 120036 | 120052 | 120101 | 120439 | 120055 |
| 60024 | 120054 | 899 | 0 | 0 | 1 | 1 | 0 | 3 | 0 | 0 | 0 | 120039 | 119607 | 109459 | 25 | 60010 | 40012 | 10000 | 10000 | 30010 | 10000 | 10000 | 1079769 | 5735293 | 6124344 | 1 | 120030 | 120054 | 120054 | 111922 | 3 | 112451 | 50010 | 30020 | 20000 | 10000 | 60020 | 10000 | 10000 | 120035 | 120051 | 1 | 1 | 50021 | 10 | 9 | 10 | 40010 | 10000 | 10000 | 0 | 10 | 10000 | 0 | 1 | 10000 | 0 | 0 | 201 | 10000 | 1 | 1 | 0 | 0 | 3140 | 7 | 17 | 4 | 6 | 119672 | 40000 | 13 | 0 | 12 | 10000 | 10000 | 40010 | 120055 | 120052 | 120120 | 120058 | 120036 |
| 60024 | 120054 | 899 | 0 | 0 | 1 | 1 | 0 | 1 | 1 | 0 | 0 | 120039 | 119566 | 109461 | 25 | 60013 | 40012 | 10001 | 10000 | 30010 | 10000 | 10000 | 1079888 | 5736084 | 6125879 | 1 | 120027 | 120035 | 120035 | 111922 | 3 | 112448 | 50010 | 30020 | 20000 | 10000 | 60020 | 10000 | 10000 | 120054 | 120051 | 1 | 1 | 50021 | 10 | 9 | 10 | 40010 | 10000 | 10000 | 0 | 10 | 10000 | 0 | 1 | 10000 | 0 | 0 | 0 | 10000 | 0 | 1 | 0 | 0 | 3140 | 6 | 99 | 5 | 7 | 119672 | 40000 | 10 | 0 | 12 | 10000 | 10000 | 40010 | 120058 | 120052 | 120121 | 120037 | 120055 |
| 60024 | 120035 | 899 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 0 | 120039 | 119538 | 109460 | 25 | 60013 | 40012 | 10001 | 10000 | 30010 | 10000 | 10000 | 1079888 | 5736230 | 6125746 | 1 | 120030 | 120054 | 120054 | 111922 | 3 | 112451 | 50010 | 30020 | 20000 | 10000 | 60020 | 10000 | 10000 | 120054 | 120051 | 1 | 1 | 50021 | 10 | 9 | 10 | 40010 | 10000 | 10000 | 0 | 10 | 10000 | 0 | 1 | 10000 | 0 | 0 | 0 | 10000 | 1 | 0 | 0 | 0 | 3140 | 3 | 94 | 7 | 5 | 119650 | 40002 | 13 | 13 | 12 | 10000 | 10000 | 40010 | 120055 | 120055 | 120109 | 120038 | 120055 |
| 60024 | 120035 | 899 | 0 | 0 | 0 | 0 | 0 | 6 | 0 | 0 | 0 | 120039 | 119498 | 109444 | 25 | 60013 | 40012 | 10000 | 10000 | 30010 | 10000 | 10000 | 1079888 | 5735293 | 6125879 | 1 | 120030 | 120054 | 120054 | 111922 | 3 | 112448 | 50010 | 30020 | 20000 | 10000 | 60020 | 10000 | 10000 | 120054 | 120051 | 1 | 1 | 50021 | 10 | 9 | 10 | 40010 | 10000 | 10000 | 0 | 10 | 10000 | 0 | 0 | 10000 | 0 | 0 | 0 | 10000 | 0 | 1 | 0 | 0 | 3140 | 5 | 99 | 7 | 9 | 119650 | 40002 | 0 | 13 | 9 | 10000 | 10000 | 40010 | 120055 | 120052 | 120104 | 120079 | 120055 |
Count: 8
Code:
ldp s0, s1, [x6, #0x10] ldp s0, s1, [x6, #0x10] ldp s0, s1, [x6, #0x10] ldp s0, s1, [x6, #0x10] ldp s0, s1, [x6, #0x10] ldp s0, s1, [x6, #0x10] ldp s0, s1, [x6, #0x10] ldp s0, s1, [x6, #0x10]
mov x7, x6 mov x8, x6 mov x9, x6 mov x10, x6 mov x11, x6 mov x12, x6 mov x13, x6
(fused SUBS/B.cc loop)
Result (median cycles for code divided by count): 0.3341
| retire uop (01) | cycle (02) | 03 | 0e | 0f | 19 | 1e | 22 | 3a | 3f | 43 | 46 | 49 | 4f | 51 | schedule uop (52) | schedule int uop (53) | schedule ldst uop (55) | dispatch int uop (56) | dispatch ldst uop (58) | int uops in schedulers (59) | simd uops in schedulers (5a) | 60 | 69 | 6d | 6e | map stall dispatch (70) | map rewind (75) | map stall (76) | dispatch uop (78) | map int uop (7c) | map ldst uop (7d) | map int uop inputs (7f) | map ldst uop inputs (80) | 82 | 83 | flush restart other nonspec (84) | 85 | inst all (8c) | inst branch (8d) | inst branch taken (90) | inst branch cond (94) | inst int alu (97) | inst simd load (98) | inst ldst (9b) | 9d | 9f | l1d tlb access (a0) | l1d tlb miss (a1) | l1d cache miss ld (a3) | a5 | ld unit uop (a6) | st unit uop (a7) | l1d cache writeback (a8) | ac | af | b5 | b6 | bb | l1d cache miss ld nonspec (bf) | c2 | cf | d5 | map dispatch bubble (d6) | dd | fetch restart (de) | e0 | e7 | ea | eb | ec | ? ldst retires (ed) | ? simd retires (ee) | ? int retires (ef) | f5 | f6 | f7 | f8 | fd |
| 160205 | 26723 | 201 | 0 | 0 | 0 | 41 | 0 | 2 | 26712 | 2 | 12 | 12 | 16 | 25 | 80100 | 100 | 80000 | 100 | 80000 | 500 | 1174628 | 1 | 26702 | 26727 | 26722 | 6650 | 3 | 6685 | 80100 | 200 | 160000 | 200 | 80000 | 26732 | 26738 | 1 | 1 | 80201 | 100 | 99 | 100 | 100 | 80000 | 80000 | 0 | 100 | 80000 | 0 | 39 | 28 | 80171 | 0 | 1 | 39 | 80000 | 6 | 1 | 35 | 39 | 0 | 5110 | 1 | 16 | 1 | 1 | 26719 | 0 | 10 | 6 | 2 | 80000 | 80000 | 100 | 26723 | 26723 | 26723 | 26728 | 26728 |
| 160204 | 26727 | 200 | 0 | 1 | 0 | 45 | 0 | 0 | 26712 | 2 | 18 | 12 | 16 | 25 | 80100 | 100 | 80000 | 100 | 80000 | 500 | 1174628 | 0 | 26702 | 26727 | 26722 | 6650 | 3 | 6685 | 80100 | 200 | 160000 | 200 | 80000 | 26727 | 26730 | 1 | 1 | 80201 | 100 | 99 | 100 | 100 | 80000 | 80000 | 0 | 100 | 80000 | 0 | 39 | 0 | 80039 | 0 | 1 | 39 | 80039 | 6 | 1 | 0 | 0 | 0 | 5110 | 1 | 16 | 1 | 1 | 26733 | 0 | 10 | 10 | 4 | 80000 | 80000 | 100 | 26723 | 26742 | 26728 | 26728 | 26723 |
| 160204 | 26730 | 201 | 0 | 0 | 0 | 45 | 0 | 2 | 26712 | 2 | 12 | 18 | 12 | 25 | 80100 | 100 | 80000 | 100 | 80000 | 500 | 1174628 | 1 | 26697 | 26727 | 26727 | 6650 | 3 | 6685 | 80100 | 200 | 160000 | 200 | 80000 | 26733 | 26722 | 1 | 1 | 80201 | 100 | 99 | 100 | 100 | 80000 | 80000 | 0 | 100 | 80000 | 0 | 43 | 0 | 80000 | 0 | 0 | 35 | 80039 | 6 | 1 | 39 | 43 | 0 | 5110 | 1 | 16 | 1 | 1 | 26724 | 0 | 10 | 10 | 4 | 80000 | 80000 | 100 | 26708 | 26708 | 26708 | 26728 | 26728 |
| 160204 | 26727 | 200 | 0 | 0 | 0 | 45 | 1 | 0 | 26712 | 2 | 0 | 12 | 16 | 25 | 80100 | 100 | 80000 | 100 | 80000 | 500 | 1170107 | 1 | 26682 | 26722 | 26722 | 6650 | 3 | 6685 | 80100 | 200 | 160000 | 200 | 80000 | 26733 | 26731 | 1 | 1 | 80201 | 100 | 99 | 100 | 100 | 80000 | 80000 | 0 | 100 | 80000 | 0 | 0 | 0 | 80039 | 0 | 0 | 35 | 80039 | 6 | 1 | 35 | 43 | 0 | 5110 | 1 | 16 | 1 | 1 | 26724 | 0 | 6 | 10 | 4 | 80000 | 80000 | 100 | 26728 | 26723 | 26708 | 26728 | 26728 |
| 160204 | 26707 | 200 | 0 | 0 | 0 | 45 | 0 | 2 | 26712 | 2 | 12 | 12 | 16 | 25 | 80100 | 100 | 80000 | 100 | 80000 | 500 | 1174628 | 1 | 26697 | 26727 | 26707 | 6650 | 3 | 6685 | 80100 | 200 | 160000 | 200 | 80000 | 26732 | 26748 | 1 | 1 | 80201 | 100 | 99 | 100 | 100 | 80000 | 80000 | 0 | 100 | 80000 | 0 | 39 | 0 | 80035 | 0 | 0 | 0 | 80039 | 6 | 1 | 35 | 43 | 0 | 5110 | 1 | 16 | 1 | 1 | 26724 | 0 | 0 | 6 | 4 | 80000 | 80000 | 100 | 26728 | 26728 | 26723 | 26708 | 26728 |
| 160204 | 26727 | 200 | 0 | 0 | 0 | 45 | 0 | 2 | 26712 | 2 | 12 | 12 | 12 | 25 | 80100 | 100 | 80000 | 100 | 80000 | 500 | 1168754 | 1 | 26702 | 26727 | 26707 | 6650 | 3 | 6685 | 80100 | 200 | 160000 | 200 | 80000 | 26722 | 26722 | 1 | 1 | 80201 | 100 | 99 | 100 | 100 | 80000 | 80000 | 0 | 100 | 80000 | 0 | 0 | 0 | 80035 | 0 | 0 | 39 | 80000 | 6 | 1 | 35 | 43 | 0 | 5110 | 1 | 16 | 1 | 1 | 26724 | 0 | 0 | 10 | 4 | 80000 | 80000 | 100 | 26728 | 26728 | 26728 | 26728 | 26728 |
| 160204 | 26727 | 200 | 0 | 0 | 0 | 0 | 0 | 2 | 26712 | 3 | 12 | 18 | 12 | 25 | 80100 | 100 | 80000 | 100 | 80000 | 500 | 1168880 | 1 | 26682 | 26707 | 26727 | 6650 | 3 | 6685 | 80100 | 200 | 160000 | 200 | 80000 | 26729 | 26729 | 1 | 1 | 80201 | 100 | 99 | 100 | 100 | 80000 | 80000 | 0 | 100 | 80130 | 0 | 39 | 0 | 80035 | 0 | 0 | 40 | 80000 | 6 | 1 | 0 | 43 | 0 | 5110 | 1 | 16 | 1 | 1 | 26724 | 0 | 4 | 10 | 4 | 80000 | 80000 | 100 | 26728 | 26728 | 26708 | 26708 | 26723 |
| 160204 | 26722 | 200 | 0 | 0 | 0 | 45 | 0 | 2 | 26712 | 2 | 12 | 12 | 16 | 25 | 80100 | 100 | 80000 | 100 | 80000 | 500 | 1174628 | 1 | 26702 | 26727 | 26727 | 6650 | 3 | 6685 | 80100 | 200 | 160000 | 200 | 80000 | 26734 | 26728 | 1 | 1 | 80201 | 100 | 99 | 100 | 100 | 80000 | 80000 | 0 | 100 | 80000 | 0 | 43 | 0 | 80035 | 0 | 0 | 39 | 80039 | 6 | 1 | 51 | 39 | 0 | 5110 | 1 | 16 | 1 | 1 | 26724 | 0 | 0 | 6 | 2 | 80000 | 80000 | 100 | 26728 | 26723 | 26728 | 26728 | 26728 |
| 160204 | 26727 | 200 | 0 | 0 | 0 | 45 | 0 | 2 | 26712 | 2 | 12 | 12 | 16 | 25 | 80100 | 100 | 80000 | 100 | 80000 | 500 | 1174628 | 0 | 26702 | 26727 | 26727 | 6650 | 3 | 6685 | 80100 | 200 | 160000 | 200 | 80000 | 26729 | 26729 | 1 | 1 | 80201 | 100 | 99 | 100 | 100 | 80000 | 80000 | 0 | 100 | 80000 | 0 | 39 | 0 | 80035 | 0 | 0 | 35 | 80039 | 6 | 1 | 35 | 43 | 0 | 5110 | 1 | 16 | 1 | 1 | 26724 | 0 | 10 | 10 | 2 | 80000 | 80000 | 100 | 26723 | 26728 | 26730 | 26723 | 26730 |
| 160204 | 26727 | 200 | 0 | 0 | 0 | 45 | 0 | 0 | 26712 | 2 | 12 | 12 | 16 | 25 | 80100 | 100 | 80000 | 100 | 80000 | 500 | 1168880 | 1 | 26702 | 26707 | 26727 | 6650 | 3 | 6685 | 80100 | 200 | 160000 | 200 | 80000 | 26726 | 26738 | 1 | 1 | 80201 | 100 | 99 | 100 | 100 | 80000 | 80000 | 0 | 100 | 80000 | 0 | 39 | 0 | 80039 | 0 | 0 | 39 | 80039 | 6 | 1 | 35 | 39 | 0 | 5110 | 1 | 16 | 1 | 1 | 26719 | 0 | 10 | 10 | 2 | 80000 | 80000 | 100 | 26728 | 26723 | 26728 | 26728 | 26728 |
Result (median cycles for code divided by count): 0.3341
| retire uop (01) | cycle (02) | 03 | mmu table walk data (08) | 09 | 0e | 0f | 1e | 22 | 24 | 3a | 3f | 43 | 46 | 49 | 4f | 51 | schedule uop (52) | schedule int uop (53) | schedule ldst uop (55) | dispatch int uop (56) | dispatch ldst uop (58) | int uops in schedulers (59) | simd uops in schedulers (5a) | 5f | 60 | 69 | 6d | 6e | map stall dispatch (70) | map rewind (75) | map stall (76) | dispatch uop (78) | map int uop (7c) | map ldst uop (7d) | map int uop inputs (7f) | map ldst uop inputs (80) | 82 | 83 | flush restart other nonspec (84) | 85 | inst all (8c) | inst branch (8d) | inst branch taken (90) | inst branch cond (94) | inst int alu (97) | inst simd load (98) | inst ldst (9b) | 9d | 9f | l1d tlb access (a0) | l1d tlb miss (a1) | l1d cache miss ld (a3) | a5 | ld unit uop (a6) | st unit uop (a7) | l1d cache writeback (a8) | ac | af | b5 | b6 | bb | l1d cache miss ld nonspec (bf) | cf | l1i cache miss demand (d3) | d5 | map dispatch bubble (d6) | d9 | da | db | dd | fetch restart (de) | e0 | e7 | ea | eb | ec | ? ldst retires (ed) | ? simd retires (ee) | ? int retires (ef) | f5 | f6 | f7 | f8 | fd |
| 160025 | 26734 | 201 | 0 | 1 | 1 | 1 | 44 | 1 | 0 | 1 | 26716 | 2 | 1 | 12 | 19 | 25 | 80010 | 10 | 80000 | 10 | 80000 | 50 | 1168754 | 0 | 0 | 26702 | 26727 | 26731 | 6676 | 3 | 6711 | 80010 | 20 | 160000 | 20 | 80000 | 26707 | 26727 | 1 | 1 | 80021 | 10 | 9 | 10 | 10 | 80000 | 80000 | 0 | 10 | 80000 | 0 | 43 | 0 | 80039 | 0 | 0 | 0 | 80039 | 6 | 0 | 39 | 44 | 5020 | 0 | 14 | 16 | 10 | 0 | 0 | 11 | 7 | 26724 | 0 | 14 | 10 | 0 | 80000 | 80000 | 10 | 26708 | 26708 | 26728 | 26732 | 26728 |
| 160024 | 26727 | 200 | 0 | 0 | 0 | 1 | 44 | 1 | 0 | 1 | 26716 | 2 | 0 | 0 | 0 | 25 | 80010 | 10 | 80000 | 10 | 80000 | 50 | 1168754 | 0 | 0 | 26702 | 26707 | 26731 | 6653 | 3 | 6768 | 80010 | 20 | 160000 | 20 | 80000 | 26731 | 26727 | 1 | 1 | 80021 | 10 | 9 | 10 | 10 | 80000 | 80000 | 0 | 10 | 80000 | 0 | 43 | 0 | 80038 | 0 | 0 | 41 | 80000 | 6 | 0 | 39 | 0 | 5020 | 0 | 12 | 16 | 6 | 0 | 0 | 10 | 10 | 26734 | 0 | 14 | 14 | 7 | 80000 | 80000 | 10 | 26728 | 26708 | 26732 | 26732 | 26728 |
| 160024 | 26727 | 200 | 0 | 0 | 0 | 0 | 44 | 1 | 0 | 1 | 26712 | 2 | 12 | 1 | 16 | 25 | 80010 | 10 | 80000 | 10 | 80000 | 50 | 1174628 | 0 | 0 | 26706 | 26707 | 26731 | 6676 | 3 | 6711 | 80010 | 20 | 160000 | 20 | 80000 | 26707 | 26727 | 1 | 1 | 80021 | 10 | 9 | 10 | 10 | 80000 | 80000 | 0 | 10 | 80000 | 0 | 43 | 0 | 80000 | 0 | 0 | 38 | 80000 | 6 | 1 | 0 | 44 | 5020 | 0 | 10 | 16 | 8 | 0 | 0 | 10 | 12 | 26728 | 0 | 10 | 10 | 7 | 80000 | 80000 | 10 | 26732 | 26732 | 26728 | 26732 | 26708 |
| 160024 | 26731 | 200 | 0 | 0 | 0 | 0 | 44 | 1 | 0 | 1 | 26716 | 0 | 12 | 12 | 16 | 25 | 80010 | 10 | 80000 | 10 | 80000 | 50 | 1168880 | 0 | 0 | 26706 | 26707 | 26731 | 6676 | 3 | 6687 | 80010 | 20 | 160000 | 20 | 80000 | 26727 | 26731 | 1 | 1 | 80021 | 10 | 9 | 10 | 10 | 80000 | 80000 | 0 | 10 | 80000 | 0 | 43 | 0 | 80003 | 0 | 0 | 0 | 80039 | 6 | 0 | 38 | 44 | 5020 | 0 | 10 | 16 | 8 | 0 | 0 | 6 | 10 | 26726 | 0 | 14 | 10 | 4 | 80000 | 80000 | 10 | 26732 | 26732 | 26732 | 26708 | 26732 |
| 160024 | 26707 | 200 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 26697 | 2 | 1 | 0 | 19 | 25 | 80010 | 10 | 80000 | 10 | 80000 | 50 | 1168880 | 0 | 0 | 26706 | 26707 | 26731 | 6672 | 3 | 6687 | 80010 | 20 | 160000 | 20 | 80000 | 26731 | 26707 | 1 | 1 | 80021 | 10 | 9 | 10 | 10 | 80000 | 80000 | 0 | 10 | 80000 | 0 | 43 | 32 | 80000 | 0 | 0 | 38 | 80039 | 0 | 0 | 39 | 43 | 5020 | 0 | 10 | 16 | 8 | 0 | 0 | 8 | 13 | 26733 | 0 | 14 | 14 | 0 | 80000 | 80000 | 10 | 26708 | 26732 | 26732 | 26728 | 26708 |
| 160024 | 26731 | 200 | 0 | 0 | 0 | 0 | 44 | 0 | 0 | 0 | 26712 | 0 | 1 | 1 | 0 | 25 | 80010 | 10 | 80000 | 10 | 80000 | 50 | 1173183 | 0 | 0 | 26706 | 26731 | 26731 | 6673 | 3 | 6707 | 80010 | 20 | 160000 | 20 | 80000 | 26731 | 26727 | 1 | 1 | 80021 | 10 | 9 | 10 | 10 | 80000 | 80000 | 0 | 10 | 80000 | 0 | 43 | 0 | 80038 | 0 | 0 | 38 | 80039 | 6 | 1 | 0 | 44 | 5020 | 0 | 6 | 16 | 8 | 0 | 0 | 10 | 10 | 26724 | 0 | 14 | 14 | 0 | 80000 | 80000 | 10 | 26708 | 26732 | 26708 | 26728 | 26728 |
| 160024 | 26731 | 200 | 0 | 0 | 0 | 0 | 44 | 0 | 0 | 0 | 26692 | 2 | 1 | 0 | 16 | 25 | 80010 | 10 | 80000 | 10 | 80000 | 50 | 1168627 | 0 | 1 | 26706 | 26731 | 26727 | 6677 | 3 | 6711 | 80010 | 20 | 160000 | 20 | 80000 | 26731 | 26707 | 1 | 1 | 80021 | 10 | 9 | 10 | 10 | 80000 | 80000 | 0 | 10 | 80000 | 0 | 43 | 0 | 80038 | 0 | 0 | 39 | 80000 | 6 | 1 | 0 | 44 | 5020 | 0 | 10 | 16 | 8 | 0 | 0 | 6 | 10 | 26732 | 0 | 0 | 14 | 7 | 80000 | 80000 | 10 | 26732 | 26708 | 26728 | 26708 | 26732 |
| 160024 | 26731 | 200 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 26716 | 2 | 1 | 1 | 19 | 25 | 80010 | 10 | 80000 | 10 | 80000 | 50 | 1174628 | 0 | 0 | 26682 | 26731 | 26731 | 6676 | 3 | 6711 | 80010 | 20 | 160000 | 20 | 80000 | 26707 | 26727 | 1 | 1 | 80021 | 10 | 9 | 10 | 10 | 80000 | 80000 | 0 | 10 | 80000 | 0 | 43 | 0 | 80000 | 0 | 0 | 41 | 80039 | 0 | 1 | 39 | 44 | 5020 | 0 | 6 | 16 | 8 | 0 | 0 | 10 | 10 | 26729 | 0 | 14 | 10 | 0 | 80000 | 80000 | 10 | 26732 | 26708 | 26708 | 26732 | 26732 |
| 160024 | 26727 | 200 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 26692 | 2 | 0 | 1 | 19 | 25 | 80010 | 10 | 80000 | 10 | 80000 | 50 | 1168880 | 0 | 1 | 26702 | 26727 | 26727 | 6653 | 3 | 6711 | 80010 | 20 | 160000 | 20 | 80000 | 26731 | 26727 | 1 | 1 | 80021 | 10 | 9 | 10 | 10 | 80000 | 80000 | 0 | 10 | 80000 | 0 | 43 | 0 | 80038 | 0 | 0 | 0 | 80000 | 0 | 1 | 38 | 44 | 5020 | 0 | 6 | 16 | 8 | 0 | 0 | 10 | 10 | 26733 | 0 | 14 | 14 | 4 | 80000 | 80000 | 10 | 26732 | 26732 | 26732 | 26708 | 26903 |
| 160024 | 26707 | 200 | 0 | 0 | 1 | 0 | 45 | 1 | 0 | 1 | 26692 | 0 | 1 | 0 | 16 | 25 | 80010 | 10 | 80000 | 10 | 80000 | 50 | 1174887 | 0 | 0 | 26706 | 26731 | 26731 | 6672 | 3 | 6687 | 80010 | 20 | 160000 | 20 | 80000 | 26731 | 26707 | 1 | 1 | 80021 | 10 | 9 | 10 | 10 | 80000 | 80000 | 1 | 10 | 80000 | 0 | 43 | 0 | 80038 | 0 | 0 | 38 | 80038 | 6 | 1 | 39 | 0 | 5020 | 0 | 6 | 16 | 8 | 0 | 0 | 10 | 6 | 26753 | 0 | 14 | 14 | 4 | 80000 | 80000 | 10 | 26732 | 26732 | 26732 | 26732 | 26732 |