Firestorm: LDR (D) measurements

Code:

  ldr d0, [x6]

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 1.000

SIMD/FP unit issues: 0.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	0e	0f	1e	22	24	3a	3f	43	46	49	4f	51	schedule uop (52)	schedule ldst uop (55)	dispatch ldst uop (58)	simd uops in schedulers (5a)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map ldst uop (7d)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst simd load (98)	inst ldst (9b)	9d	l1d tlb access (a0)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	ea	eb	ec	? ldst retires (ed)	f5	f6	f7	f8	fd
1005	399	3	1	1	41	1	0	1	359	2	18	0	12	25	1000	1000	1000	14838	1	349	374	392	212	3	232	1000	1000	1000	389	389	1	1	1001	1000	1000	0	1000	39	1000	0	35	1000	6	1	35	39	73	3	16	2	2	386	6	0	2	1000	390	390	391	375	391
1004	389	2	0	1	0	1	0	1	374	2	0	0	12	25	1000	1000	1000	14774	0	364	389	389	212	3	248	1000	1000	1000	389	389	1	1	1001	1000	1000	0	1000	39	1000	0	38	1035	6	1	35	39	73	2	16	2	2	386	6	6	2	1000	390	375	375	375	390
1004	389	2	0	0	0	0	0	0	374	2	18	18	12	25	1000	1000	1000	14060	0	364	389	389	212	3	247	1000	1000	1000	389	389	1	1	1001	1000	1000	1	1000	39	1036	0	0	1000	6	0	35	0	73	2	16	2	2	386	0	0	4	1000	390	390	390	390	390
1004	389	2	1	1	41	1	0	1	374	2	18	0	16	25	1000	1000	1000	14838	0	349	389	389	197	3	249	1000	1000	1000	389	389	1	1	1001	1000	1000	1	1000	39	1035	1	35	1035	0	0	0	39	73	2	16	2	2	371	0	6	2	1000	390	392	390	390	390
1004	391	2	0	0	44	0	0	1	379	0	12	18	12	25	1000	1000	1000	14060	1	364	389	389	212	3	247	1000	1000	1000	391	374	1	1	1001	1000	1000	0	1000	0	1035	0	39	1035	6	1	35	39	73	2	16	2	2	386	6	6	0	1000	390	390	390	390	390
1004	389	2	1	0	41	0	0	1	374	2	18	18	0	25	1000	1000	1000	14838	1	364	389	374	212	3	249	1000	1000	1000	399	389	1	1	1001	1000	1000	0	1000	39	1000	1	35	1035	6	1	35	39	73	2	16	2	2	371	0	6	2	1000	375	390	390	375	390
1004	374	2	0	0	41	1	0	1	359	0	0	18	12	25	1000	1000	1000	14060	1	364	374	389	212	3	247	1000	1000	1000	389	374	1	1	1001	1000	1000	0	1000	39	1035	0	35	1000	0	0	35	39	73	2	16	2	2	386	0	6	2	1000	375	390	390	375	375
1004	374	2	0	0	41	0	0	1	359	0	0	18	12	25	1000	1000	1000	14060	1	364	374	391	212	3	247	1000	1000	1000	394	389	1	1	1001	1000	1000	0	1000	0	1035	0	35	1036	6	1	0	39	73	2	16	2	2	371	6	0	0	1000	390	375	395	390	375
1004	391	3	0	0	41	1	0	0	359	0	18	0	11	25	1000	1000	1000	14844	1	349	389	389	197	3	247	1000	1000	1000	389	391	1	1	1001	1000	1000	0	1000	39	1035	0	39	1035	6	1	35	39	73	2	16	2	2	396	6	0	2	1000	392	390	390	390	390
1004	394	3	0	0	45	1	0	1	374	0	0	0	0	25	1000	1000	1000	14982	1	369	389	374	212	3	250	1000	1000	1000	389	374	1	1	1001	1000	1000	0	1000	0	1000	0	35	1035	6	0	0	39	73	2	16	2	2	386	6	6	2	1000	389	390	375	390	390

Test 2: Latency 1->2 roundtrip

Chain cycles: 3

Code:

  ldr d0, [x6]
  fmov x0, d0
  eor x8, x8, x0
  eor x8, x8, x0
  add x6, x6, x8

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 9.0047

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	09	0e	0f	18	19	1e	1f	22	23	24	3a	3f	4d	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	69	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	ac	af	b5	l1d cache miss ld nonspec (bf)	c2	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
50205	120047	899	0	1	1	0	0	0	1	0	1	0	0	0	120020	119708	109480	25	60103	40102	10001	10000	30100	10000	10000	1079200	5736044	6138399	0	120023	0	120047	120047	113141	3	113658	50100	30200	10000	10000	60200	10000	10000	120047	120047	1	1	50201	100	99	100	40100	10000	10000	1	100	10000	1	1	10000	0	0	10000	1	1	0	0	0	3210	1	101	1	1	119646	40000	6	6	0	10000	40100	120036	120048	120118	120049	120048
50204	120047	899	0	0	0	0	0	0	1	0	1	0	0	0	120020	119594	109449	25	60100	40100	10000	10000	30100	10000	10000	1079200	5736044	6134461	0	120011	0	120047	120035	113143	29	113642	50100	30200	10000	10000	60200	10000	10000	120047	120047	1	1	50201	100	99	100	40100	10000	10000	0	100	10000	0	1	10000	7	0	10000	1	1	0	0	0	3210	1	135	1	1	119646	40000	0	6	5	10000	40100	120051	120145	120052	120048	120051
50204	120047	899	0	0	0	0	0	0	1	0	0	0	0	0	120032	119573	109464	25	60100	40102	10001	10000	30100	10000	10000	1078999	5735455	6133818	0	120023	0	120047	120047	113141	3	113636	50100	30200	10000	10000	60200	10000	10066	120035	120047	1	1	50201	100	99	100	40100	10000	10000	0	100	10000	0	1	10000	0	0	10000	1	0	0	0	0	3210	1	101	1	1	119660	40002	0	0	5	10000	40100	120048	120048	120085	120048	120048
50204	120035	900	0	0	0	0	0	0	0	0	0	0	0	0	120020	119640	109461	25	60103	40102	10001	10000	30100	10000	10000	1078862	5735455	6133818	0	120026	0	120047	120047	113143	3	113658	50100	30200	10064	10000	60200	10000	10000	120047	120047	1	1	50201	100	99	100	40100	10000	10000	0	100	10000	0	1	10000	1	0	10000	1	1	0	0	0	3210	1	135	1	1	119660	40002	6	6	8	10000	40100	120036	120080	120066	120057	120048
50204	120035	899	0	0	0	0	0	0	1	0	0	0	0	0	120020	119613	109461	25	60100	40102	10001	10000	30100	10000	10000	1078862	5736044	6133818	0	120026	0	120047	120047	113141	3	113636	50100	30200	10000	10000	60200	10000	10000	120035	120035	1	1	50201	100	99	100	40100	10000	10000	0	100	10000	0	1	10000	0	0	10000	1	1	0	0	0	3210	1	135	1	1	119660	40000	0	0	5	10000	40100	120048	120048	120103	120051	120036
50204	120047	899	0	0	0	0	0	0	1	0	0	0	0	0	120020	119576	109461	25	60100	40100	10000	10000	30100	10000	10000	1088148	5736188	6134541	0	120023	0	120035	120035	113143	17	113658	50100	30200	10000	10000	60200	10000	10000	120047	120035	1	1	50201	100	99	100	40100	10000	10000	0	100	10000	0	1	10000	0	0	10000	0	1	0	0	0	3210	1	135	0	1	119646	40000	6	6	0	10000	40100	120036	120107	120083	120048	120048
50204	120035	899	0	0	0	0	0	0	13	0	0	1	0	0	120032	119572	109461	25	60100	40100	10000	10000	30100	10000	10000	1078862	5736044	6134461	0	120023	0	120035	120047	113233	3	113636	50100	30200	10000	10000	60200	10000	10000	120035	120035	1	1	50201	100	99	100	40100	10000	10000	0	100	10000	0	1	10000	0	0	10000	0	1	0	0	0	3210	1	135	1	1	119646	40002	6	0	5	10000	40100	120095	120094	120074	120069	120048
50204	120035	899	0	0	0	0	0	0	0	0	0	0	0	0	120032	119567	109462	25	60103	40100	10000	10000	30269	10000	10000	1079200	5736044	6133818	0	120023	3	120047	120050	113141	3	113658	50100	30200	10000	10000	60200	10000	10000	120047	120047	1	1	50201	100	99	100	40100	10000	10000	0	100	10000	0	1	10000	2	0	10000	1	1	0	0	0	3210	1	101	1	1	119646	40002	6	0	5	10000	40100	120048	120048	120115	120058	120048
50204	120047	899	0	0	0	0	0	0	1	0	0	1	0	0	120032	119594	109461	25	60103	40102	10000	10000	30100	10000	10000	1078862	5736044	6134461	0	120023	0	120047	120035	113141	3	113658	50100	30200	10000	10000	60200	10000	10000	120050	120047	1	1	50201	100	99	100	40100	10000	10000	0	100	10000	0	1	10000	0	0	10000	0	1	0	0	0	3210	1	135	1	1	119685	40002	6	6	5	10000	40100	120048	120054	120111	120049	120036
50204	120047	900	1	0	0	1	0	12	4359	3080	0	0	0	0	123405	121366	110703	991	60528	40405	10071	10072	35062	11787	11678	1162716	5819988	6220481	1	120023	0	120047	120050	113560	253	115285	58143	35559	11822	11835	69536	11980	11939	122771	123587	34	1	50201	100	99	100	40100	10000	10000	1	100	10052	0	0	10039	0	131425	10052	0	0	2	0	0	4093	1	367	1	2	122204	40269	6	0	0	10000	40100	123147	123668	123440	124035	123799

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 9.0054

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	09	l2 tlb miss data (0b)	0e	0f	18	19	1e	1f	22	23	24	3a	3f	4d	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	af	b5	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	cf	d0	d5	map dispatch bubble (d6)	d9	da	db	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
50025	120057	899	1	0	0	0	0	0	0	0	2	0	1	0	0	0	120042	119518	109455	25	60013	40014	10002	10000	30010	10000	10055	1079692	5736668	6133216	0	120011	120054	120035	113172	3	113693	50010	30020	10000	10000	60020	10000	10000	120054	120051	1	1	50021	10	9	10	40010	10000	10000	0	10	10000	0	1	10000	0	0	0	10000	1	0	1	0	0	3141	0	2	107	0	0	0	2	2	119669	40000	13	0	12	10000	40010	120055	120052	120036	120055	120055
50024	120051	900	0	0	0	0	0	0	0	0	1	0	0	0	0	0	120036	119512	109541	25	60013	40012	10000	10000	30010	10000	10000	1079557	5736380	6132757	1	120027	120054	120035	113172	3	113674	50010	30020	10000	10000	60020	10000	10000	120035	120051	1	1	50022	10	9	10	40010	10000	10000	0	10	10000	0	1	10000	0	0	0	10000	0	0	1	0	0	3179	0	2	107	0	0	0	2	2	119669	40002	0	10	12	10000	40010	120055	120036	120055	120055	120055
50024	120035	899	0	0	0	0	0	0	0	0	1	0	1	0	0	0	120039	119512	109449	25	60013	40010	10001	10000	30010	10000	10000	1079629	5736380	6132757	0	120027	120054	120054	113172	3	113693	50010	30020	10000	10000	60020	10000	10000	120054	120035	1	1	50022	10	9	10	40010	10000	10000	0	10	10000	0	1	10000	0	0	0	10000	0	0	0	0	0	3141	0	2	107	0	0	0	2	5	119666	40000	10	0	12	10000	40010	120055	120055	120055	120055	120055
50024	120051	899	0	0	0	0	0	0	0	0	1	0	0	0	0	0	120039	119513	109449	25	60010	40012	10000	10000	30010	10000	10000	1079584	5736380	6133662	1	120030	120035	120035	113172	3	113674	50010	30020	10000	10000	60020	10061	10000	120035	120051	1	1	50021	10	9	10	40010	10000	10000	0	10	10000	0	1	10000	0	0	0	10000	1	0	1	0	0	3141	0	2	107	0	0	0	2	2	119669	40000	13	0	9	10000	40010	120055	120055	120036	120036	120036
50024	120054	899	0	0	0	0	0	1	0	0	0	0	0	0	0	0	120039	119512	109467	25	60013	40010	10001	10000	30010	10000	10000	1079584	5736380	6133662	0	120030	120054	120054	113172	3	113693	50010	30020	10000	10000	60020	10000	10000	120035	120051	1	1	50021	10	9	10	40010	10000	10000	0	10	10000	0	1	10000	0	0	0	10000	1	0	0	0	0	3141	0	2	107	0	0	1	3	2	119669	40002	10	13	12	10000	40010	120036	120055	120052	120105	120038
50024	120057	899	0	0	0	0	1	0	0	0	6	0	1	0	0	0	120020	119492	109449	25	60013	40012	10001	10000	30010	10000	10000	1079584	5736380	6133662	0	120033	120057	120057	113162	3	113680	50010	30020	10000	10000	60020	10000	10000	120060	120041	1	1	50021	10	9	10	40010	10000	10000	1	10	10002	1	1	10002	1	0	1	10000	1	1	1	1	2	3141	0	2	107	0	0	0	2	2	119672	40004	13	10	0	10000	40010	120058	120042	120042	120061	120061
50024	120041	899	1	0	0	0	0	1	0	0	0	0	0	0	0	0	120039	119512	109464	25	60013	40012	10001	10000	30010	10000	10000	1079517	5736380	6133662	0	120011	120054	120054	113172	3	113693	50010	30020	10000	10000	60398	10000	10000	120051	120054	1	1	50021	10	9	10	40010	10000	10000	0	10	10000	0	1	10000	0	0	0	10000	1	0	1	0	0	3141	0	5	107	0	0	0	2	2	119669	40002	10	10	9	10000	40010	120055	120052	120055	120036	120055
50024	120051	899	0	0	0	0	0	0	0	0	1	0	0	0	0	0	120039	119492	109467	25	60013	40012	10001	10000	30010	10000	10000	1079584	5735455	6133662	0	120027	120054	120079	113172	3	113693	50010	30020	10000	10000	60020	10000	10000	120054	120051	1	1	50021	10	9	10	40010	10000	10000	0	10	10000	0	1	10000	0	0	0	10000	1	0	1	0	0	3141	0	2	107	0	0	0	2	2	119669	40002	13	13	12	10000	40010	120052	120036	120036	120036	120055
50024	120054	899	0	0	0	0	0	0	0	0	1	0	0	0	0	0	120042	119499	109473	25	60013	40014	10001	10000	30010	10000	10000	1079463	5736668	6133968	0	120061	120035	120054	113172	3	113693	50010	30020	10000	10000	60020	10000	10000	120054	120051	1	1	50021	10	9	10	40010	10000	10000	0	10	10000	0	0	10000	1	0	0	10001	1	1	1	1	0	3141	0	2	107	0	0	0	2	2	119672	40004	0	13	0	10000	40010	120058	120042	120058	120061	120058
50024	120057	899	1	1	0	0	0	1	0	0	1	0	0	0	0	0	120042	119518	109470	25	60016	40012	10002	10000	30010	10000	10000	1079638	5736524	6134121	0	120027	120035	120051	113172	3	113693	50253	30020	10000	10000	60020	10000	10000	120035	120054	1	1	50021	10	9	10	40010	10000	10000	0	10	10000	0	1	10000	0	0	0	10000	1	0	1	0	0	3141	0	2	107	0	0	0	2	2	119669	40002	13	13	0	10000	40010	120055	120036	120055	120055	120036

Test 3: throughput

Count: 8

Code:

  ldr d0, [x6]
  ldr d0, [x6]
  ldr d0, [x6]
  ldr d0, [x6]
  ldr d0, [x6]
  ldr d0, [x6]
  ldr d0, [x6]
  ldr d0, [x6]

Initialization

  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.3341

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	0e	0f	1e	22	23	24	3a	3f	43	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
80205	26732	200	1	1	45	1	0	0	1	26707	2	12	18	16	25	80100	100	80000	100	80000	500	1167808	26697	26722	26722	16650	3	16690	80278	200	80000	200	80000	26727	26722	1	1	80201	100	99	100	100	80000	80000	0	100	80000	0	0	80039	0	39	80039	6	1	35	43	5178	1	16	1	1	26724	10	6	4	80000	100	26728	26728	26728	26728	26728
80204	26722	200	0	0	41	1	0	0	2	26707	2	18	12	12	25	80100	100	80000	100	80000	500	1166525	26697	26722	26727	16645	3	16832	80100	200	80000	200	80000	26722	26723	1	1	80201	100	99	100	100	80000	80000	0	100	80019	20	39	80039	0	42	80000	6	1	35	0	5110	1	16	1	1	26726	0	0	4	80000	100	26723	26708	26723	26723	26723
80204	26722	200	0	0	41	1	0	0	1	26707	2	18	12	16	25	80100	100	80000	100	80000	500	1167808	26702	26726	26722	16650	3	16795	80100	200	80000	200	80000	26722	26722	1	1	80201	100	99	100	100	80000	80000	0	100	80000	0	39	80000	0	0	80039	6	1	35	39	5110	1	16	1	1	26724	10	6	0	80000	100	26728	26728	26728	26708	26728
80204	26727	200	0	0	41	1	0	0	2	26707	2	12	0	16	25	80100	100	80000	100	80000	500	1177038	26682	26727	26722	16650	3	16781	80100	200	80000	200	80000	26722	26722	1	1	80201	100	99	100	100	80000	80000	0	100	80000	0	39	80035	1	35	80035	6	1	39	39	5110	1	16	1	1	26724	10	6	4	80000	100	26728	26728	26728	26728	26728
80204	26727	200	0	0	45	1	0	0	2	26712	2	0	12	12	25	80100	100	80000	100	80000	500	1177038	26702	26727	26722	16650	3	16787	80100	200	80000	200	80000	26727	26722	1	1	80201	100	99	100	100	80000	80000	0	100	80000	0	39	80039	0	39	80000	6	1	35	43	5110	1	16	1	1	26724	10	0	4	80000	100	26723	26723	26723	26728	26723
80204	26722	200	0	0	45	1	0	0	2	26712	2	18	12	26	25	80100	100	80000	100	80000	500	1168570	26702	26727	26727	16650	3	16784	80100	200	80000	200	80000	26727	26722	1	1	80201	100	99	100	100	80000	80000	0	100	80000	0	39	80039	0	39	80039	6	0	35	43	5110	1	16	1	1	26719	6	6	2	80000	100	26723	26728	26723	26728	26723
80204	26707	200	0	0	45	1	0	0	0	26692	2	12	18	16	25	80100	100	80000	100	80000	500	1166525	26702	26727	26727	16650	3	16794	80100	200	80000	200	80000	26722	26722	1	1	80201	100	99	100	100	80000	80000	0	100	80000	0	39	80039	0	39	80035	6	1	35	0	5110	1	16	1	1	26724	0	0	4	80000	100	26728	26728	26728	26728	26728
80204	26722	200	0	0	45	1	0	0	2	26712	2	12	12	16	25	80100	100	80000	100	80000	500	1167231	26702	26727	26727	16650	3	16776	80100	200	80000	200	80000	26727	26722	1	1	80201	100	99	100	100	80000	80000	0	100	80000	0	0	80039	0	39	80039	6	1	35	43	5110	1	16	1	1	26724	10	6	2	80000	100	26723	26723	26728	26728	26723
80204	26727	200	0	0	45	0	0	0	1	26707	2	12	12	16	25	80100	100	80000	100	80000	500	1167231	26682	26727	26727	16645	3	16794	80100	200	80000	200	80000	26727	26722	1	1	80201	100	99	100	100	80000	80000	0	100	80000	0	39	80039	0	39	80035	6	1	35	43	5110	1	16	1	1	26704	10	6	4	80000	100	26728	26708	26728	26728	26728
80204	26727	200	0	0	45	1	0	0	2	26712	0	18	18	16	25	80100	100	80000	100	80000	500	1167808	26702	26727	26730	16633	3	16684	80100	200	80000	200	80000	26728	26722	1	1	80201	100	99	100	100	80000	80000	1	100	80000	0	39	80039	0	39	80039	6	1	35	0	5110	1	16	1	1	26719	10	10	4	80000	100	26728	26728	26728	26728	26728

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.3341

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	09	l2 tlb miss data (0b)	0e	0f	18	19	1e	22	3a	3f	43	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	69	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	a5	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
80025	26726	200	0	0	0	0	1	1	0	0	0	0	1	26717	2	18	0	47	25	80010	10	80000	10	80000	50	1170204	0	26707	0	26732	26733	16677	3	16695	80010	20	80000	20	80000	26715	26714	1	1	80021	10	9	10	10	80000	80000	1	10	80000	0	39	0	80039	0	0	0	39	80039	6	1	35	43	0	0	5020	19	16	9	9	26719	10	0	4	80000	10	26729	26729	26729	26709	26728
80024	26722	200	0	0	0	0	0	0	0	0	45	0	3	26718	2	0	18	14	25	80010	10	80000	10	80000	50	1167298	0	26707	0	26732	26714	16677	3	16695	80010	20	80000	20	80000	26715	26732	1	1	80021	10	9	10	10	80000	80000	0	10	80021	19	42	0	80057	1	0	0	59	80038	6	0	19	42	19	0	5020	11	16	6	9	26725	0	0	4	80000	10	26728	26728	26728	26709	26745
80024	26728	200	0	0	0	0	0	0	0	0	41	0	2	26713	0	12	0	16	25	80010	10	80000	10	80000	50	1168843	0	26702	0	26708	26708	16672	3	16707	80010	20	80000	20	80000	26732	26732	1	1	80021	10	9	10	10	80000	80000	0	10	80020	21	42	0	80058	1	0	0	62	80039	6	0	56	0	19	0	5043	6	16	9	7	26871	6	10	4	80000	10	26945	26886	26892	26885	26874
80024	26870	201	0	1	0	0	0	0	1	1	495	0	1	27019	2	0	12	105	74	80270	10	80260	10	80356	50	1175674	0	26683	0	27135	26727	16672	3	16688	80010	20	80000	20	80000	26728	26708	1	1	80021	10	9	10	10	80000	80000	0	10	80000	0	0	0	80000	0	0	0	0	80000	0	1	35	0	0	0	5020	4	16	6	8	26729	9	9	2	80000	10	26734	26716	26820	27029	26734
80024	26737	200	1	0	0	0	0	0	0	0	21	1	1	26717	2	18	0	1	25	80010	10	80000	10	80000	50	1170204	0	26689	0	26715	26717	16677	3	16694	80010	20	80000	20	80000	26732	27182	1	1	80021	10	9	10	10	80000	80000	0	10	80020	20	42	0	80057	1	5	1	62	80038	0	1	19	0	19	0	5020	5	16	5	7	26729	0	9	2	80000	10	26733	26733	26734	26733	26733
80024	26714	200	1	1	1	0	0	0	0	0	65	1	2	26717	1	18	0	15	25	80010	10	80000	10	80000	50	1167599	0	26707	0	26714	26715	16677	3	16695	80010	20	80000	20	80000	26740	26714	1	1	80021	10	9	10	10	80000	80000	0	10	80019	21	42	0	80019	1	0	1	51	80038	0	0	57	0	19	0	5020	9	16	9	5	26729	9	0	0	80000	10	26733	26733	26733	26733	26733
80024	26715	200	1	1	1	1	1	1	0	0	65	0	2	26717	2	0	18	1	25	80010	10	80000	10	80000	50	1165822	0	26708	0	26732	26732	16677	3	16712	80010	20	80000	20	80000	26722	26722	1	1	80021	10	9	10	10	80000	80000	0	10	80000	0	39	0	80000	0	0	0	39	80039	6	1	0	0	0	0	5020	8	16	8	9	26725	10	10	0	80000	10	26728	26728	26709	26709	26719
80024	26708	200	0	0	0	0	0	0	0	0	45	1	0	26693	0	0	12	12	25	80010	10	80000	10	80000	50	1168843	0	26703	0	26728	26710	16672	3	16707	80010	20	80000	20	80000	26728	26722	1	1	80021	10	9	10	10	80000	80000	0	10	80000	0	0	0	80000	0	0	0	39	80039	0	1	35	39	0	0	5020	8	16	5	7	26705	0	6	0	80000	10	26728	26723	26709	26728	26729
80024	26708	200	0	0	0	0	0	0	0	0	45	0	0	26712	2	0	12	12	25	80010	10	80000	10	80000	50	1168843	0	26697	0	26728	26728	16672	3	16688	80010	20	80000	20	80000	26727	26722	1	1	80021	10	9	10	10	80000	80000	0	10	80000	0	0	0	80039	0	0	0	35	80039	6	1	0	0	0	0	5020	5	16	5	7	26725	10	10	4	80000	10	26728	26709	26723	26728	26728
80024	26722	200	0	0	0	0	1	0	0	0	41	1	0	26693	2	12	18	12	25	80010	10	80000	10	80000	50	1166750	0	26697	0	26708	26728	16924	3	16688	80010	20	80000	20	80000	26722	26708	1	1	80021	10	9	10	10	80000	80000	0	10	80000	0	39	0	80039	0	0	0	39	80000	0	0	39	43	0	0	5020	9	16	7	8	26705	0	10	4	80000	10	26709	26709	26709	26723	26728

LDR (D)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->2 roundtrip

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations