Firestorm: LDR (Q) measurements

Code:

  ldr q0, [x6]

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 1.000

SIMD/FP unit issues: 0.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	l2 tlb miss data (0b)	0e	0f	1e	22	23	3a	3f	43	46	49	4f	51	schedule uop (52)	schedule ldst uop (55)	dispatch ldst uop (58)	simd uops in schedulers (5a)	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map ldst uop (7d)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst simd load (98)	inst ldst (9b)	9d	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	st unit uop (a7)	a9	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	ea	eb	ec	? ldst retires (ed)	f5	f6	f7	f8	fd
1005	394	3	0	0	0	0	1	45	1	0	1	379	2	12	12	20	25	1000	1000	1000	14989	369	394	394	217	3	253	1000	1000	1000	394	394	1	1	1001	1000	1000	0	1000	0	43	1039	0	0	39	1039	6	1	39	43	0	0	73	2	16	1	1	391	10	10	4	1000	395	395	395	395	395
1004	394	2	0	0	0	0	0	45	1	0	1	379	2	12	12	16	25	1000	1000	1000	14989	369	394	394	221	3	253	1000	1000	1000	398	394	1	1	1001	1000	1000	0	1000	0	43	1039	0	0	38	1038	6	1	39	43	0	0	73	1	16	1	1	391	14	14	4	1000	395	395	395	395	395
1004	394	3	0	0	0	0	1	45	1	0	1	379	2	12	12	16	25	1000	1000	1000	15274	373	394	394	217	3	256	1000	1000	1000	394	394	1	1	1001	1000	1000	0	1000	0	43	1039	0	0	39	1039	6	1	39	43	0	0	73	1	16	1	1	391	10	10	4	1000	399	399	395	395	395
1004	394	3	0	0	0	0	0	45	1	0	1	380	2	12	12	16	25	1000	1000	1000	15018	369	394	394	217	3	259	1000	1000	1000	398	394	1	1	1001	1000	1000	0	1000	0	43	1039	0	0	39	1039	6	1	39	43	0	0	73	1	16	1	1	391	10	10	4	1000	396	395	395	395	395
1004	394	3	0	0	0	0	0	45	1	0	1	383	2	1	1	16	25	1000	1000	1000	15018	373	398	398	221	3	261	1000	1000	1000	398	394	1	1	1001	1000	1000	0	1000	0	43	1038	0	0	38	1038	6	1	39	44	0	0	73	1	16	1	1	395	10	14	7	1000	395	395	399	399	399
1004	398	3	0	0	0	0	0	44	0	1	1	379	2	1	1	19	25	1000	1000	1000	15018	369	398	398	221	3	256	1000	1000	1000	398	394	1	1	1001	1000	1000	0	1000	0	43	1038	0	0	39	1038	6	1	39	44	0	0	73	1	16	1	1	391	10	14	4	1000	395	395	399	395	399
1004	394	3	0	0	0	0	0	44	0	1	1	383	2	12	12	19	25	1000	1000	1000	15018	373	398	394	221	3	261	1000	1000	1000	394	394	1	1	1001	1000	1000	1	1000	0	43	1038	0	0	39	1039	6	1	39	43	0	0	73	1	16	1	1	391	10	10	4	1000	395	395	395	395	399
1004	394	3	0	0	0	0	0	45	0	1	1	379	2	12	12	19	25	1000	1000	1000	15034	369	398	398	221	3	252	1000	1000	1000	398	394	1	1	1001	1000	1000	0	1000	0	43	1038	0	0	39	1038	6	1	39	43	0	0	73	1	16	1	1	395	10	10	4	1000	395	395	395	399	395
1004	394	2	0	0	0	0	0	45	0	1	1	379	2	1	1	16	25	1000	1000	1000	15208	373	398	398	221	3	260	1000	1000	1000	398	394	1	1	1001	1000	1000	0	1000	0	43	1038	0	0	38	1039	6	1	39	44	0	0	73	1	16	1	1	395	14	10	4	1000	395	399	399	395	395
1004	394	3	0	0	0	1	1	45	0	1	1	383	2	1	1	19	25	1000	1000	1000	15274	373	398	398	221	3	256	1000	1000	1000	399	394	1	1	1001	1000	1000	0	1000	0	43	1040	0	0	38	1038	6	1	39	43	0	0	73	1	16	1	1	395	14	14	7	1000	399	399	399	399	399

Test 2: Latency 1->2 roundtrip

Chain cycles: 3

Code:

  ldr q0, [x6]
  fmov x0, d0
  eor x8, x8, x0
  eor x8, x8, x0
  add x6, x6, x8

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 9.0053

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk instruction (07)	mmu table walk data (08)	09	l2 tlb miss instruction (0a)	l2 tlb miss data (0b)	0e	18	19	1e	1f	22	23	24	3a	3f	4d	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	69	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	af	b5	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
50205	120053	900	1	0	1	0	0	1	1	0	0	2	0	1	0	0	0	120026	119515	109469	25	60106	40102	10002	10000	30100	10000	10000	1079053	5735750	6137397	1	120032	0	120056	120056	113151	3	113673	50100	30200	10000	10000	60200	10000	10000	120057	120053	1	1	50201	100	99	100	40100	10000	10000	0	100	10001	2	1	10002	0	1	1	10000	1	1	1	1	0	0	0	3210	4	107	2	2	119660	40004	0	6	5	10000	40100	120042	120057	120057	120057	120042
50204	120053	899	1	0	0	0	0	1	0	0	0	74	168	1	0	0	0	120026	119515	109469	25	60103	40104	10001	10000	30100	10000	10000	1079026	5736476	6136419	1	120017	0	120053	120053	113151	3	113630	50100	30200	10000	10000	60200	10000	10000	120056	120053	1	1	50201	100	99	100	40100	10000	10000	1	100	10003	2	1	10002	0	1	1	10000	1	1	0	1	1	0	0	3210	2	107	2	2	119660	40004	9	0	0	10000	40100	120086	120042	120057	120057	120057
50204	120065	900	1	0	1	0	0	0	0	0	0	1	0	0	0	0	0	120041	119512	109466	25	60106	40102	10002	10000	30100	10000	10000	1079053	5736476	6133458	1	120029	3	120041	120053	113174	3	113674	50100	30200	10000	10000	60200	10000	10000	120056	120041	1	1	50201	100	99	100	40100	10000	10000	1	100	10001	1	0	10001	0	0	1	10000	0	1	1	1	2	0	0	3210	2	135	2	2	119663	40002	0	6	0	10000	40100	120057	120057	120042	120057	120057
50204	120041	900	1	0	1	0	0	0	0	0	0	1	0	1	0	0	0	120026	119515	109466	25	60103	40104	10001	10000	30100	10000	10000	1079053	5736476	6133458	0	120017	0	120041	120053	113137	3	113673	50100	30200	10000	10000	60200	10000	10000	120056	120053	1	1	50201	100	99	100	40100	10000	10000	0	100	10004	2	1	10002	0	1	1	10000	1	1	1	1	0	0	0	3210	2	107	2	2	119668	40002	0	0	5	10000	40100	120054	120054	120042	120057	120057
50204	120053	899	1	0	0	0	0	0	0	0	0	1	0	0	0	0	0	120041	119512	109466	25	60106	40102	10002	10000	30100	10000	10000	1079026	5736332	6136419	0	120029	0	120041	120041	113148	3	113670	50100	30200	10000	10000	60200	10000	10000	120056	120053	1	1	50201	100	99	100	40100	10000	10000	0	100	10002	1	1	10002	0	1	1	10000	0	1	0	1	0	0	0	3210	2	135	3	2	119654	40004	9	0	5	10000	40100	120057	120057	120057	120054	120057
50204	120041	899	1	0	0	0	0	1	0	0	0	2	0	0	0	0	0	120038	119512	109469	25	60106	40104	10002	10000	30100	10000	10000	1079026	5735750	6136470	1	120017	0	120053	120053	113151	3	113673	50100	30200	10000	10000	60200	10000	10000	120041	120053	1	1	50201	100	99	100	40100	10000	10000	0	100	10002	3	0	10002	0	2	1	10000	1	1	0	1	0	0	0	3210	2	107	2	2	119660	40004	0	0	5	10000	40100	120057	120057	120057	120057	120042
50204	120053	899	1	0	1	0	0	1	0	0	0	7	0	0	0	0	0	120026	119515	109455	25	60103	40104	10002	10000	30100	10000	10000	1079026	5735750	6133458	1	120017	0	120053	120053	113137	28	113715	50100	30200	10000	10000	60200	10000	10000	120056	120053	1	1	50201	100	99	100	40100	10000	10000	0	100	10001	1	1	10002	0	0	1	10000	0	1	1	1	0	0	0	3210	2	107	2	2	119763	40004	9	0	5	10000	40100	120062	120042	120054	120054	120057
50204	120056	899	1	0	0	0	0	0	0	0	0	2	0	1	0	0	0	120041	119513	109469	25	60103	40104	10002	10000	30100	10000	10000	1079053	5736332	6136572	0	120017	0	120053	120056	113148	3	113673	50100	30200	10000	10000	60200	10000	10000	120056	120041	1	1	50201	100	99	100	40100	10000	10000	1	100	10002	3	1	10001	0	1	1	10000	1	1	0	1	1	0	0	3210	2	135	2	2	119654	40002	0	6	5	10000	40100	120058	120055	120042	120057	120057
50204	120041	899	1	0	0	0	0	0	0	0	0	1	0	1	0	0	0	120041	119513	109455	25	60106	40102	10002	10000	30100	10000	10000	1079053	5736332	6136572	1	120017	0	120041	120053	113137	3	113670	50100	30200	10000	10000	60200	10000	10000	120041	120053	1	1	50201	100	99	100	40100	10000	10000	1	100	10001	1	1	10001	0	0	1	10000	1	1	1	1	0	0	0	3210	2	107	7	6	121466	40197	9	0	5	10000	40100	122359	122047	120908	122230	122390
50204	122381	916	1	0	0	0	0	2	0	25	25	3311	2112	1	0	0	0	122369	119513	109469	52	60106	40102	10002	10000	30100	10000	10000	1102188	5754766	6163189	0	121813	0	122285	122143	113960	280	115108	55218	33275	11502	11458	67692	11389	11459	122625	121994	28	1	50201	100	99	100	40100	10000	10000	0	100	10036	7	1	10062	0	0	53789	10027	1	1	1	1	0	0	0	4463	3	107	2	3	120888	40190	10	10	10	10000	40100	120135	121418	121852	122336	120060

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 9.0054

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	l2 tlb miss data (0b)	0e	0f	19	1e	22	24	3f	4d	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	69	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	af	b5	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
50025	120062	899	1	1	0	0	1	0	10	0	0	120020	119509	109464	25	60013	40012	10001	10000	30010	10000	10000	1079557	5736236	6133662	1	120030	0	120054	120054	113172	3	113690	50010	30020	10000	10000	60020	10000	10000	120051	120035	1	1	50021	10	9	10	40010	10000	10000	1	10	10000	0	1	10000	0	0	0	10000	1	0	1	0	0	0	0	3140	5	107	3	3	119650	40002	13	10	0	10000	40010	120036	120055	120055	120052	120055
50024	120054	899	0	0	0	0	0	0	1	0	0	120039	119512	109449	25	60010	40012	10001	10000	30010	10000	10148	1079517	5736236	6132757	1	120030	0	120051	120051	113172	3	113674	50010	30020	10000	10000	60020	10000	10000	120054	120035	1	1	50021	10	9	10	40010	10000	10000	0	10	10000	0	1	10000	0	0	0	10000	1	0	0	0	0	0	0	3140	5	107	4	4	119650	40002	13	13	9	10000	40010	120061	120064	120042	120061	120042
50024	120060	900	1	0	0	0	0	0	7	0	0	120020	119492	109467	25	60010	40012	10001	10000	30010	10000	10000	1079584	5736236	6133662	1	120011	0	120051	120035	113169	3	113693	50010	30020	10000	10000	60020	10000	10000	120051	120035	1	1	50021	10	9	10	40010	10000	10000	0	10	10000	0	1	10000	0	0	0	10000	0	0	1	0	0	0	0	3140	2	107	2	4	119669	40002	13	13	9	10000	40010	120055	120055	120055	120052	120036
50024	120035	899	0	0	0	0	0	0	0	0	0	120036	119509	109467	25	60013	40012	10000	10000	30010	10000	10000	1079584	5736380	6133662	0	120030	0	120035	120035	113169	3	113690	50010	30020	10000	10000	60020	10000	10000	120051	120051	1	1	50021	10	9	10	40010	10000	10000	1	10	10000	0	1	10000	0	0	0	10000	1	0	1	0	0	0	0	3140	2	107	5	3	119669	40002	13	0	12	10000	40010	120052	120055	120055	120055	120055
50024	120054	899	0	0	0	0	0	0	1	0	0	120039	119492	109467	25	60010	40012	10001	10000	30010	10000	10000	1079584	5735455	6133662	0	120030	0	120035	120051	113169	3	113690	50010	30020	10000	10000	60020	10000	10000	120035	120035	1	1	50022	10	9	10	40010	10000	10000	0	10	10000	0	0	10000	1	0	0	10000	1	0	1	0	0	0	0	3140	2	107	3	4	119669	40000	10	10	9	10000	40010	120055	120036	120055	120036	120036
50024	120054	899	0	0	0	0	0	0	1	0	0	120020	119492	109449	25	60010	40010	10000	10000	30010	10000	10000	1079584	5736380	6133815	1	120030	0	120054	120035	113153	3	113693	50010	30020	10000	10000	60020	10000	10000	120051	120051	1	1	50021	10	9	10	40010	10000	10000	1	10	10000	0	1	10000	0	0	0	10000	1	0	0	0	0	0	0	3140	3	107	4	4	119669	40002	13	13	12	10000	40010	120055	120036	120055	120036	120036
50024	120035	899	0	0	0	0	0	0	1	0	0	120036	119512	109449	25	60013	40012	10001	10000	30010	10000	10000	1079584	5736236	6133815	0	120030	0	120054	120054	113172	3	113693	50010	30020	10000	10000	60020	10000	10000	120051	120093	1	1	50021	10	9	10	40010	10000	10000	0	10	10000	0	0	10000	2	0	3	10000	1	0	1	0	0	0	0	3140	4	107	3	4	119669	40007	0	10	9	10000	40010	120052	120036	120036	120055	120036
50024	120054	899	0	0	0	0	0	0	1	0	0	120039	119512	109467	25	60013	40010	10001	10000	30010	10000	10000	1079584	5735455	6133662	1	120027	0	120096	120054	113155	3	113674	50010	30501	10106	10064	60020	10000	10000	120054	120051	1	1	50021	10	9	10	40010	10000	10000	0	10	10001	1	1	10001	0	0	1	10000	1	1	1	1	1	0	0	3140	5	107	4	2	119675	40004	13	13	12	10000	40010	120061	120058	120042	120061	120061
50024	120060	899	1	1	1	0	0	0	1	0	0	120020	119512	109464	25	60013	40010	10000	10000	30010	10000	10000	1079526	5736236	6132757	1	120035	0	120054	120054	113153	3	113693	50010	30020	10000	10000	60020	10000	10000	120039	120035	1	1	50021	10	9	10	40010	10000	10000	1	10	10000	0	1	10000	0	0	0	10000	1	0	1	0	0	0	0	3140	3	107	4	4	119669	40002	13	13	12	10000	40010	120036	120055	120055	120055	120036
50024	120054	899	0	0	0	0	0	0	1	0	0	120039	119515	109470	25	60016	40012	10002	10000	30010	10000	10000	1079638	5736524	6133216	1	120036	0	120041	120060	113178	22	113680	50010	30020	10000	10000	60020	10000	10000	120041	120049	1	1	50021	10	9	10	40010	10000	10000	0	10	10001	2	1	10001	0	0	1	10000	1	1	1	1	0	0	0	3140	4	107	3	3	119650	40000	0	13	12	10000	40010	120055	120055	120055	120052	120055

Test 3: throughput

Count: 8

Code:

  ldr q0, [x6]
  ldr q0, [x6]
  ldr q0, [x6]
  ldr q0, [x6]
  ldr q0, [x6]
  ldr q0, [x6]
  ldr q0, [x6]
  ldr q0, [x6]

Initialization

  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.3341

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk instruction (07)	mmu table walk data (08)	09	l2 tlb miss data (0b)	0e	0f	18	19	1e	1f	22	23	3a	3f	43	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst ldst (9b)	9f	l1d tlb access (a0)	l1d cache miss ld (a3)	a5	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
80205	26732	200	1	0	1	1	0	0	0	0	0	65	0	0	0	3	26717	2	18	18	15	25	80100	100	80000	100	80000	500	1167026	1	26717	26727	26727	16650	3	16685	80100	200	80000	200	80000	26727	26722	2	1	80201	100	99	100	100	80000	80000	100	80000	39	0	80035	0	0	39	80039	6	1	35	0	0	5110	1	16	1	1	26719	0	10	6	0	80000	100	26728	26728	26728	26728	26735
80204	26722	201	0	0	0	0	0	0	0	0	0	45	0	1	0	2	26716	0	12	12	16	25	80100	100	80000	100	80000	500	1167231	1	26702	26727	26727	16650	3	16685	80100	200	80000	200	80000	26727	26707	1	1	80201	100	99	100	100	80000	80000	100	80000	39	0	80039	0	0	42	80039	6	1	35	43	0	5110	1	16	1	1	26719	0	10	10	4	80000	100	26728	26708	26728	26728	26708
80204	26727	200	0	0	0	0	0	0	1	0	0	41	0	0	0	2	26712	2	18	18	16	25	80100	100	80000	100	80000	500	1165789	1	26702	26727	26727	16650	3	16680	80100	200	80000	200	80000	26722	26722	1	1	80201	100	99	100	100	80000	80000	100	80000	39	0	80039	0	0	39	80000	6	1	39	43	0	5110	1	16	1	1	26719	0	10	10	4	80000	100	26728	26728	26728	26723	26728
80204	26727	200	0	0	0	0	0	0	0	0	0	41	0	0	0	1	26712	2	18	12	16	25	80100	100	80000	100	80000	500	1167231	1	26702	26727	26727	16630	3	16685	80100	200	80000	200	80000	26707	26722	1	1	80201	100	99	100	100	80000	80000	100	80000	39	0	80039	0	0	39	80035	6	1	35	39	0	5110	1	16	1	1	26719	0	10	6	2	80000	100	26728	26708	26708	26728	26728
80204	26727	200	0	0	0	0	0	1	1	0	0	41	0	0	0	2	26712	2	18	18	16	25	80100	100	80000	100	80000	500	1167231	1	26702	26727	26707	16650	3	16685	80100	200	80000	200	80000	26727	26722	1	1	80201	100	99	100	100	80000	80000	100	80000	39	0	80039	0	0	39	80039	0	1	39	43	0	5110	1	16	1	1	26728	0	10	10	0	80000	100	26728	26728	26728	26728	26728
80204	26727	200	0	0	0	0	0	1	0	0	0	41	0	0	0	0	26712	2	18	12	18	25	80100	100	80000	100	80000	500	1167808	1	26697	26728	26727	16650	3	16685	80100	200	80000	200	80000	26722	26722	1	1	80201	100	99	100	100	80000	80000	100	80000	39	0	80039	1	4	38	80039	6	1	0	43	0	5110	1	16	1	1	26737	0	10	10	4	80000	100	26708	26728	26733	26728	26735
80204	26722	200	0	0	0	0	0	1	1	0	0	41	0	0	1	0	26707	0	18	18	16	25	80100	100	80000	100	80000	500	1166525	1	26702	26751	26727	16645	3	16685	80100	200	80000	200	80000	26727	26722	1	1	80201	100	99	100	100	80000	80000	100	80000	39	0	80039	0	2	48	80039	6	1	39	43	0	5110	1	16	1	1	26707	0	10	10	0	80000	100	26728	26728	26728	26728	26728
80204	26727	200	0	0	0	0	0	1	0	0	0	45	0	0	1	2	26712	2	18	12	12	25	80100	100	80000	100	80000	500	1167808	0	26697	26722	26727	16645	3	16685	80100	200	80000	200	80000	26727	26722	1	1	80201	100	99	100	100	80000	80000	100	80000	43	0	80035	0	0	39	80035	6	1	35	43	0	5110	1	16	1	1	26719	0	10	6	0	80000	100	26728	26728	26728	26728	26728
80204	26707	200	0	0	0	0	0	0	0	0	0	45	0	0	0	2	26712	2	12	12	16	25	80100	100	80000	100	80000	500	1167231	1	26710	26727	26727	16650	3	16680	80100	200	80000	200	80000	26722	26722	1	1	80201	100	99	100	100	80000	80000	100	80000	39	0	80000	0	0	39	80035	6	1	0	43	0	5110	1	16	1	1	26724	0	10	6	2	80000	100	26728	26723	26723	26728	26728
80204	26727	200	0	0	0	0	0	1	0	0	0	45	0	0	1	2	26712	2	18	12	16	25	80100	100	80000	100	80000	500	1167231	1	26703	26727	26727	16650	3	16685	80100	200	80000	200	80000	26722	26722	1	1	80201	100	99	100	100	80000	80000	100	80000	39	0	80039	0	0	35	80039	6	1	39	43	0	5110	1	16	1	1	26719	0	10	10	4	80000	100	26728	26728	26728	26723	26727

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.3341

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk instruction (07)	mmu table walk data (08)	09	l2 tlb miss data (0b)	0e	0f	19	1e	1f	22	24	3a	3f	43	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	5f	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	a5	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
80025	26736	200	1	0	1	1	1	0	0	0	66	0	1	0	1	26721	3	7	7	0	25	80010	10	80000	10	80000	50	1168286	0	1	26712	26736	26737	16681	3	16716	80010	20	80000	20	80000	26737	26736	1	1	80021	10	9	10	10	80000	80000	0	10	80020	20	43	0	80019	0	0	0	64	80040	6	1	59	43	19	0	5020	4	16	4	2	26734	13	13	0	80000	10	26737	26737	26737	26737	26750
80024	26715	200	1	0	1	1	1	0	0	0	67	0	1	0	3	26722	2	7	7	19	25	80010	10	80000	10	80000	50	1168283	0	1	27119	26764	26737	16681	3	16716	80010	20	80000	20	80000	26736	26737	1	1	80021	10	9	10	10	80000	80000	0	10	80020	19	0	0	80059	1	0	1	60	80041	6	1	19	43	18	1	5020	4	16	5	4	26733	13	13	5	80000	10	26737	26737	26737	26741	26760
80024	26755	200	1	0	0	0	0	1	0	0	67	0	0	0	3	26721	3	7	7	18	25	80010	10	80000	10	80000	50	1158230	0	1	26712	26740	26753	17064	3	16695	80010	20	80000	20	80000	26736	26736	1	1	80021	10	9	10	10	80000	80000	0	10	80020	19	43	0	80059	1	0	1	21	80040	6	1	58	43	19	1	5020	4	16	2	4	26733	0	0	5	80000	10	26716	26737	26737	26737	26814
80024	26739	200	1	0	0	1	1	0	0	0	67	0	1	0	2	27312	2	7	0	19	25	80010	10	80000	10	80000	50	1167791	0	1	26711	26737	26714	16681	3	16695	80010	20	80000	20	80000	26715	26736	1	1	80021	10	9	10	10	80000	80000	0	10	80019	19	43	0	80018	0	0	1	61	80000	6	1	58	43	19	1	5020	5	16	2	6	26733	13	13	0	80000	10	26737	26737	26738	26716	26737
80024	26736	200	1	0	1	1	1	0	0	0	67	0	1	0	2	26728	3	0	7	1	25	80010	10	80000	10	80000	50	1169050	0	1	26717	26750	26718	16664	32	16719	80010	20	80000	20	80000	26717	26737	2	1	80021	10	9	10	10	80000	80000	0	10	80020	19	45	122	80060	1	0	0	63	80039	6	1	58	45	19	0	5066	2	16	2	4	26733	13	13	0	80000	10	26738	26738	26738	26716	26737
80024	26736	200	1	0	1	1	0	0	0	0	297	0	1	0	2	26722	2	7	7	1	25	80010	10	80000	10	80000	50	1169050	0	1	26711	26736	26736	16681	3	16716	80010	20	80000	20	80000	26737	26736	1	1	80021	10	9	10	10	80000	80000	0	10	80021	20	45	0	80019	1	0	1	63	80039	0	1	58	43	19	0	5020	4	16	6	4	26734	13	13	0	80000	10	26716	26738	26738	26715	26737
80024	26736	200	1	0	1	1	1	0	0	0	123	0	1	0	2	26699	3	7	0	19	25	80010	10	80000	10	80000	50	1171764	0	1	26715	26837	26721	16681	3	16695	80010	20	80000	20	80000	26737	26715	1	1	80021	10	9	10	10	80000	80000	0	10	80019	20	43	0	80059	0	0	0	61	80000	6	0	59	43	19	0	5020	2	16	2	4	26734	13	0	5	80000	10	26738	26716	26747	27228	26928
80024	26739	207	1	0	1	1	1	1	1	0	70	0	0	0	3	26722	2	0	7	19	25	80010	10	80000	10	80000	50	1168472	0	1	26690	26714	26736	16681	3	16716	80010	20	80000	20	80000	26737	26736	1	1	80021	10	9	10	10	80000	80000	0	10	80020	20	45	0	80059	0	0	2	21	80041	6	1	58	43	19	0	5020	2	16	2	4	26733	13	13	0	80000	10	26716	26737	26737	26716	26740
80024	26736	200	1	1	1	1	1	1	0	0	66	0	0	0	3	26731	3	7	7	0	25	80010	10	80000	10	80000	50	1173975	0	1	26715	26784	26987	16697	3	16695	80010	20	80000	20	80000	26737	26714	1	1	80021	10	9	10	10	80000	80000	0	10	80021	19	43	0	80059	0	0	2	21	80040	6	1	59	43	19	0	5020	2	16	4	2	26733	13	13	5	80000	10	26738	26737	26738	26737	26737
80024	26736	200	1	0	1	1	1	1	1	0	66	0	0	0	3	26721	0	7	7	20	25	80010	10	80000	10	80000	50	1167219	0	1	26712	26745	26715	16692	3	16694	80010	20	80000	20	80000	26736	26737	1	1	80021	10	9	10	10	80000	80000	0	10	80020	19	43	0	80019	1	0	0	21	80039	0	1	59	43	19	2	5020	4	16	6	4	26734	0	0	5	80000	10	26875	26744	26750	26737	26737

LDR (Q)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->2 roundtrip

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations