Firestorm: LDR (S) measurements

Code:

  ldr s0, [x6]

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 1.000

SIMD/FP unit issues: 0.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	0e	0f	1e	22	24	3a	3f	43	46	49	4f	51	schedule uop (52)	schedule ldst uop (55)	dispatch ldst uop (58)	simd uops in schedulers (5a)	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map ldst uop (7d)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst simd load (98)	inst ldst (9b)	9d	l1d tlb access (a0)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	ea	eb	ec	? ldst retires (ed)	f5	f6	f7	f8	fd
1005	398	3	0	0	45	1	0	1	379	2	18	12	16	25	1000	1000	1000	14838	364	394	389	217	3	252	1000	1000	1000	394	391	1	1	1001	1000	1000	0	1000	39	1039	0	39	1039	6	1	35	43	73	1	16	1	1	386	6	6	2	1000	395	395	390	395	395
1004	394	3	0	0	45	1	0	1	379	2	18	18	16	25	1000	1000	1000	15037	364	389	389	217	3	249	1000	1000	1000	394	389	1	1	1001	1000	1000	0	1000	39	1036	0	39	1035	6	1	35	43	73	1	16	1	1	391	10	6	4	1000	395	395	396	395	390
1004	394	3	0	0	45	1	0	1	382	2	12	12	16	25	1000	1000	1000	14989	364	394	389	217	3	247	1000	1000	1000	394	410	1	1	1001	1000	1000	0	1000	39	1039	0	39	1039	6	1	35	43	73	1	16	1	1	391	10	6	2	1000	395	395	390	390	395
1004	394	2	1	1	45	0	0	2	379	2	18	18	46	25	1000	1000	1000	15018	366	394	389	216	3	247	1000	1000	1000	394	389	1	1	1001	1000	1000	0	1000	39	1039	0	39	1039	6	1	35	43	73	1	16	1	1	391	10	6	2	1000	395	397	395	390	395
1004	394	3	1	0	45	1	0	2	379	2	12	12	16	25	1000	1000	1000	14989	369	394	394	217	3	252	1000	1000	1000	394	389	1	1	1001	1000	1000	0	1000	39	1039	0	39	1035	6	1	35	39	73	1	16	1	1	391	10	10	4	1000	395	395	395	395	395
1004	394	2	0	0	45	0	0	2	379	2	18	12	12	25	1000	1000	1000	14989	369	394	391	216	3	252	1000	1000	1000	394	389	1	1	1001	1000	1000	0	1000	39	1039	0	39	1035	6	1	35	43	73	1	16	1	1	391	10	6	2	1000	395	395	395	397	395
1004	389	3	1	0	45	0	0	1	379	2	12	18	16	25	1000	1000	1000	14838	369	394	394	217	3	247	1000	1000	1000	391	391	1	1	1001	1000	1000	0	1000	39	1035	0	39	1039	6	1	35	39	73	1	16	1	1	386	6	6	2	1000	390	390	392	390	390
1004	389	3	0	0	42	0	0	2	374	2	18	18	16	25	1000	1000	1000	14838	364	389	389	217	3	252	1000	1000	1000	389	389	1	1	1001	1000	1000	0	1000	39	1035	0	35	1035	6	1	35	39	73	1	16	1	1	386	6	6	4	1000	399	395	397	395	390
1004	394	3	0	0	45	1	0	2	379	2	18	18	16	25	1000	1000	1000	14838	369	394	394	216	3	252	1000	1000	1000	394	391	1	1	1001	1000	1000	0	1000	39	1039	0	39	1039	6	1	39	39	73	1	16	1	1	391	10	6	4	1000	395	395	395	395	395
1004	389	3	0	0	45	0	0	2	379	2	12	12	16	25	1000	1000	1000	14989	369	394	394	217	3	252	1000	1000	1000	394	389	1	1	1001	1000	1000	0	1000	39	1039	0	39	1039	6	1	35	43	73	1	16	1	1	391	10	10	4	1000	395	395	395	392	395

Test 2: Latency 1->2 roundtrip

Chain cycles: 3

Code:

  ldr s0, [x6]
  fmov x0, d0
  eor x8, x8, x0
  eor x8, x8, x0
  add x6, x6, x8

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 9.0050

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	l2 tlb miss data (0b)	0e	0f	18	19	1e	1f	22	23	3a	3f	4d	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	69	6b	6d	6e	map stall dispatch (70)	int prf full (71)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	af	b5	l1d cache miss ld nonspec (bf)	c2	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
50205	120057	899	0	0	0	0	0	0	0	0	0	0	0	120039	119493	109550	25	60103	40102	10001	10000	30100	10000	10000	1079035	5736380	6136317	1	120030	0	120054	120051	113149	0	3	113671	50100	30200	10000	10000	60200	10000	10000	120054	120035	1	1	50201	100	99	100	40100	10000	10000	0	100	10000	0	1	10000	0	0	0	10000	1	1	0	0	3211	4	107	4	4	119661	40002	13	10	12	10000	40100	120055	120055	120055	120055	120055
50204	120051	899	0	0	0	0	0	0	1	0	1	0	0	120039	119518	109449	25	60100	40102	10001	10000	30100	10000	10000	1079134	5751341	6138725	1	120587	0	120054	120054	113149	0	15	113671	50100	30363	10000	10000	60200	10000	10109	120150	120051	1	1	50201	100	99	100	40100	10000	10000	0	100	10000	0	1	10002	0	0	12310	10010	1	0	0	0	3294	8	107	4	4	119661	40018	13	10	12	10000	40100	120163	120052	120054	120148	120052
50204	120054	899	0	1	0	0	0	0	0	0	0	0	0	120126	119692	109467	52	60103	40102	10003	10000	30100	10000	10147	1079035	5736380	6138804	1	120365	0	120054	120054	113521	0	3	113671	50100	30200	10000	10000	60200	10000	10000	120057	120051	1	1	50201	100	99	100	40100	10000	10000	0	100	10000	0	1	10000	0	0	0	10000	1	1	0	0	3211	4	107	4	4	119661	40000	13	13	12	10000	40100	120052	120055	120052	120052	120052
50204	120054	899	0	0	0	0	0	0	1	0	1	0	0	120039	119518	109449	25	60103	40102	10001	10000	30100	10000	10000	1079080	5736380	6136317	0	120030	0	120054	120054	113149	0	3	113671	50100	30200	10000	10000	61492	10000	10000	120052	120051	1	1	50201	100	99	100	40100	10000	10000	0	100	10000	0	1	10000	0	0	213	10000	1	0	0	0	3211	4	107	4	4	119661	40002	10	10	9	10000	40100	120055	120055	120036	120055	120093
50204	120051	899	0	0	0	1	0	0	1	0	0	0	0	120080	119510	109467	25	60103	40102	10001	10000	30100	10000	10000	1079035	5736380	6136317	1	120030	0	120054	120054	113149	0	3	113671	50100	30200	10000	10000	60200	10000	10000	120054	120051	1	1	50201	100	99	100	40100	10000	10000	0	100	10000	0	1	10000	2	0	0	10000	1	1	0	0	3211	4	107	4	4	119661	40002	13	10	9	10000	40100	120055	120055	120052	120036	120036
50204	120054	899	0	0	0	0	0	0	1	0	0	0	0	120045	119513	109467	25	60103	40102	10001	10000	30100	10000	10000	1079035	5736380	6136317	1	120011	0	120051	120095	113149	0	3	113671	50100	30200	10000	10000	60200	10000	10000	120051	120051	1	1	50201	100	99	100	40100	10000	10000	0	100	10000	0	1	10000	0	0	0	10000	1	1	0	0	3211	4	107	4	4	119658	40002	13	13	12	10000	40100	120055	120036	120055	120052	120052
50204	120054	899	0	0	0	0	0	0	1	0	0	0	0	120020	119510	109467	25	60103	40102	10001	10000	30100	10000	10000	1079035	5736380	6134461	1	120030	0	120054	120054	113149	0	3	113658	50100	30200	10000	10000	60200	10000	10000	120051	120051	1	1	50201	100	99	100	40100	10000	10000	0	100	10000	0	1	10000	0	0	0	10000	1	1	0	0	3211	4	107	4	4	119658	40002	13	13	12	10000	40100	120071	120068	120055	120052	120055
50204	120035	899	0	0	0	0	0	0	7	0	0	0	0	120036	119513	109467	25	60103	40120	10001	10000	30100	10000	10000	1079008	5736380	6136317	1	120030	0	120054	120054	113149	0	3	113668	50100	30200	10000	10000	60200	10000	10000	120054	120051	1	1	50201	100	99	100	40100	10000	10000	0	100	10000	0	1	10000	0	0	0	10000	1	1	0	0	3211	4	107	5	5	119661	40002	13	13	12	10000	40100	120055	120055	120052	120055	120055
50204	120035	899	0	0	0	0	0	0	1	0	0	0	0	120039	119513	109467	25	60103	40102	10001	10000	30100	10000	10000	1079035	5736380	6136317	1	120011	0	120054	120054	113149	0	3	113671	50100	30200	10000	10000	61506	10000	10000	120059	120051	1	1	50201	100	99	100	40100	10000	10000	0	100	10000	0	1	10000	0	0	30	10000	1	1	0	0	3211	4	107	4	4	119661	40002	13	13	12	10000	40100	120055	120055	120055	120055	120036
50204	120054	899	0	0	1	1	0	0	1	0	1	0	0	120039	119493	109449	25	60103	40102	10001	10000	30100	10000	10000	1079035	5736380	6134461	0	120030	0	120054	120051	113149	0	3	113671	50100	30200	10000	10000	60200	10000	10000	120035	120051	1	1	50201	100	99	100	40100	10000	10000	1	100	10000	0	0	10000	0	0	0	10000	1	1	0	0	3442	4	107	4	4	119646	40009	0	10	12	10000	40100	120055	120038	120055	120036	120055

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 9.0048

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	09	l2 tlb miss data (0b)	0e	0f	18	19	1e	1f	22	23	24	3a	3f	4d	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	b5	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	cf	d0	d5	map dispatch bubble (d6)	da	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
50025	120041	899	1	1	1	0	0	0	0	0	5	0	0	0	0	0	120050	119499	109455	25	60013	40014	10002	10000	30010	10000	10000	1079602	5736476	6133764	0	120032	120053	120056	113171	3	113695	50010	30020	10000	10000	60020	10000	10000	120041	120053	1	1	50021	10	9	10	40010	10000	10000	0	10	10002	2	1	10003	0	0	2	1	10000	1	1	1	1	0	3140	0	3	107	6	3	3	119656	40004	9	0	8	10000	40010	120057	120057	120057	120042	120057
50024	120041	899	1	0	0	1	0	0	0	0	2	0	1	0	0	0	120041	119514	109455	25	60016	40014	10002	10000	30010	10000	10000	1080978	5737628	6133764	0	120032	120056	120056	113176	3	113692	50010	30020	10000	10000	60020	10000	10000	120056	120041	1	1	50022	10	9	10	40010	10000	10000	0	10	10002	1	1	10002	0	0	2	1	10000	1	1	1	1	1	3140	0	4	107	4	3	3	119671	40004	9	9	8	10000	40010	120057	120057	120057	120057	120042
50024	120056	899	1	1	1	1	1	1	0	0	2	0	0	0	0	0	120041	119514	109466	25	60013	40014	10001	10000	30010	10000	10000	1079463	5735750	6133764	1	120029	120053	120053	113171	3	113695	50010	30020	10000	10000	60020	10000	10000	120056	120053	1	1	50021	10	9	10	40010	10000	10000	0	10	10002	1	0	10004	0	2	0	1	10000	1	1	0	1	0	3140	0	4	107	6	3	3	119671	40004	6	9	8	10000	40010	120042	120042	120057	120057	120054
50024	120053	899	1	1	1	0	0	0	0	0	23	0	1	0	0	0	120026	119514	109469	25	60016	40012	10002	10000	30010	10000	10000	1079575	5735750	6133764	0	120029	120053	120056	113159	3	113695	50010	30020	10000	10000	60020	10000	10000	120041	120041	1	1	50021	10	9	10	40010	10000	10000	0	10	10002	2	0	10001	0	0	0	1	10000	1	1	1	1	0	3140	0	4	107	6	4	3	119671	40004	9	6	8	10000	40010	120042	120042	120057	120057	120057
50024	120053	899	1	0	1	0	1	0	0	0	2	0	0	0	0	0	120041	119499	109466	25	60016	40012	10002	10000	30010	10000	10000	1079602	5735750	6133764	0	120029	120041	120056	113159	3	113695	50010	30020	10000	10000	60020	10000	10000	120056	120053	1	1	50021	10	9	10	40010	10000	10000	1	10	10001	2	1	10001	0	0	0	7	10000	1	1	0	1	1	3140	0	4	17	5	3	3	119656	40002	9	6	8	10000	40010	120054	120057	120042	120057	120054
50024	120053	899	1	0	0	0	0	0	0	0	2	0	0	0	0	0	120041	119519	109469	25	60016	40014	10002	10000	30010	10000	10000	1079602	5736332	6133764	0	120032	120056	120056	113174	3	113695	50010	30020	10000	10000	60020	10000	10000	120056	120053	1	1	50021	10	9	10	40010	10000	10000	0	10	10001	1	1	10001	0	0	1	1	10000	0	1	1	1	0	3140	0	3	107	5	2	3	119671	40004	9	6	8	10000	40010	120057	120042	120057	120057	120042
50024	120041	899	1	1	1	0	0	0	0	0	2	0	0	0	0	0	120041	119514	109455	25	60013	40014	10002	10000	30010	10000	10000	1079463	5737324	6136244	0	120032	120056	120056	113174	3	113695	50010	30020	10000	10000	60020	10000	10000	120041	120053	1	1	50021	10	9	10	40010	10000	10000	0	10	10001	1	1	10003	0	0	2	1	10000	0	1	1	1	0	3140	0	2	107	6	3	3	119671	40004	0	0	8	10000	40010	120042	120057	120042	120054	120057
50024	120056	899	1	0	0	0	0	0	0	0	2	0	1	0	0	0	120041	119516	109469	25	60016	40012	10001	10000	30010	10000	10000	1079463	5736332	6133764	0	120029	120041	120056	113174	3	113680	50010	30020	10000	10000	60020	10000	10000	120056	120041	1	1	50021	10	9	10	40010	10000	10000	0	10	10001	2	0	10001	0	1	1	1	10000	1	1	1	1	0	3140	0	2	107	5	2	3	119784	40004	9	0	8	10000	40010	120041	120048	120048	120048	120048
50024	120048	1015	0	0	0	0	1	0	0	0	1	0	0	0	0	1	120042	119515	109473	25	60016	40012	10001	10000	30010	10000	10000	1079638	5736524	6133968	0	120036	120041	120057	113159	3	113696	50010	30020	10000	10000	60020	10000	10000	120041	120041	1	1	50021	10	9	10	40010	10000	10000	0	10	10002	1	1	10002	0	0	0	1	10000	1	1	0	1	1	3140	0	10	107	0	2	3	119666	40002	13	0	12	10000	40010	120055	120055	120055	120055	120055
50024	120035	899	0	0	0	0	0	1	0	0	12	0	0	0	0	0	120036	119492	109467	25	60013	40012	10001	10000	30010	10000	10000	1079517	5736236	6133662	0	120032	120053	120053	113174	3	113692	50010	30020	10065	10000	60020	10000	10000	120053	120099	1	1	50021	10	9	10	40010	10000	10000	0	10	10001	1	1	10003	0	1	0	1	10000	1	1	0	1	0	3140	0	4	107	0	2	3	119671	40004	9	6	8	10000	40010	120042	120042	120057	120054	120057

Test 3: throughput

Count: 8

Code:

  ldr s0, [x6]
  ldr s0, [x6]
  ldr s0, [x6]
  ldr s0, [x6]
  ldr s0, [x6]
  ldr s0, [x6]
  ldr s0, [x6]
  ldr s0, [x6]

Initialization

  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.3341

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	09	l2 tlb miss data (0b)	0e	0f	18	19	1e	1f	22	23	3a	3f	43	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	a5	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	c2	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
80205	26727	200	0	0	1	0	0	0	0	0	45	0	1	0	1	26712	2	12	12	16	25	80100	100	80000	100	80016	500	1167303	1	26682	26727	26727	16655	6	16679	80116	200	80024	200	80024	26730	26724	1	1	80201	100	99	100	100	80000	80000	0	100	80000	0	0	0	80039	0	0	39	80039	6	1	39	43	0	1	1	1	5118	0	16	0	1	26729	0	10	10	4	80000	100	26731	26711	26728	26728	26728
80204	26727	200	0	0	0	0	0	0	0	0	45	0	1	0	1	26712	2	12	0	16	25	80100	100	80000	100	80014	500	1167303	0	26702	26727	26707	16655	6	16659	80114	200	80024	200	80024	26707	26803	1	1	80201	100	99	100	100	80000	80000	0	100	80000	0	43	0	80039	0	0	39	80039	6	1	39	43	0	1	1	1	5118	0	16	0	0	26724	0	0	10	4	80000	100	26728	26728	26728	26728	26728
80204	26707	200	0	0	0	0	0	0	0	0	0	0	1	0	1	26712	2	12	12	16	25	80100	100	80000	100	80014	500	1167303	1	26702	26727	26727	16655	6	16679	80115	200	80024	200	80024	26733	26734	1	1	80201	100	99	100	100	80000	80000	0	100	80000	0	43	0	80039	0	0	39	80000	6	1	39	43	0	1	1	1	5118	0	16	0	0	26724	0	10	10	0	80000	100	26728	26728	26728	26728	26708
80204	26727	208	0	0	0	0	0	0	0	0	45	0	0	0	1	26712	2	0	12	16	25	80100	100	80000	100	80015	500	1167303	1	26702	26727	26727	16655	6	16679	80115	200	80024	200	80024	26737	26809	1	1	80201	100	99	100	100	80000	80000	0	100	80000	0	43	0	80039	0	0	42	80039	0	1	39	43	0	1	1	1	5118	0	16	0	0	26724	0	0	10	4	80000	100	26728	26728	26728	26728	26728
80204	26727	200	0	0	0	0	0	0	0	0	45	0	0	0	0	26712	0	12	12	16	25	80100	100	80000	100	80015	500	1167303	1	26702	26707	26727	16635	6	16659	80115	200	80024	200	80024	26719	26742	1	1	80201	100	99	100	100	80000	80000	0	100	80000	0	43	0	80039	0	0	0	80039	6	0	39	43	0	1	1	1	5118	0	16	0	0	26704	0	10	10	0	80000	100	26728	26708	26728	26728	26728
80204	26727	200	0	0	0	0	0	0	0	0	54	0	1	0	0	26712	2	12	12	678	265	81406	100	80520	106	81977	532	1222198	0	28055	28208	28222	17744	79	17959	82082	200	82332	202	81959	28068	27917	11	1	80201	100	99	100	100	80000	80000	0	100	81302	0	43	315	81339	0	2	5699	80819	6	1	39	43	4	1	0	0	5267	3	73	3	1	27681	1	10	14	4	80000	100	27662	27627	27778	27617	27778
80204	27620	200	0	1	0	0	0	0	6	7	972	352	1	0	1	27735	2	12	12	541	196	81012	110	80910	108	81246	500	1200635	1	27645	27749	27816	16945	51	17391	81348	202	81343	200	81350	27759	27772	8	1	80201	100	99	100	100	80000	80000	0	100	80782	2	43	190	80951	1	0	4887	80949	6	1	39	43	4	0	0	0	5268	1	24	3	1	27533	0	10	10	4	80000	100	27776	27738	27738	27184	27772
80204	27625	208	0	0	0	0	0	0	7	7	969	616	0	0	0	27762	2	12	12	531	195	80882	100	81040	103	81246	522	1203539	1	26835	27768	27779	17406	51	17419	81350	200	81348	200	81348	27871	27767	7	1	80201	100	99	100	100	80000	80000	0	100	80260	0	43	190	80950	1	0	4828	80949	6	1	39	0	2	0	0	0	5178	1	65	1	1	27691	1	10	0	4	80000	100	27766	27764	27775	27910	27775
80204	27776	208	0	1	0	1	0	0	6	7	189	704	0	0	1	26906	2	12	12	540	196	81012	102	80260	100	81246	500	1205372	0	27832	28077	28050	17490	61	17624	81524	200	81151	202	81731	28065	28031	10	1	80201	100	99	100	100	80000	80000	0	100	80262	2	43	289	81209	1	2	6377	81170	6	1	39	43	2	0	0	0	5313	1	16	1	1	26724	0	10	10	4	80000	100	26708	26728	26728	26728	26728
80204	26727	199	0	0	0	0	0	0	0	0	45	0	0	0	1	26692	2	12	12	0	25	80100	100	80000	100	80000	500	1165789	0	26702	26727	26727	16650	3	16685	80100	200	80000	200	80000	26735	26738	1	1	80201	100	99	100	100	80000	80000	1	100	80000	0	0	0	80000	0	0	39	80039	0	1	0	43	0	0	0	0	5110	1	16	1	1	26724	0	10	10	4	80000	100	26728	26728	26728	26728	26728

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.3340

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	09	l2 tlb miss data (0b)	0e	0f	1e	22	24	3a	3f	43	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	cf	l1i cache miss demand (d3)	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
80025	26732	200	1	1	1	1	1	1	65	0	0	0	26693	0	18	18	12	25	80010	10	80000	10	80000	50	1166750	1	26697	26722	26722	16667	3	16707	80010	20	80000	20	80000	26807	26712	1	1	80021	10	9	10	10	80000	80000	1	10	80000	0	80035	0	0	80035	6	1	35	39	5020	0	6	16	4	3	26705	6	6	2	80000	10	26729	26723	26723	26723	26723
80024	26722	200	0	0	0	0	0	0	41	1	0	2	26707	2	18	0	12	25	80010	10	80000	10	80000	50	1166886	1	26683	26708	26708	16672	3	16707	80010	20	80000	20	80000	26724	26714	1	1	80021	10	9	10	10	80000	80000	1	10	80000	39	80000	0	35	80035	6	1	35	39	5020	1	4	16	4	4	26705	0	6	0	80000	10	26709	26723	26723	26723	26728
80024	26708	200	0	0	0	0	0	0	41	1	0	1	26707	1	18	18	0	25	80010	10	80000	10	80000	50	1167605	1	26697	26722	26708	16652	3	16702	80010	20	80000	20	80000	26728	26728	1	1	80021	10	9	10	10	80000	80000	0	10	80000	39	80000	10	35	80035	6	1	35	39	5020	1	4	16	3	4	26719	6	6	2	80000	10	26723	26723	26709	26723	26723
80024	26727	200	0	0	0	0	0	0	0	1	0	0	26712	2	0	18	12	25	80010	10	80000	10	80000	50	1166993	1	26697	26722	26722	16667	3	16707	80010	20	80000	20	80000	26722	26722	1	1	80021	10	9	10	10	80000	80000	0	10	80000	39	80035	0	35	80039	6	1	35	39	5020	1	4	16	4	3	26719	0	0	0	80000	10	26723	26723	26726	26723	26710
80024	26722	200	0	0	0	0	0	0	0	0	0	1	26713	0	0	0	2	25	80010	10	80000	10	80000	50	1167605	1	26683	26722	26722	16667	3	16688	80010	20	80000	20	80000	26728	27011	1	1	80021	10	9	10	10	80000	80000	0	10	80000	39	80035	0	0	80035	6	0	35	0	5020	4	4	16	4	4	26719	6	6	2	80000	10	26723	26723	26723	26723	26709
80024	26722	200	0	0	0	0	0	0	0	1	0	2	26712	2	18	0	12	25	80010	10	80000	10	80000	50	1166750	1	26683	26722	26708	16667	3	16688	80010	20	80000	20	80000	26852	26719	1	1	80021	10	9	10	10	80000	80000	0	10	80000	39	80035	1	35	80000	6	1	0	39	5020	4	4	16	4	4	26719	10	6	0	80000	10	26709	26723	26723	26723	26723
80024	26722	200	0	0	0	0	0	0	41	0	0	1	26693	2	0	18	12	25	80010	10	80000	10	80000	50	1167605	1	26683	26722	26728	16667	3	16702	80010	20	80000	20	80000	26869	26734	1	1	80021	10	9	10	10	80000	80000	0	10	80000	0	80035	1	0	80035	6	0	0	43	5020	4	4	16	4	3	26719	6	0	2	80000	10	26723	26723	26709	26709	26709
80024	26708	200	0	0	0	0	0	0	0	0	0	1	26712	2	0	18	0	25	80010	10	80000	10	80000	50	1167605	1	26702	26722	26708	16652	3	16702	80010	20	80000	20	80000	26813	26731	1	1	80021	10	9	10	10	80000	80000	0	10	80000	0	80035	0	35	80035	0	1	0	0	5020	4	4	16	4	4	26719	0	10	4	80000	10	26709	26709	26723	26709	26709
80024	26722	200	0	0	0	0	0	0	45	1	0	1	26707	0	18	18	9	25	80010	10	80000	10	80000	50	1167605	1	26697	26722	26722	16672	3	16707	80010	20	80000	20	80000	26730	26849	1	1	80021	10	9	10	10	80000	80000	0	10	80000	39	80000	0	35	80035	6	0	35	43	5020	4	3	16	3	4	26705	6	6	0	80000	10	26723	26723	26723	26723	26709
80024	26722	200	0	0	0	0	0	0	12	0	0	1	26707	2	12	18	16	25	80010	10	80000	10	80000	50	1167605	1	26697	26722	26708	16652	3	16688	80010	20	80000	20	80000	26736	27175	1	1	80021	10	9	10	10	80000	80000	0	10	80000	0	80035	0	0	80035	0	0	35	39	5020	4	4	16	3	4	26705	6	6	2	80000	10	26709	26709	26723	26723	26709

LDR (S)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->2 roundtrip

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations