Firestorm: LDR (literal, D) measurements

Code:

  ldr d0, .+4

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 1.000

SIMD/FP unit issues: 0.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	l2 tlb miss data (0b)	0e	0f	1e	20	22	23	3a	3e	3f	40	43	46	49	4f	51	schedule uop (52)	schedule ldst uop (55)	dispatch ldst uop (58)	simd uops in schedulers (5a)	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map ldst uop (7d)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst simd load (98)	inst ldst (9b)	9d	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	l1d cache miss ld (a3)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ab	ac	af	ldst x64 uop (b1)	b5	b6	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	e7	ea	eb	ec	? ldst retires (ed)	f5	f6	f7	f8	fd
1004	405	3	0	0	0	1	1	18	5	0	0	0	0	367	6	0	0	0	5	25	1000	1000	1000	14448	367	382	382	197	3	240	1000	1000	382	382	1	1	1001	1000	1000	0	1000	0	0	50	1022	4	0	10	0	11	1015	62	18	2	11	34	0	0	73	3	16	2	2	396	0	8	0	4	1000	383	392	383	387	383
1004	391	3	0	0	0	0	0	0	0	1	0	0	0	375	0	1	0	0	11	25	1000	1000	1000	14838	366	391	383	204	3	241	1000	1000	382	391	1	1	1001	1000	1000	0	1000	0	0	34	1011	0	0	0	0	22	1011	62	6	1	11	17	0	0	73	2	16	2	2	387	0	0	8	0	1000	383	391	383	391	392
1004	391	3	0	0	0	0	0	34	12	0	0	0	0	376	0	1	0	0	0	25	1000	1000	1000	14060	357	382	391	214	3	240	1000	1000	390	382	1	1	1001	1000	1000	0	1015	0	0	35	1022	0	0	0	0	38	1011	62	12	2	11	34	0	0	73	2	16	2	2	380	0	0	6	2	1000	390	399	390	383	390
1004	388	3	1	0	1	0	0	56	13	0	0	0	0	374	16	0	1	0	6	25	1000	1000	1000	14856	364	388	398	211	3	256	1000	1000	389	397	1	1	1001	1000	1000	0	1028	20	0	17	1042	9	6	0	0	32	1011	62	12	2	30	33	19	2	73	2	16	2	2	386	0	7	0	4	1000	389	389	398	389	390
1004	414	2	1	0	0	0	1	57	0	0	0	1	0	384	0	0	1	0	11	25	1000	1000	1000	15260	363	398	388	220	3	256	1000	1000	398	397	1	1	1001	1000	1000	0	1020	21	0	17	1030	15	0	5	10	21	1016	62	6	1	41	33	19	1	73	2	16	2	2	385	0	7	9	4	1000	390	398	390	399	399
1004	389	3	1	1	1	0	0	56	5	0	0	1	0	367	13	0	1	0	12	25	1000	1000	1000	15260	364	388	389	220	3	247	1000	1000	389	397	1	1	1001	1000	1000	0	1033	19	1	50	1043	8	1	12	0	52	1000	62	12	1	41	17	19	0	73	2	16	2	2	387	0	7	0	4	1000	391	390	390	402	397
1004	395	3	1	1	1	0	0	38	0	0	0	3	0	366	0	0	1	0	5	25	1000	1000	1000	14879	372	389	389	211	3	240	1000	1000	388	397	1	1	1001	1000	1000	0	1023	20	0	33	1031	2	0	9	0	53	1022	62	6	1	19	17	19	1	73	2	16	2	2	394	0	7	0	4	1000	390	383	389	389	389
1004	389	3	1	0	1	0	0	54	0	0	0	1	0	408	0	0	0	0	5	25	1000	1000	1000	14816	363	389	388	219	3	246	1000	1000	388	389	1	1	1001	1000	1000	0	1026	19	0	17	1030	0	0	9	0	54	1011	62	6	2	41	33	19	1	73	2	16	2	2	386	0	7	7	3	1000	389	399	389	401	389
1004	389	3	1	0	1	0	0	56	12	0	0	0	0	382	0	0	0	0	13	25	1000	1000	1000	15295	372	397	398	220	3	255	1000	1000	389	398	1	1	1001	1000	1000	0	1020	19	0	33	1032	1	0	1	0	52	1011	62	6	1	31	33	19	2	73	2	16	2	2	386	0	7	0	0	1000	389	382	391	392	398
1004	390	3	1	0	1	1	0	21	0	0	0	0	0	373	0	0	1	0	0	25	1000	1000	1000	14859	364	397	397	204	3	247	1000	1000	389	404	1	1	1001	1000	1000	0	1020	19	0	17	1041	1	0	0	0	21	1016	62	6	1	19	17	19	1	73	2	16	2	2	385	0	7	0	0	1000	382	382	398	390	382

Count: 8

Code:

  ldr d0, .+4
  ldr d0, .+4
  ldr d0, .+4
  ldr d0, .+4
  ldr d0, .+4
  ldr d0, .+4
  ldr d0, .+4
  ldr d0, .+4

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.3340

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	09	l2 tlb miss data (0b)	0e	0f	18	19	1e	1f	20	22	3a	3e	3f	40	43	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	l1d cache miss ld (a3)	a5	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ab	ac	af	ldst x64 uop (b1)	b5	b6	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	c3	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	e7	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
80204	26725	200	0	13	0	54	0	0	0	0	42	0	0	0	38	0	26699	5	1	0	0	3	25	80100	100	80000	100	80000	500	1166368	26688	26713	26716	16637	3	16672	80100	200	80000	200	26713	26752	1	1	80201	100	99	100	100	80000	80000	0	100	80281	198	1	33	0	80012	185	0	260	0	12	80152	5000	17	1	22	17	0	504	395	5110	2	16	2	2	26715	0	0	4	0	2	80000	100	26715	26715	26723	26723	26717
80204	26713	200	0	64	0	37	0	0	0	0	25	0	0	0	143	0	26700	0	1	0	0	9	25	80100	100	80000	100	80000	500	1164663	26689	26715	26713	16637	3	16673	80100	200	80000	200	26713	26737	1	1	80201	100	99	100	100	80000	80000	0	100	80297	111	0	18	0	80012	534	0	409	0	27	80238	5000	6	1	12	17	0	63	134	5110	2	16	2	2	26714	1	0	4	6	0	80000	100	26714	26714	26708	26714	26714
80204	26714	200	0	44	0	11	1	0	0	0	58	0	0	0	158	0	26695	4	1	1	0	5	25	80100	100	80000	100	80000	500	1167491	26688	26713	26714	16636	3	16671	80100	200	80000	200	26722	26767	1	1	80201	100	99	100	100	80000	80000	0	100	80368	189	3	35	0	80012	78	1	271	0	23	80299	5000	6	2	13	34	0	443	402	5110	2	16	2	2	26715	0	0	4	4	0	80000	100	26716	26721	26721	26722	26722
80204	26720	200	0	70	0	3	0	0	0	0	21	0	5	0	85	0	26706	0	2	0	0	6	25	80100	100	80000	100	80000	500	1170419	26699	26724	26715	16643	3	16685	80100	200	80000	200	26720	26731	1	1	80201	100	99	100	100	80000	80000	0	100	80273	226	1	53	0	80023	139	0	235	0	35	80284	5000	6	0	25	34	0	449	276	5110	2	16	2	2	26722	0	0	0	4	0	80000	100	26716	26722	26714	26728	26715
80204	26721	200	0	60	0	12	0	0	0	0	35	0	0	0	0	0	26698	12	1	0	0	3	25	80100	100	80000	100	80000	500	1166960	26703	26720	26713	16645	3	16678	80100	200	80000	200	26722	26739	1	1	80201	100	99	100	100	80000	80000	0	100	80192	85	1	50	0	80023	502	0	75	0	23	80158	5000	12	3	23	17	0	519	463	5110	2	16	2	2	26736	0	0	7	6	0	80000	100	26715	26715	26715	26722	26721
80204	26720	200	0	43	0	53	0	0	0	0	28	0	0	1	35	0	26699	6	0	0	0	3	25	80100	100	80000	100	80000	500	1166905	26691	26721	26721	16636	3	16672	80100	200	80000	200	26721	26721	1	1	80201	100	99	100	100	80000	80000	0	100	80857	5	0	33	159	80548	37	1	111	6	5008	80932	5042	6	1	11	33	0	13	83	5270	2	49	4	2	27644	0	23	7	4	2	80000	100	27760	27762	27615	27773	27457
80204	27620	208	0	0	0	2	1	0	7	6	282	616	0	0	1	0	27608	0	0	1	0	526	190	81035	129	80910	126	81246	540	1199537	27641	27755	27810	16744	53	17418	81191	200	81347	202	27732	27606	9	1	80201	100	99	100	100	80000	80000	0	100	81008	2	0	35	226	80940	75	3	345	6	6342	81005	5049	6	2	22	17	0	95	153	5248	3	65	4	5	27672	0	23	4	6	2	80000	100	27770	27622	27656	27758	27709
80204	27762	208	0	1	0	0	0	0	7	7	950	616	7	0	1	0	27628	0	0	0	0	489	232	81171	129	80910	128	81068	653	1204538	27772	27760	27761	17347	37	17148	81373	208	81151	207	27881	27751	8	1	80201	100	99	100	100	80000	80000	0	100	80921	14	5	17	223	80922	3	2	66	0	5611	81002	5056	6	1	32	34	19	62	32	5178	1	72	2	2	27556	0	22	0	3	0	80000	100	27745	27765	27768	27654	27760
80204	27747	208	1	2	1	0	0	0	8	7	699	440	0	0	6	0	28052	0	1	2	2	616	166	81165	127	81170	127	81602	653	1185496	28047	28028	28077	17535	30	17731	81728	204	81732	202	27914	28064	9	1	80201	100	99	100	100	80000	80000	0	100	81140	19	3	52	257	81214	80	1	120	0	4870	81188	5073	12	2	41	17	19	77	21	5313	3	88	5	3	27928	0	24	0	3	0	80000	100	28111	28057	28063	28034	27157
80204	28065	210	1	0	0	0	0	0	9	2	1228	704	16	0	126	0	26707	0	1	0	3	11	25	80100	100	80000	100	80000	500	1176930	26696	26720	26727	16637	3	16678	80100	200	80000	200	26726	26738	1	1	80201	100	99	100	100	80000	80000	0	100	80208	66	0	34	0	80043	386	0	159	0	32	80207	5000	6	1	31	17	19	328	382	5110	2	16	2	2	26725	0	0	3	0	2	80000	100	26730	26723	26723	26721	26722

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.3391

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	09	l2 tlb miss data (0b)	0e	0f	18	19	1e	1f	20	22	29	2b	3a	3e	3f	40	43	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	69	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	92	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	l1d cache miss ld (a3)	a5	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ab	ac	af	ldst x64 uop (b1)	ldst xpg uop (b2)	b5	b6	bb	be	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	c3	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	e7	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
80024	27183	203	2	0	2	2	0	0	0	0	438	0	93	1	0	0	7	44	27082	77	14	78	93	333	25	80010	10	80000	10	80000	50	1184396	1	27101	0	27124	27103	17056	3	17117	80010	20	80000	20	27138	27110	1	1	80021	10	9	0	10	10	80000	80000	0	10	80122	20	31	391	193	80450	173	2	185	28	322	80370	5000	10	115	20	305	10	333	19	2	47	0	5020	13	16	6	13	27122	16	11	2	6	80000	10	27136	27103	27128	27117	27132
80024	27095	204	1	0	0	0	0	0	0	0	383	0	87	1	0	0	7	60	27093	66	12	76	113	277	25	80010	10	80000	10	80000	50	1186257	1	27059	0	27099	27109	17055	3	17101	80010	20	80000	20	27135	27130	1	1	80021	10	9	0	10	10	80000	80000	0	10	80182	21	13	341	189	80355	173	1	82	30	428	80356	5000	10	109	13	294	10	220	19	46	104	0	5020	4	16	4	12	27180	24	13	9	2	80000	10	27129	27171	27223	27146	27158
80024	27127	202	1	1	0	0	0	0	0	0	521	0	115	1	0	1	10	44	27127	123	27	65	100	324	25	80010	10	80000	10	80000	50	1187558	1	27115	3	27106	27115	17090	3	17123	80010	20	80000	20	27157	27166	1	1	80021	10	9	0	10	10	80000	80000	0	10	80207	36	25	436	181	80346	154	1	108	28	363	80379	5000	10	167	23	324	10	344	37	35	75	0	5020	4	16	5	13	27713	13	15	5	3	80000	10	27176	27128	27255	27136	27140
80024	27085	203	2	2	2	3	0	1	0	0	679	88	60	1	32	0	10	84	27256	85	10	112	87	321	25	80010	10	80000	10	80000	50	1184785	1	27064	0	27095	27076	17015	3	17167	80010	20	80000	20	27208	27197	1	1	80021	10	9	0	10	10	80000	80000	0	10	80311	37	26	322	178	80371	178	1	90	14	1430	80491	5000	10	62	6	331	10	390	32	8	9	0	5020	12	16	6	6	27190	24	8	7	6	80000	10	27176	27127	27186	27140	27099
80024	27082	203	2	2	1	2	0	0	0	0	516	0	80	1	0	0	14	52	27131	101	7	125	94	371	25	80010	10	80000	10	80000	50	1188735	0	27078	0	27115	27112	17087	3	17134	80010	20	80000	20	27154	27094	1	1	80021	10	9	0	10	10	80000	80000	0	10	80152	39	11	365	188	80427	140	4	156	22	389	80427	5000	10	117	18	426	10	266	37	0	69	0	5020	7	16	6	12	27153	18	10	2	6	80000	10	27194	27358	27112	27161	27109
80024	27136	203	2	0	0	1	0	0	0	0	545	0	132	2	0	0	14	52	27098	78	12	140	104	336	25	80010	10	80000	10	80000	50	1187959	0	27113	0	27111	27092	17078	3	17097	80010	20	80193	20	27108	27157	1	1	80021	10	9	0	10	10	80000	80000	1	10	80165	39	22	426	182	80430	138	3	146	34	498	80489	5000	10	115	19	346	10	269	36	42	35	0	5020	5	16	7	4	27143	20	6	9	9	80000	10	27178	27186	27157	27320	27162
80024	27170	203	2	0	0	2	0	0	0	0	566	0	102	1	0	0	10	100	27100	87	17	81	61	318	25	80010	10	80000	10	80000	50	1186464	0	27110	0	27132	27257	17096	3	17129	80010	20	80000	20	27137	27123	1	1	80021	10	9	0	10	10	80000	80000	0	10	80153	42	24	452	185	80502	137	3	232	26	399	80413	5000	10	135	17	354	10	419	38	37	59	0	5043	4	24	3	6	27173	18	3	12	8	80000	10	27144	27585	27260	27115	27169
80024	27238	205	2	1	0	2	0	1	3	1	744	0	84	2	0	0	7	44	27082	71	12	123	136	357	25	80010	10	80000	10	80000	50	1187768	0	27090	0	27123	27099	17057	3	17080	80010	20	80000	20	27118	27115	1	1	80021	10	9	0	10	10	80000	80000	0	10	80157	39	17	561	186	80385	107	2	115	46	301	80466	5000	10	117	22	444	10	427	37	39	5	0	5020	4	16	11	6	27139	17	6	5	3	80000	10	27179	27098	27111	27099	27119
80024	27125	203	2	2	2	2	0	0	0	0	810	0	141	2	0	0	7	24	27098	88	11	61	103	301	25	80010	10	80000	10	80000	50	1186205	1	27104	0	27159	27191	17083	3	17111	80010	20	80000	20	27122	27086	1	1	80021	10	9	0	10	10	80000	80000	2	10	80177	38	20	307	184	80394	145	3	205	46	438	80521	5000	10	95	22	367	10	305	33	4	22	0	5020	4	16	4	5	27160	12	7	2	6	80000	10	27160	27164	27168	27145	27119
80024	27133	203	2	0	3	3	0	1	0	0	396	0	85	1	0	1	11	0	27093	44	21	121	59	285	25	80010	10	80000	10	80000	50	1187495	0	27117	0	27099	27168	17089	3	17150	80010	20	80193	20	27129	27129	1	1	80021	10	9	0	10	10	80000	80000	0	10	80212	34	18	293	189	80364	188	1	175	28	493	80375	5000	10	102	28	309	10	314	37	14	216	0	5020	8	16	4	9	27129	19	14	6	7	80000	10	27178	27198	27180	27113	27173

LDR (literal, D)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations