Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

LDR (literal, D)

Test 1: uops

Code:

  ldr d0, .+4

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 1.000

SIMD/FP unit issues: 0.000

retire uop (01)cycle (02)03l1d tlb fill (05)mmu table walk data (08)l2 tlb miss data (0b)0e0f1e2022233a3e3f404346494f51schedule uop (52)schedule ldst uop (55)dispatch ldst uop (58)simd uops in schedulers (5a)696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map ldst uop (7d)8283flush restart other nonspec (84)85inst all (8c)inst simd load (98)inst ldst (9b)9dl1d tlb access (a0)l1d tlb miss (a1)l1d cache miss st (a2)l1d cache miss ld (a3)ld unit uop (a6)st unit uop (a7)l1d cache writeback (a8)a9abacafldst x64 uop (b1)b5b6bbl1d cache miss ld nonspec (bf)l1d tlb miss nonspec (c1)c2cfd5map dispatch bubble (d6)ddfetch restart (de)e0e7eaebec? ldst retires (ed)f5f6f7f8fd
100440530001118500003676000525100010001000144483673823821973240100010003823821110011000100001000005010224010011101562182113400733162239608041000383392383387383
1004391300000001000375010011251000100010001483836639138320432411000100038239111100110001000010000034101100002210116261111700732162238700801000383391383391392
100439130000034120000376010002510001000100014060357382391214324010001000390382111001100010000101500351022000038101162122113400732162238000621000390399390383390
100438831010056130000374160106251000100010001485636438839821132561000100038939711100110001000010282001710429600321011621223033192732162238607041000389389398389390
100441421000157000103840010112510001000100015260363398388220325610001000398397111001100010000102021017103015051021101662614133191732162238507941000390398390399399
1004389311100565001036713010122510001000100015260364388389220324710001000389397111001100010000103319150104381120521000621214117190732162238707041000391390390402397
100439531110038000303660010525100010001000148793723893892113240100010003883971110011000100001023200331031209053102262611917191732162239407041000390383389389389
100438931010054000104080000525100010001000148163633893882193246100010003883891110011000100001026190171030009054101162624133191732162238607731000389399389401389
10043893101005612000038200001325100010001000152953723973982203255100010003893981110011000100001020190331032101052101162613133192732162238607001000389382391392398
100439031011021000003730010025100010001000148593643973972043247100010003894041110011000100001020190171041100021101662611917191732162238507001000382382398390382

Test 2: throughput

Count: 8

Code:

  ldr d0, .+4
  ldr d0, .+4
  ldr d0, .+4
  ldr d0, .+4
  ldr d0, .+4
  ldr d0, .+4
  ldr d0, .+4
  ldr d0, .+4

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.3340

retire uop (01)cycle (02)03l1d tlb fill (05)mmu table walk data (08)09l2 tlb miss data (0b)0e0f18191e1f20223a3e3f404346494f51schedule uop (52)schedule int uop (53)schedule ldst uop (55)dispatch int uop (56)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map ldst uop (7d)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd load (98)inst ldst (9b)9d9fl1d tlb access (a0)l1d tlb miss (a1)l1d cache miss st (a2)l1d cache miss ld (a3)a5ld unit uop (a6)st unit uop (a7)l1d cache writeback (a8)a9abacafldst x64 uop (b1)b5b6bbl1d cache miss ld nonspec (bf)l1d tlb miss nonspec (c1)c2c3cfd5map dispatch bubble (d6)ddfetch restart (de)e0e7? int output thing (e9)eaebec? ldst retires (ed)? int retires (ef)f5f6f7f8fd
80204267252000130540000420003802669951003258010010080000100800005001166368266882671326716166373166728010020080000200267132675211802011009910010080000800000100802811981330800121850260012801525000171221705043955110216222671500402800001002671526715267232672326717
8020426713200064037000025000143026700010092580100100800001008000050011646632668926715267131663731667380100200800002002671326737118020110099100100800008000001008029711101808001253404090278023850006112170631345110216222671410460800001002671426714267082671426714
8020426714200044011100058000158026695411052580100100800001008000050011674912668826713267141663631667180100200800002002672226767118020110099100100800008000001008036818933508001278127102380299500062133404434025110216222671500440800001002671626721267212672226722
802042672020007003000021050850267060200625801001008000010080000500117041926699267242671516643316685801002008000020026720267311180201100991001008000080000010080273226153080023139023503580284500060253404492765110216222672200040800001002671626722267142672826715
802042672120006001200003500000266981210032580100100800001008000050011669602670326720267131664531667880100200800002002672226739118020110099100100800008000001008019285150080023502075023801585000123231705194635110216222673600760800001002671526715267152672226721
8020426720200043053000028001350266996000325801001008000010080000500116690526691267212672116636316672801002008000020026721267211180201100991001008000080000010080857503315980548371111650088093250426111330138352702494227644023742800001002776027762276152777327457
802042762020800021076282616001027608001052619081035129809101268124654011995372764127755278101674453174188119120081347202277322760691802011009910010080000800000100810082035226809407533456634281005504962221709515352483654527672023462800001002777027622276562775827709
80204277622080100007795061670102762800004892328117112980910128810686531204538277722776027761173473717148813732088115120727881277518180201100991001008000080000010080921145172238092232660561181002505661323419623251781722227556022030800001002774527765277682765427760
80204277472081210008769944000602805201226161668116512781170127816026531185496280472802828077175353017731817282048173220227914280649180201100991001008000080000010081140193522578121480112004870811885073122411719772153133885327928024030800001002811128057280632803427157
802042806521010000092122870416012602670701031125801001008000010080000500117693026696267202672716637316678801002008000020026726267381180201100991001008000080000010080208660340800433860159032802075000613117193283825110216222672500302800001002673026723267232672126722

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.3391

retire uop (01)cycle (02)03l1d tlb fill (05)mmu table walk data (08)09l2 tlb miss data (0b)0e0f18191e1f2022292b3a3e3f404346494f51schedule uop (52)schedule int uop (53)schedule ldst uop (55)dispatch int uop (56)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)60696b6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map ldst uop (7d)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)92inst branch cond (94)inst int alu (97)inst simd load (98)inst ldst (9b)9d9fl1d tlb access (a0)l1d tlb miss (a1)l1d cache miss st (a2)l1d cache miss ld (a3)a5ld unit uop (a6)st unit uop (a7)l1d cache writeback (a8)a9abacafldst x64 uop (b1)ldst xpg uop (b2)b5b6bbbel1d cache miss ld nonspec (bf)l1d tlb miss nonspec (c1)c2c3cdcfd5map dispatch bubble (d6)ddfetch restart (de)e0e7eaebec? ldst retires (ed)? int retires (ef)f5f6f7f8fd
80024271832032022000043809310074427082771478933332580010108000010800005011843961271010271242710317056317117800102080000202713827110118002110901010800008000001080122203139119380450173218528322803705000101152030510333192470502013166132712216112680000102713627103271282711727132
800242709520410000000383087100760270936612761132772580010108000010800005011862571270590270992710917055317101800102080000202713527130118002110901010800008000001080182211334118980355173182304288035650001010913294102201946104050204164122718024139280000102712927171272232714627158
800242712720211000000521011510110442712712327651003242580010108000010800005011875581271153271062711517090317123800102080000202715727166118002110901010800008000001080207362543618180346154110828363803795000101672332410344373575050204165132771313155380000102717627128272552713627140
8002427085203222301006798860132010842725685101128732125800101080000108000050118478512706402709527076170153171678001020800002027208271971180021109010108000080000010803113726322178803711781901414308049150001062633110390328905020121666271902487680000102717627127271862714027099
800242708220322120000516080100145227131101712594371258001010800001080000501188735027078027115271121708731713480010208000020271542709411800211090101080000800000108015239113651888042714041562238980427500010117184261026637069050207166122715318102680000102719427358271122716127109
8002427136203200100005450132200145227098781214010433625800101080000108000050118795902711302711127092170783170978001020801932027108271571180021109010108000080000110801653922426182804301383146344988048950001011519346102693642350502051674271432069980000102717827186271572732027162
8002427170203200200005660102100101002710087178161318258001010800001080000501186464027110027132272571709631712980010208000020271372712311800211090101080000800000108015342244521858050213732322639980413500010135173541041938375905043424362717318312880000102714427585272602711527169
80024272382052102013174408420074427082711212313635725800101080000108000050118776802709002712327099170573170808001020800002027118271151180021109010108000080000010801573917561186803851072115463018046650001011722444104273739505020416116271391765380000102717927098271112709927119
800242712520322220000810014120072427098881161103301258001010800001080000501186205127104027159271911708331711180010208000020271222708611800211090101080000800002108017738203071848039414532054643880521500010952236710305334220502041645271601272680000102716027164271682714527119
800242713320320330100396085101110270934421121592852580010108000010800005011874950271170270992716817089317150800102080193202712927129118002110901010800008000001080212341829318980364188117528493803755000101022830910314371421605020816492712919146780000102717827198271802711327173