Apple M1 Microarchitecture Research by Dougall Johnson

Firestorm: Overview | Base Instructions | SIMD and FP Instructions
Icestorm:  Overview | Base Instructions | SIMD and FP Instructions

LDR (literal, Q)

Test 1: uops

Code:

  ldr q0, .+4

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 1.000

SIMD/FP unit issues: 0.000

retire (01)cycle (02)030508090b0e0f1e2022233a3e3f404346494f51inst issue (52)~issue ld/st (55)~dispatch ld/st (58)huge thing ld/st (5a)60696d6edispatch stall (70)scheduler rewind (75)scheduler stall (76)~dispatch op (78)~map op ld/st (7d)8283pipeline redirect (84)85inst all (8c)inst fp/simd load (98)inst ldst (9b)9da0a1a2a3a6a7a8a9abacafb1b5b6bbdcache load miss (bf)c2cfd5d6ddinst fetch restart (de)e0e7eaebecld/st retires (ed)f5f6f7f8fd
1004398310000022000603794000725100010001000145430367384392197324210001000392385111001100010000100000381032000641101618612232190731161138109951000393411386385393
1004392310000144410303785000425100010001000145540359384396205325210001000385392111001100010000100501381016700016104518618149380731161138109951000389418395393393
10043923000010441710303690000142510001000100014571035939239220732511000100039339411100110001000010000019101650131416104418612216380731161138209941000395385393393385
1004384300000045700203855000825100010001000145630359384384208324210001000392393111001100010000100500191016170001610381866117190731161138907951000385386385385386
1004385300000044171020369000014251000100010001453613603843942153241100010003843921110011000100001012003810348081632104418612232380731161138109951000394385395393386
10043922100000237003037813100825100010001000145360360392385207324110001000384384111001100010000100000381016000016101618612135190731161138209751000395393393385385
1004392301000022510203770300725100010001000150000368394384207324210001000385392111001100010000101200571016120131016104518612216380731161138109951000385393386385386
10043843000000450003036900001125100010001000145710368385384207325010001000384392111001100010000100000191016000032103218612132380731161139009951000393395385393385
100439330000002300000377113001125100010001000145360359394393216325010001000384392111001100010000100400381034100101216101618612216190731161138109951000393386384394385
100438430000002212102036904001425100010001000149470369384385216324210001000393384111001100010001101300391016120131632104318612216380731161138909951000401385393395385

Test 2: throughput

Count: 8

Code:

  ldr q0, .+4
  ldr q0, .+4
  ldr q0, .+4
  ldr q0, .+4
  ldr q0, .+4
  ldr q0, .+4
  ldr q0, .+4
  ldr q0, .+4

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.3341

retire (01)cycle (02)030508090b0e0f1e1f2022233a3e3f404346494f51inst issue (52)~issue int (53)~issue ld/st (55)~dispatch int (56)~dispatch ld/st (58)huge thing int (59)huge thing ld/st (5a)696d6edispatch stall (70)scheduler rewind (75)scheduler stall (76)~dispatch op (78)~map op int (7c)~map op ld/st (7d)~map lookup int (7f)8283pipeline redirect (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst b.cc (94)inst integer (97)inst fp/simd load (98)inst ldst (9b)9d9fa0a1a2a3a6a7a8a9abacafb1b5b6bbdcache load miss (bf)dtlb miss (c1)c2c3cfd5d6ddinst fetch restart (de)e0e7eaebecld/st retires (ed)gpr retires (ef)f5f6f7f8fd
8020426738200162000063061018502671103005258010010080000100800005001167711266982672426726166473167728010020080000200267232673311802011009910010080000800000100803857723880064901648448011715000172521919353443511021622267340475800001002673226739267292673026738
8020426733200120108106501310840267134267162580100100800001008000050011673772669826726267271666131679780100200800002002672426723118020110099100100800008000001008024320338800513970395045801681500061381919111155511021622267270710800001002672926731267272673026725
802042673420011713200460510310267095100102580100100800001008000050011674162671026728267291665531678880100200800002002673026734118020110099100100800008000001008006713725480065891520638802521500061381919341469511021622267233302800001002672526732267292672426730
8020426731200141058005006101440267173202925801001008000010080000500116730526700267252672416646316786801002008000020026729267331180201100991001008000080000010080148170335800471660274040801691500061471919419115511021622267260772800001002672926725267272673126725
802042673120111116200520500164426723622012258010010080000100800005001166105266992672526728166523167838010020080000200267282672911802011009910010080000800000100800774056388003841502390448027515000122453519226148511021622267241745800001002672726724267302672726726
802042673020019804004703101930267209500725801001008000010080000500117109626706267242672416645316828801002008000020026725267291180201100991001008000080000010080123213238800661252389067802511500061381919477420511021622267232714800001002672726726267272672426726
802042672620017013000460510163026720457012258010010080000100800005001167549267052672526728166523167818010020080000200267352673911802011009910010080000800000100801582744198003846013846398030215000122513819526459511021622267220775800001002672826726267262672526724
802042672720014501500670410122026709525052580100100800001008000050011752812670026723267261665031678380100200800002002672526726118020110099100100800008000001008017959338800631480984528011115000122543819175324511021622267212775800001002672726723267232672526730
80204267262001661115004301310149026723440062580100100800001008000050011686002669926732267271664431678180100200800002002672426725118020110099100100800008000001008042246053880052477099037802921500061381919422317511021622267280214800001002672626728267262672526726
802042672420017812100860130030267133200625801001008000010080000500116749526699267252672316648316796801002008000020026725267231180201100991001008000080000010080637271238800533400365037802371500061361919309286511021622267202742800001002673426738267262672626726

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.3476

retire (01)cycle (02)030508090b0e0f1e1f2022292b3a3e3f404346494f51inst issue (52)~issue int (53)~issue ld/st (55)~dispatch int (56)~dispatch ld/st (58)huge thing int (59)huge thing ld/st (5a)60696d6edispatch stall (70)scheduler rewind (75)scheduler stall (76)~dispatch op (78)~map op int (7c)~map op ld/st (7d)~map lookup int (7f)8283pipeline redirect (84)85inst all (8c)inst branch (8d)inst branch taken (90)92inst b.cc (94)inst integer (97)inst fp/simd load (98)inst ldst (9b)9d9fa0a1a2a3a5a6a7a8a9abacafb1b2b5b6bbbedcache load miss (bf)dtlb miss (c1)c2c3cfd5d6ddinst fetch restart (de)e0e7? int output thing (e9)eaebecld/st retires (ed)gpr retires (ef)f5f6f7f8fd
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