Firestorm: LDR (literal, Q) measurements

Code:

  ldr q0, .+4

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 1.000

SIMD/FP unit issues: 0.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	09	l2 tlb miss data (0b)	0e	0f	1e	20	22	23	3a	3e	3f	40	43	46	49	4f	51	schedule uop (52)	schedule ldst uop (55)	dispatch ldst uop (58)	simd uops in schedulers (5a)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map ldst uop (7d)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst simd load (98)	inst ldst (9b)	9d	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	l1d cache miss ld (a3)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ab	ac	af	ldst x64 uop (b1)	b5	b6	bb	l1d cache miss ld nonspec (bf)	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	e7	ea	eb	ec	? ldst retires (ed)	f5	f6	f7	f8	fd
1004	398	3	1	0	0	0	0	0	22	0	0	0	6	0	379	4	0	0	0	7	25	1000	1000	1000	14543	0	367	384	392	197	3	242	1000	1000	392	385	1	1	1001	1000	1000	0	1000	0	0	38	1032	0	0	0	6	41	1016	186	12	2	32	19	0	73	1	16	1	1	381	0	9	9	5	1000	393	411	386	385	393
1004	392	3	1	0	0	0	0	1	44	4	1	0	3	0	378	5	0	0	0	4	25	1000	1000	1000	14554	0	359	384	396	205	3	252	1000	1000	385	392	1	1	1001	1000	1000	0	1005	0	1	38	1016	7	0	0	0	16	1045	186	18	1	49	38	0	73	1	16	1	1	381	0	9	9	5	1000	389	418	395	393	393
1004	392	3	0	0	0	0	1	0	44	17	1	0	3	0	369	0	0	0	0	14	25	1000	1000	1000	14571	0	359	392	392	207	3	251	1000	1000	393	394	1	1	1001	1000	1000	0	1000	0	0	19	1016	5	0	13	14	16	1044	186	12	2	16	38	0	73	1	16	1	1	382	0	9	9	4	1000	395	385	393	393	385
1004	384	3	0	0	0	0	0	0	45	7	0	0	2	0	385	5	0	0	0	8	25	1000	1000	1000	14563	0	359	384	384	208	3	242	1000	1000	392	393	1	1	1001	1000	1000	0	1005	0	0	19	1016	17	0	0	0	16	1038	186	6	1	17	19	0	73	1	16	1	1	389	0	7	9	5	1000	385	386	385	385	386
1004	385	3	0	0	0	0	0	0	44	17	1	0	2	0	369	0	0	0	0	14	25	1000	1000	1000	14536	1	360	384	394	215	3	241	1000	1000	384	392	1	1	1001	1000	1000	0	1012	0	0	38	1034	8	0	8	16	32	1044	186	12	2	32	38	0	73	1	16	1	1	381	0	9	9	5	1000	394	385	395	393	386
1004	392	2	1	0	0	0	0	0	23	7	0	0	3	0	378	13	1	0	0	8	25	1000	1000	1000	14536	0	360	392	385	207	3	241	1000	1000	384	384	1	1	1001	1000	1000	0	1000	0	0	38	1016	0	0	0	0	16	1016	186	12	1	35	19	0	73	1	16	1	1	382	0	9	7	5	1000	395	393	393	385	385
1004	392	3	0	1	0	0	0	0	22	5	1	0	2	0	377	0	3	0	0	7	25	1000	1000	1000	15000	0	368	394	384	207	3	242	1000	1000	385	392	1	1	1001	1000	1000	0	1012	0	0	57	1016	12	0	13	10	16	1045	186	12	2	16	38	0	73	1	16	1	1	381	0	9	9	5	1000	385	393	386	385	386
1004	384	3	0	0	0	0	0	0	45	0	0	0	3	0	369	0	0	0	0	11	25	1000	1000	1000	14571	0	368	385	384	207	3	250	1000	1000	384	392	1	1	1001	1000	1000	0	1000	0	0	19	1016	0	0	0	0	32	1032	186	12	1	32	38	0	73	1	16	1	1	390	0	9	9	5	1000	393	395	385	393	385
1004	393	3	0	0	0	0	0	0	23	0	0	0	0	0	377	11	3	0	0	11	25	1000	1000	1000	14536	0	359	394	393	216	3	250	1000	1000	384	392	1	1	1001	1000	1000	0	1004	0	0	38	1034	10	0	10	12	16	1016	186	12	2	16	19	0	73	1	16	1	1	381	0	9	9	5	1000	393	386	384	394	385
1004	384	3	0	0	0	0	0	0	22	12	1	0	2	0	369	0	4	0	0	14	25	1000	1000	1000	14947	0	369	384	385	216	3	242	1000	1000	393	384	1	1	1001	1000	1000	1	1013	0	0	39	1016	12	0	13	16	32	1043	186	12	2	16	38	0	73	1	16	1	1	389	0	9	9	5	1000	401	385	393	395	385

Count: 8

Code:

  ldr q0, .+4
  ldr q0, .+4
  ldr q0, .+4
  ldr q0, .+4
  ldr q0, .+4
  ldr q0, .+4
  ldr q0, .+4
  ldr q0, .+4

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.3341

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	09	l2 tlb miss data (0b)	0e	0f	1e	1f	20	22	23	3a	3e	3f	40	43	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	l1d cache miss ld (a3)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ab	ac	af	ldst x64 uop (b1)	b5	b6	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	c3	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	e7	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
80204	26738	200	1	62	0	0	0	0	63	0	6	1	0	185	0	26711	0	3	0	0	5	25	80100	100	80000	100	80000	500	1167711	26698	26724	26726	16647	3	16772	80100	200	80000	200	26723	26733	1	1	80201	100	99	100	100	80000	80000	0	100	80385	77	2	38	80064	90	1	64	8	44	80117	15000	17	2	52	19	19	353	443	5110	2	16	2	2	26734	0	4	7	5	80000	100	26732	26739	26729	26730	26738
80204	26733	200	1	2	0	108	1	0	65	0	13	1	0	84	0	26713	4	2	6	7	16	25	80100	100	80000	100	80000	500	1167377	26698	26726	26727	16661	3	16797	80100	200	80000	200	26724	26723	1	1	80201	100	99	100	100	80000	80000	0	100	80243	20	3	38	80051	397	0	395	0	45	80168	15000	6	1	38	19	19	111	155	5110	2	16	2	2	26727	0	7	1	0	80000	100	26729	26731	26727	26730	26725
80204	26734	200	1	17	1	32	0	0	46	0	5	1	0	31	0	26709	5	1	0	0	10	25	80100	100	80000	100	80000	500	1167416	26710	26728	26729	16655	3	16788	80100	200	80000	200	26730	26734	1	1	80201	100	99	100	100	80000	80000	0	100	80067	137	2	54	80065	89	1	520	6	38	80252	15000	6	1	38	19	19	341	469	5110	2	16	2	2	26723	3	3	0	2	80000	100	26725	26732	26729	26724	26730
80204	26731	200	1	41	0	58	0	0	50	0	6	1	0	144	0	26717	3	2	0	2	9	25	80100	100	80000	100	80000	500	1167305	26700	26725	26724	16646	3	16786	80100	200	80000	200	26729	26733	1	1	80201	100	99	100	100	80000	80000	0	100	80148	170	3	35	80047	166	0	274	0	40	80169	15000	6	1	47	19	19	419	115	5110	2	16	2	2	26726	0	7	7	2	80000	100	26729	26725	26727	26731	26725
80204	26731	201	1	11	1	62	0	0	52	0	5	0	0	164	4	26723	6	2	2	0	12	25	80100	100	80000	100	80000	500	1166105	26699	26725	26728	16652	3	16783	80100	200	80000	200	26728	26729	1	1	80201	100	99	100	100	80000	80000	0	100	80077	405	6	38	80038	415	0	239	0	44	80275	15000	12	2	45	35	19	226	148	5110	2	16	2	2	26724	1	7	4	5	80000	100	26727	26724	26730	26727	26726
80204	26730	200	1	98	0	4	0	0	47	0	3	1	0	193	0	26720	9	5	0	0	7	25	80100	100	80000	100	80000	500	1171096	26706	26724	26724	16645	3	16828	80100	200	80000	200	26725	26729	1	1	80201	100	99	100	100	80000	80000	0	100	80123	213	2	38	80066	125	2	389	0	67	80251	15000	6	1	38	19	19	477	420	5110	2	16	2	2	26723	2	7	1	4	80000	100	26727	26726	26727	26724	26726
80204	26726	200	1	70	1	30	0	0	46	0	5	1	0	163	0	26720	4	5	7	0	12	25	80100	100	80000	100	80000	500	1167549	26705	26725	26728	16652	3	16781	80100	200	80000	200	26735	26739	1	1	80201	100	99	100	100	80000	80000	0	100	80158	274	4	19	80038	460	1	384	6	39	80302	15000	12	2	51	38	19	526	459	5110	2	16	2	2	26722	0	7	7	5	80000	100	26728	26726	26726	26725	26724
80204	26727	200	1	45	0	15	0	0	67	0	4	1	0	122	0	26709	5	2	5	0	5	25	80100	100	80000	100	80000	500	1175281	26700	26723	26726	16650	3	16783	80100	200	80000	200	26725	26726	1	1	80201	100	99	100	100	80000	80000	0	100	80179	59	3	38	80063	148	0	98	4	52	80111	15000	12	2	54	38	19	175	324	5110	2	16	2	2	26721	2	7	7	5	80000	100	26727	26723	26723	26725	26730
80204	26726	200	1	66	1	115	0	0	43	0	13	1	0	149	0	26723	4	4	0	0	6	25	80100	100	80000	100	80000	500	1168600	26699	26732	26727	16644	3	16781	80100	200	80000	200	26724	26725	1	1	80201	100	99	100	100	80000	80000	0	100	80422	460	5	38	80052	477	0	99	0	37	80292	15000	6	1	38	19	19	422	317	5110	2	16	2	2	26728	0	2	1	4	80000	100	26726	26728	26726	26725	26726
80204	26724	200	1	78	1	21	0	0	86	0	13	0	0	3	0	26713	3	2	0	0	6	25	80100	100	80000	100	80000	500	1167495	26699	26725	26723	16648	3	16796	80100	200	80000	200	26725	26723	1	1	80201	100	99	100	100	80000	80000	0	100	80637	271	2	38	80053	340	0	365	0	37	80237	15000	6	1	36	19	19	309	286	5110	2	16	2	2	26720	2	7	4	2	80000	100	26734	26738	26726	26726	26726

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.3476

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	09	l2 tlb miss data (0b)	0e	0f	1e	1f	20	22	29	2b	3a	3e	3f	40	43	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	92	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	l1d cache miss ld (a3)	a5	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ab	ac	af	ldst x64 uop (b1)	ldst xpg uop (b2)	b5	b6	bb	be	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	c3	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	e7	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
80024	27955	209	1	1	4	1	1	0	737	0	143	1	0	0	15	112	27766	100	160	62	94	953	25	80010	10	80000	10	80000	50	1218328	1	27734	27759	27856	17783	3	17833	80010	20	80000	20	27752	27872	1	1	80021	10	9	0	10	10	80000	80000	0	10	80187	20	17	493	656	80690	137	3	174	14	670	80807	15000	30	141	14	952	30	305	19	48	114	5020	16	16	12	11	27790	119	0	31	21	16	80000	10	27850	27791	27869	27814	27783
80024	27807	208	1	1	1	1	0	0	778	0	84	1	56	0	15	64	27752	79	179	84	51	925	25	80010	10	80000	10	80000	50	1219289	0	27791	27769	27784	17721	3	17823	80010	20	80000	20	27856	27819	1	1	80021	10	9	0	10	10	80000	80000	0	10	80243	19	30	450	660	80666	207	1	135	72	848	80790	15000	30	81	18	776	30	437	19	10	14	5020	12	16	12	12	27812	107	0	17	27	12	80000	10	27826	27795	27787	27845	27842
80024	27821	207	1	1	0	0	0	0	801	0	97	0	0	0	20	84	27776	59	174	42	62	911	25	80010	10	80000	10	80000	50	1217124	0	27775	27836	27837	17819	3	17806	80010	20	80000	20	27775	27800	1	1	80021	10	9	0	10	10	80000	80000	0	10	80215	19	12	369	680	80714	136	2	138	40	591	80615	15000	30	90	16	619	30	261	19	1	77	5020	11	16	13	11	27829	122	0	22	18	12	80000	10	27841	27833	27811	27819	27809
80024	27814	208	1	6	1	1	0	0	883	0	166	1	0	0	59	108	27790	104	186	113	102	932	25	80010	10	80000	10	80000	50	1216205	1	27798	27851	27788	17765	3	17780	80012	20	80000	20	27815	27884	1	1	80021	10	9	0	10	10	80000	80000	0	10	80270	20	11	263	661	80696	78	1	119	40	675	80838	15000	30	93	15	780	30	338	19	34	48	5020	11	16	10	7	27796	113	0	10	19	9	80000	10	27769	27790	27776	27801	27771
80024	27766	208	1	0	2	0	0	0	896	0	116	0	32	0	18	60	27784	120	161	76	48	901	25	80010	10	80000	10	80000	50	1216588	0	27753	27747	27762	17798	3	17749	80010	20	80000	20	27803	27812	1	1	80021	10	9	0	10	10	80000	80000	0	10	80227	19	16	356	666	80972	149	5	108	52	756	80659	15000	30	114	16	621	30	353	19	26	35	5020	12	16	12	12	27814	134	0	22	15	9	80000	10	27791	27734	27800	27757	27774
80024	27774	208	1	1	1	1	0	1	851	0	105	1	0	0	20	108	28449	119	210	68	55	921	25	80010	10	80000	10	80000	50	1219189	1	27719	27810	27758	17788	3	17812	80010	20	80000	20	27846	27850	1	1	80021	10	9	0	10	10	80000	80000	0	10	80193	20	17	738	666	80747	165	0	153	44	733	80967	15000	30	83	15	675	30	337	19	51	42	5020	13	16	11	12	27813	119	0	21	11	10	80000	10	27793	27832	27835	27825	27760
80024	27772	208	1	0	3	0	0	0	738	0	73	0	0	0	31	28	27793	115	163	83	103	910	25	80010	10	80000	10	80000	50	1220393	0	27806	27860	27783	17747	3	17805	80010	20	80000	20	27795	27833	1	1	80021	10	9	0	10	10	80000	80000	0	10	80227	28	7	435	672	80773	131	3	209	24	808	80995	15000	30	112	16	802	30	399	19	32	48	5020	11	16	10	8	27851	114	0	26	17	12	80000	10	27817	27847	27824	27866	27809
80024	27866	208	1	2	1	0	0	0	775	0	112	1	0	0	16	92	27757	119	169	72	55	869	25	80010	10	80000	10	80000	50	1217069	0	27757	27765	27739	17677	3	17793	80010	20	80000	20	27775	27810	1	1	80021	10	9	0	10	10	80000	80000	0	10	80132	30	12	419	670	80677	158	2	138	18	662	80654	15000	30	80	9	614	30	324	19	38	40	5020	12	16	11	13	27867	130	0	16	13	19	80000	10	27822	27783	27763	27761	27787
80024	27821	207	1	1	0	0	0	0	808	0	92	1	0	0	12	88	27800	124	168	71	77	924	25	80010	10	80000	10	80000	50	1217657	0	27733	27760	27763	17718	3	17745	80010	20	80000	20	27792	27817	1	1	80021	10	9	0	10	10	80000	80000	0	10	80172	20	19	498	670	80755	157	3	156	18	660	80824	15000	30	147	12	673	30	319	19	49	181	5020	11	16	12	11	27810	125	0	35	27	12	80000	10	27819	27828	27780	27805	27787
80024	27833	208	1	3	0	1	0	0	777	0	76	2	56	1	20	64	27768	122	192	76	64	927	25	80010	10	80000	10	80000	50	1220050	0	27799	27777	27778	17785	24	17923	80010	20	80000	20	27876	27912	1	1	80021	10	9	0	10	10	80000	80000	0	10	80181	21	24	346	663	80821	115	2	107	0	731	80802	15000	30	102	25	866	30	287	19	9	136	5020	12	16	11	11	27794	115	0	24	14	13	80000	10	27949	27770	27858	27825	27763

LDR (literal, Q)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations