Firestorm: LDR (literal, S) measurements

Code:

  ldr s0, .+4

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 1.000

SIMD/FP unit issues: 0.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	l2 tlb miss data (0b)	0f	1e	20	22	23	3a	3f	40	43	46	4f	51	schedule uop (52)	schedule ldst uop (55)	dispatch ldst uop (58)	simd uops in schedulers (5a)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map ldst uop (7d)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst simd load (98)	inst ldst (9b)	9d	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	l1d cache miss ld (a3)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ab	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	c3	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	ea	eb	ec	? ldst retires (ed)	f5	f6	f7	f8	fd
1004	386	2	0	0	0	0	53	24	0	0	0	379	0	0	0	4	25	1000	1000	1000	14774	0	361	394	394	216	3	246	1000	1000	394	402	1	1	1001	1000	1000	0	1020	21	0	32	1039	0	0	0	0	50	1020	12	2	40	16	19	1	0	73	1	16	1	1	391	4	2	2	1000	400	388	395	389	395
1004	409	3	1	2	0	0	37	0	1	0	1	373	14	0	0	8	25	1000	1000	1000	15097	0	368	394	393	215	3	252	1000	1000	393	394	1	1	1001	1000	1000	0	1019	20	0	16	1029	2	0	5	12	44	1020	12	2	39	32	19	0	0	73	1	16	1	1	390	4	2	2	1000	389	388	396	389	394
1004	388	3	1	1	0	0	53	0	0	0	2	372	0	0	0	9	25	1000	1000	1000	14887	0	362	387	388	210	3	245	1000	1000	386	386	1	1	1001	1000	1000	0	1019	20	0	16	1029	0	0	0	6	47	1016	6	1	30	16	19	1	0	73	1	16	1	1	385	4	4	2	1000	389	405	396	402	389
1004	404	3	1	0	1	0	37	0	0	0	1	372	0	0	0	6	25	1000	1000	1000	14725	0	362	388	387	210	3	245	1000	1000	391	386	1	1	1001	1000	1000	0	1020	19	0	16	1029	1	0	6	0	31	1010	6	1	29	16	19	1	0	73	1	16	1	1	384	4	1	2	1000	388	389	389	388	388
1004	387	3	1	0	0	0	38	0	0	0	1	373	0	0	4	3	25	1000	1000	1000	14774	1	362	388	388	210	3	245	1000	1000	386	386	1	1	1001	1000	1000	1	1020	21	0	16	1029	1	0	0	6	37	1010	6	1	30	16	19	1	0	73	1	16	1	1	384	2	2	2	1000	388	387	387	388	388
1004	393	3	1	1	1	0	37	0	0	0	0	373	0	0	0	4	25	1000	1000	1000	14788	0	361	386	388	210	3	246	1000	1000	387	386	1	1	1001	1000	1000	0	1019	19	0	16	1029	0	0	0	4	54	1027	6	1	29	16	19	1	0	73	1	16	1	1	385	4	4	2	1000	389	388	389	388	388
1004	387	3	1	1	0	0	37	0	0	0	1	373	0	1	0	5	25	1000	1000	1000	15023	1	363	388	389	210	3	246	1000	1000	388	387	1	1	1001	1000	1000	0	1020	20	0	16	1029	1	0	1	6	41	1010	6	1	29	16	19	1	0	73	1	16	1	1	384	4	4	2	1000	388	388	388	389	388
1004	394	2	1	1	1	0	37	0	1	0	0	373	0	0	1	8	25	1000	1000	1000	15059	0	361	387	394	217	3	252	1000	1000	393	386	1	1	1001	1000	1000	0	1021	21	0	16	1029	0	0	0	6	37	1010	6	1	30	16	19	1	0	73	1	16	1	1	383	4	2	2	1000	389	389	388	389	388
1004	402	2	1	0	0	0	37	0	0	0	1	373	0	0	0	4	25	1000	1000	1000	14759	0	363	387	388	213	3	246	1000	1000	387	387	1	1	1001	1000	1000	0	1020	19	0	16	1029	1	0	0	4	53	1010	6	1	29	16	19	0	0	73	1	16	1	1	378	4	2	2	1000	388	389	389	388	389
1004	397	3	1	0	1	0	16	0	0	0	0	365	0	0	0	5	25	1000	1000	1000	14599	0	356	380	381	203	3	239	1000	1000	380	385	1	1	1001	1000	1000	1	1007	0	1	32	1010	0	0	0	10	20	1010	6	2	20	16	0	0	0	73	1	16	1	1	377	6	3	2	1000	381	381	382	387	388

Count: 8

Code:

  ldr s0, .+4
  ldr s0, .+4
  ldr s0, .+4
  ldr s0, .+4
  ldr s0, .+4
  ldr s0, .+4
  ldr s0, .+4
  ldr s0, .+4

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.3342

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	09	l2 tlb miss data (0b)	0e	18	19	1e	1f	20	22	3a	3e	3f	40	43	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	69	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	l1d cache miss ld (a3)	a5	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ab	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	c2	c3	cf	d5	map dispatch bubble (d6)	d8	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
80204	26731	200	1	62	1	1	0	0	0	111	0	0	0	7	0	26720	0	3	2	2	7	25	80100	100	80000	100	80000	500	1175193	0	26694	0	26716	26723	16646	3	16678	80100	200	80000	200	26718	26716	1	1	80201	100	99	100	100	80000	80000	0	100	80736	0	2	32	0	80042	127	3	208	0	185	80096	12	2	11	16	82	498	5110	2	16	0	2	2	26716	0	4	3	2	80000	100	26717	26719	26820	26724	26734
80204	26941	200	0	14	0	5	0	0	0	25	0	7	0	9	0	26697	6	2	0	0	6	25	80100	123	80000	100	80000	500	1168307	0	27452	0	26715	27161	16638	3	16675	80100	204	80000	202	27411	26713	4	1	80201	100	99	100	100	80000	80000	0	100	80789	61	1	32	119	80040	164	1	151	6	228	80139	6	2	11	16	252	422	5110	2	16	122	2	2	26709	22	4	3	2	80000	100	26714	26762	27268	26714	26714
80204	26931	200	0	2	0	8	0	0	0	6	0	6	1	20	0	26698	0	0	0	0	264	168	80100	100	80000	100	80712	500	1172001	1	26688	0	26713	27568	16636	30	17337	80100	200	80575	200	27273	26713	1	1	80201	100	99	100	100	80000	80000	0	100	80078	114	1	32	0	80402	83	0	90	0	145	80174	6	1	10	16	69	717	5110	2	16	0	2	2	27301	21	4	3	2	80000	100	26719	26714	26714	26714	26725
80204	26720	200	0	35	0	75	0	0	0	17	0	5	0	277	0	26697	6	2	0	0	3	25	80100	100	80130	100	80712	626	1166200	1	26688	0	26717	27167	16636	3	17217	80100	200	80000	200	26825	26713	1	1	80201	100	99	100	100	80000	80000	0	100	80248	97	0	16	35	80031	517	1	79	0	145	80185	12	3	10	16	187	155	5110	2	16	0	2	2	26757	0	4	3	2	80000	100	26721	26714	26713	26714	26723
80204	26866	200	0	0	0	91	0	0	0	17	0	12	1	14	0	26957	3	1	0	0	37	25	80100	100	80130	100	80178	500	1169079	0	26690	0	26867	26713	16635	3	16671	80100	200	80000	200	26713	26715	1	1	80201	100	99	100	100	80000	80000	0	100	80316	1	2	16	0	80042	618	4	162	6	70	80328	6	1	11	16	146	392	5110	2	16	0	2	2	26710	0	4	3	2	80000	100	26714	26714	26714	26714	26810
80204	26786	202	0	0	0	47	0	0	1	17	0	5	1	50	16	26852	0	0	0	0	3	25	80100	100	80000	100	80000	500	1168581	0	26828	0	26713	26925	16643	3	16671	80304	200	80000	200	26719	26712	3	1	80201	100	99	100	100	80000	80000	0	100	80420	35	1	16	0	80038	408	1	396	0	176	80178	6	1	12	16	406	212	5110	2	16	0	2	2	26724	0	4	3	2	80000	100	26714	26714	26714	26714	26723
80204	26867	200	0	0	0	66	0	0	0	48	0	4	1	1	0	26703	0	0	0	0	10	25	80100	123	80000	118	80000	570	1168304	0	26688	0	26713	26720	16635	10	16678	80479	200	80000	200	26713	26713	1	1	80201	100	99	100	100	80000	80000	0	100	80105	0	0	16	0	80033	81	2	128	0	55	80314	12	1	11	16	319	149	5110	2	16	0	2	2	26710	0	5	3	2	80000	100	26714	26719	26714	26724	26876
80204	26869	200	0	56	0	60	0	0	0	17	0	0	1	0	0	26854	5	1	0	0	107	25	80255	100	80130	100	80178	500	1171657	0	26688	0	26978	26719	16804	3	16667	80100	200	80190	200	26718	26978	1	1	80201	100	99	100	100	80000	80000	0	100	80346	186	0	16	0	80152	108	3	159	6	947	80104	12	2	21	32	451	142	5110	2	16	0	2	2	26710	0	5	3	2	80000	100	26720	26725	26720	26716	26718
80204	26852	200	0	53	0	22	0	0	0	2	0	5	0	265	20	26704	0	0	0	0	7	25	80100	100	80000	127	80000	601	1172522	1	26702	0	26718	26818	16642	3	16677	80100	200	80000	200	26713	26719	1	1	80201	100	99	100	100	80000	80000	0	100	80192	0	1	32	0	80013	94	1	86	16	116	80187	12	1	20	32	494	155	5110	2	33	0	2	2	26853	0	4	3	2	80000	100	26728	26724	26717	26724	26739
80204	26735	200	0	43	0	48	1	0	0	34	0	7	0	1	0	26699	12	0	0	0	3	25	80100	100	80000	100	80000	500	1166655	1	26695	0	26721	26713	16636	3	16689	80100	200	80000	200	26713	26713	1	1	80201	100	99	100	100	80000	80000	0	100	80130	3	3	16	0	80039	445	4	331	6	115	80025	6	1	10	16	74	155	5110	2	16	0	2	2	26710	0	4	3	2	80000	100	26925	26714	26715	26968	26714

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.3370

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	09	l2 tlb miss data (0b)	1e	20	22	23	29	2b	3a	3e	3f	40	43	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	92	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	l1d cache miss ld (a3)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ab	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	c2	c3	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	e7	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
80024	26977	201	0	1	0	283	90	1	0	0	0	11	56	26825	107	8	63	74	172	25	80010	10	80000	10	80000	50	1176109	26843	26850	26903	16841	3	16818	80010	20	80000	20	26820	26847	1	1	80021	10	9	0	10	10	80000	80000	0	10	80128	0	5	272	80272	170	2	163	20	502	80325	145	17	250	296	19	240	0	5020	5	16	3	3	26859	0	23	18	11	80000	10	26834	26842	26850	26828	26833
80024	26872	201	0	1	0	380	108	1	0	24	0	9	36	26839	107	6	40	33	75	25	80010	10	80000	10	80000	50	1173349	26817	26834	26828	16790	3	16822	80010	20	80000	20	26929	26915	1	1	80021	10	9	0	10	10	80000	80000	0	10	80136	0	23	338	80347	194	2	180	42	320	80501	110	22	253	262	65	129	0	5020	3	16	3	3	26844	0	32	23	17	80000	10	26918	26878	26926	26868	26880
80024	26920	201	0	0	0	470	115	1	0	0	0	9	36	26785	120	12	32	21	69	25	80010	10	80000	10	80000	50	1176462	26787	26837	26841	16781	3	16802	80010	20	80000	20	26846	26894	1	1	80021	10	9	0	10	10	80000	80000	0	10	80147	2	17	346	80319	105	3	173	64	391	80340	130	23	293	347	49	110	0	5020	2	16	2	3	26848	0	27	30	20	80000	10	26901	26892	26904	26913	26887
80024	26851	201	1	1	0	353	63	1	0	0	1	37	0	26840	71	6	56	52	96	25	80010	10	80000	10	80000	50	1176927	26834	26843	26860	16787	3	16838	80010	20	80000	20	26867	26851	1	1	80021	10	9	1	10	10	80000	80000	0	10	80164	0	11	301	80300	132	3	217	22	340	80445	111	25	279	380	24	219	0	5020	3	16	2	3	26854	0	25	19	12	80000	10	26829	26877	26868	26842	26825
80024	26959	201	0	0	0	409	143	0	0	0	0	9	60	26843	85	7	19	52	77	25	80010	10	80000	10	80000	50	1183176	26857	26850	27349	16823	3	16827	80368	20	80000	20	26857	26869	1	1	80021	10	9	0	10	10	80000	80000	0	10	80122	0	13	311	80217	103	4	178	86	284	80380	76	14	185	250	35	269	0	5020	2	16	3	3	26848	0	26	33	11	80000	10	26840	26878	26820	26825	26837
80024	26940	201	0	0	5	355	24	1	0	24	0	13	72	26831	72	10	85	49	87	25	80010	10	80000	10	80000	50	1178183	26793	26850	26875	16826	3	16837	80010	20	80000	20	26883	26883	1	1	80021	10	9	1	10	10	80000	80000	0	10	80111	0	6	279	80228	157	2	103	36	268	80564	131	15	196	277	10	121	0	5020	3	16	3	3	26848	0	22	24	10	80000	10	26818	26864	26853	26855	26864
80024	27030	202	6	2	0	370	119	0	0	0	1	11	64	26860	97	5	39	72	102	25	80010	10	80000	10	80000	50	1174223	26881	26850	26823	16769	3	16878	80010	20	80000	20	26971	26823	1	1	80021	10	9	0	10	10	80000	80000	0	10	80089	0	17	272	80226	133	2	155	30	406	80407	174	20	253	325	12	110	0	5020	3	16	3	2	26850	0	28	18	10	80000	10	26859	26869	26860	26923	26914
80024	27008	201	0	0	0	321	68	1	0	24	0	8	80	26853	116	11	38	25	81	25	80010	10	80000	10	80000	50	1174824	26866	26810	26828	16824	3	16848	80010	20	80000	20	26874	26859	1	1	80021	10	9	0	10	10	80000	80000	0	10	80144	0	8	367	80250	192	2	131	62	373	80468	130	15	209	269	72	656	0	5020	3	16	3	3	26840	0	32	19	18	80000	10	26859	26877	26937	26859	26836
80024	26970	201	1	0	0	376	67	1	0	0	0	5	44	26801	78	5	50	47	81	25	80010	10	80000	10	80000	50	1177101	26782	26838	26847	16842	3	16830	80546	20	80000	20	26889	26861	1	1	80021	10	9	0	10	10	80000	80000	0	10	80075	0	13	478	80279	90	3	103	66	368	80415	188	20	254	433	45	75	0	5020	3	16	3	3	26889	0	15	22	11	80000	10	26810	26842	26824	26837	26841
80024	27004	201	0	0	0	425	21	0	0	0	0	12	32	26824	84	6	47	42	80	25	80010	10	80000	10	80000	50	1177944	26828	27055	26844	16759	3	16843	80010	20	80000	20	26864	26852	1	1	80021	10	9	0	10	10	80000	80000	0	10	80207	2	16	331	80193	170	3	164	50	297	80369	101	17	196	243	61	154	0	5020	3	16	4	3	26834	1	29	17	7	80000	10	26866	26870	26844	26848	26849

LDR (literal, S)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations