Firestorm: LDR (post-index, D) measurements

Code:

  ldr d0, [x6], #8

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 2.000

Integer unit issues: 1.000

Load/store unit issues: 1.000

SIMD/FP unit issues: 0.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	l2 tlb miss data (0b)	0e	0f	1e	20	22	2b	3a	3e	3f	40	43	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map ldst uop (7d)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst simd load (98)	inst ldst (9b)	9d	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	l1d cache miss ld (a3)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ab	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	c2	c3	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
1005	1055	8	0	0	0	0	74	17	1	0	3	12	1025	16	15	5	7	19	25	2000	1000	1000	1000	1000	50762	45824	1015	1040	1040	824	3	898	2000	1000	1000	1040	1040	1	1	1001	1000	1000	2	1020	0	0	69	1038	2	1	17	8	27	1040	48	6	24	48	0	0	73	1	16	1	1	1037	1000	41	36	0	1000	1000	1041	1041	1041	1041	1041
1004	1040	8	0	0	0	0	74	25	1	0	2	28	1025	11	13	0	20	19	25	2000	1000	1000	1000	1000	50762	45824	1015	1040	1040	824	3	898	2000	1000	1000	1040	1040	1	1	1001	1000	1000	0	1014	0	0	54	1022	0	1	0	12	40	1053	24	4	31	72	0	0	73	1	16	1	1	1037	1000	35	34	0	1000	1000	1041	1041	1041	1041	1041
1004	1040	7	0	0	0	0	52	19	0	0	1	0	1025	0	14	1	14	24	25	2000	1000	1000	1000	1000	50762	45824	1015	1040	1040	824	3	898	2000	1000	1000	1040	1040	1	1	1001	1000	1000	2	1024	0	7	45	1024	0	7	0	0	24	1024	36	6	31	72	0	0	73	1	16	1	1	1037	1000	35	33	0	1000	1000	1041	1041	1041	1041	1041
1004	1040	7	0	0	0	0	62	12	0	0	2	4	1025	12	14	1	24	12	25	2000	1000	1000	1000	1000	50762	45824	1015	1040	1040	824	3	898	2000	1000	1000	1040	1040	1	1	1001	1000	1000	2	1016	0	0	45	1027	2	0	17	12	38	1044	24	6	27	32	0	0	73	1	16	1	1	1037	1000	33	30	0	1000	1000	1041	1041	1041	1041	1041
1004	1040	8	0	0	0	0	73	12	0	0	1	0	1025	13	17	3	7	12	25	2000	1000	1000	1000	1000	50778	45824	1015	1040	1040	824	3	898	2000	1000	1000	1040	1040	1	1	1001	1000	1000	2	1022	0	0	34	1039	3	3	15	0	24	1067	36	6	29	56	0	0	73	1	16	1	1	1037	1000	36	36	0	1000	1000	1041	1041	1041	1041	1041
1004	1040	8	0	0	0	0	67	16	0	0	1	0	1025	0	13	1	11	20	25	2000	1000	1000	1000	1000	50746	45824	1015	1040	1040	824	3	898	2000	1000	1000	1040	1040	1	1	1001	1000	1000	2	1020	12	0	72	1042	9	1	0	0	32	1025	41	5	27	48	0	0	73	1	16	1	1	1037	1000	33	33	0	1000	1000	1041	1041	1041	1041	1041
1004	1040	8	0	0	0	0	69	15	1	0	1	0	1025	9	18	3	14	20	25	2000	1000	1000	1000	1000	50770	45824	1015	1040	1040	824	3	898	2000	1000	1000	1040	1040	1	1	1001	1000	1000	2	1019	0	0	68	1039	2	1	17	10	30	1051	36	7	28	48	0	0	73	1	16	1	1	1037	1000	42	32	0	1000	1000	1041	1041	1041	1041	1041
1004	1040	8	0	0	0	0	60	13	1	0	2	0	1025	10	14	3	21	21	25	2000	1000	1000	1000	1000	50754	45824	1015	1040	1040	824	3	898	2000	1000	1000	1040	1040	1	1	1001	1000	1000	2	1020	0	0	54	1045	1	0	13	12	27	1047	47	6	25	56	0	0	73	1	16	1	1	1037	1000	33	32	0	1000	1000	1041	1041	1041	1041	1041
1004	1040	8	0	0	0	0	82	28	0	0	2	0	1025	0	15	11	8	21	25	2000	1000	1000	1000	1000	50762	45824	1015	1040	1040	824	3	898	2000	1000	1000	1040	1040	1	1	1001	1000	1000	2	1000	0	0	79	1044	3	1	13	12	24	1040	30	6	29	56	0	0	73	1	16	1	1	1037	1000	33	39	0	1000	1000	1041	1041	1041	1041	1041
1004	1040	8	0	0	0	0	61	15	1	0	0	4	1025	12	12	0	5	21	25	2000	1000	1000	1000	1000	50770	45824	1015	1040	1040	824	3	898	2000	1000	1000	1040	1040	1	1	1001	1000	1000	2	1016	0	0	73	1038	3	1	16	4	29	1040	36	5	26	48	0	0	73	1	16	1	1	1037	1000	38	36	0	1000	1000	1041	1041	1041	1041	1041

Test 2: Latency 1->2 roundtrip

Chain cycles: 3

Code:

  ldr d0, [x6], #8
  fmov x0, d0
  eor x8, x8, x0
  eor x8, x8, x0
  add x6, x6, x8

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 9.1890

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	09	l2 tlb miss instruction (0a)	l2 tlb miss data (0b)	0f	18	19	1e	1f	20	22	23	29	3a	3e	3f	40	43	49	4d	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	l1d cache miss ld (a3)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ab	ac	af	b5	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	c3	branch cond mispred nonspec (c5)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
50209	121944	914	0	0	0	0	0	0	0	0	622	0	821	1	0	776	0	108	121528	821	5	4	121452	25	70481	50398	10151	10000	40100	10000	10000	1076184	4603827	4649788	121748	121790	121694	115019	3	115353	60100	30200	10000	10000	60200	10000	10000	121673	121771	1	1	50201	100	99	100	40100	10000	10000	1	100	11022	0	115	550	10705	201	12	927	48	41	10933	144	5	126	2	0	3	0	3210	1	76	1	1	121561	50260	930	852	868	10000	50100	121979	121794	121915	121732	121635
50204	121814	911	0	0	0	0	0	0	0	4	616	0	844	1	0	688	0	180	121882	811	8	3	121549	25	70529	50354	10140	10000	40100	10000	10000	1077819	4605545	4654999	121936	121827	121794	115059	3	115456	60100	30200	10000	10000	60200	10000	10000	121743	121763	1	1	50201	100	99	100	40100	10000	10000	0	100	10923	0	118	551	10713	207	11	908	66	40	10911	131	3	118	1	0	6	0	3210	1	76	1	1	121438	50274	892	864	902	10000	50100	121655	121641	121625	121893	121733
50204	121653	912	0	0	0	0	0	0	0	0	573	0	814	1	0	720	1	116	121777	818	5	0	121382	25	70493	50390	10133	10000	40100	10000	10000	1078071	4607147	4650366	121674	121833	121769	114886	3	115510	60100	30200	10000	10000	60200	10000	10000	121848	121819	1	1	50201	100	99	100	40100	10000	10000	0	100	10908	0	117	536	10685	222	15	908	48	32	10911	129	5	123	1	0	5	0	3210	1	76	1	1	121456	50272	826	860	781	10000	50100	121647	121902	121760	121831	121939
50205	121810	913	0	0	0	0	0	0	0	0	592	0	825	1	0	712	0	144	121831	796	6	3	121663	25	70505	50362	10130	10000	40100	10000	10000	1076905	4603952	4652408	121745	121802	121632	115002	3	115283	60100	30200	10000	10000	60200	10000	10000	121700	121591	1	1	50201	100	99	100	40100	10000	10000	0	100	10980	2	119	543	10720	195	9	923	42	43	10958	130	7	125	1	0	12	0	3210	1	76	1	1	121565	50268	862	866	701	10000	50100	121664	121740	121624	121824	121782
50204	121860	912	1	1	0	0	0	0	0	0	570	0	801	1	0	744	1	116	121789	818	5	0	121477	25	70478	50352	10116	10000	40100	10000	10000	1077639	4602212	4646695	121805	121918	121617	115183	3	115328	60100	30200	10000	10000	60200	10000	10000	121748	121713	1	1	50201	100	99	100	40100	10000	10000	0	100	10912	2	123	545	10714	213	12	910	50	47	10911	128	5	119	2	4	7	0	3210	1	76	1	1	121532	50260	918	1030	755	10000	50100	121772	121693	121887	121714	121835
50204	121830	913	0	0	0	0	0	0	0	0	537	0	806	1	0	704	0	112	121724	833	7	2	121413	25	70490	50336	10113	10000	40100	10000	10000	1079011	4598138	4648246	121809	121644	121779	114991	3	115440	60100	30200	10000	10000	60496	10000	10000	121780	121688	1	1	50201	100	99	100	40100	10000	10000	0	100	10914	0	120	549	10718	214	14	927	72	38	10925	110	5	129	1	0	8	0	3210	1	76	1	0	121340	50254	848	872	781	10000	50100	121777	121658	121716	121745	121889
50204	121715	912	0	0	0	0	0	0	0	4	609	0	839	1	0	688	0	128	121684	806	4	0	121501	25	70490	50382	10138	10000	40100	10000	10000	1077018	4607842	4648257	121776	121707	121823	114963	3	115420	60100	30200	10000	10000	60200	10000	10000	121730	121909	1	1	50201	100	99	100	40100	10000	10000	0	100	10905	0	120	563	10722	207	12	892	50	41	10919	118	5	127	1	0	12	0	3210	1	76	1	1	121349	50254	904	848	830	10000	50100	121783	121771	121747	121799	121808
50204	121890	914	0	0	0	0	0	0	0	0	560	0	829	1	0	704	0	136	121644	808	4	2	122865	638	70934	50670	10211	10052	44097	11033	11060	1140236	4662249	4703773	123665	124495	124531	116354	231	116997	65873	33681	11136	11158	67090	11128	11159	124314	124450	30	1	50201	100	99	100	40100	10000	10000	0	100	10907	0	118	541	10714	217	10	906	48	19699	10918	119	4	122	1	0	10	1	3872	1	293	2	2	123722	50562	891	920	763	10000	50100	124401	124577	124414	123672	124607
50204	123882	932	0	0	0	1	1	0	0	0	2348	3256	805	1	0	712	0	136	124028	784	5	2	121630	210	70481	50342	10157	10050	42956	10995	10975	1122508	4655749	4701686	121940	121786	122012	114978	3	115345	60100	30325	10000	10000	60200	10000	10000	121681	121980	1	1	50201	100	99	100	40100	10000	10000	0	100	10932	0	119	522	10718	203	12	981	74	37	10931	127	5	134	0	0	4	0	3210	1	76	1	1	121767	50262	1079	1048	970	10000	50100	122048	121775	122041	121890	121988
50204	121847	913	0	0	0	0	0	0	0	0	448	0	802	0	1	744	0	100	121962	814	3	0	121669	25	70508	50348	10152	10000	40100	10000	10000	1079561	4609277	4656513	121911	122068	122073	115136	3	115591	60100	30200	10000	10000	60200	10000	10000	121838	121805	1	1	50202	100	99	100	40100	10000	10000	0	100	10905	0	104	555	10684	210	10	940	56	37	10931	124	4	126	0	15	4	0	3210	1	76	1	1	121619	50278	1022	1146	957	10000	50100	121951	121885	122043	122006	121907

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 9.1840

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk instruction (07)	mmu table walk data (08)	09	l2 tlb miss data (0b)	0e	0f	19	1e	1f	20	22	29	3a	3e	3f	40	43	4d	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	69	6b	6d	6e	map stall dispatch (70)	int prf full (71)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	l1d cache miss ld (a3)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ab	ac	af	b5	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	c3	cf	d5	map dispatch bubble (d6)	da	db	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
50029	122076	913	2	0	0	0	0	1	0	0	508	264	833	1	608	2	104	121763	785	1	121559	25	70409	50264	10131	10000	40010	10046	10000	1077547	4606272	4649752	1	121838	0	121848	121581	115040	0	3	115588	60010	30020	10000	10000	60020	10000	10000	121838	121885	1	1	50021	10	9	10	40010	10000	10000	0	10	10892	3	121	514	10665	194	12	925	26	22	10925	143	3	123	2	3	7	3140	4	82	0	0	4	9	121480	50268	970	1002	961	10000	50010	121924	121890	121803	121984	122022
50024	121953	911	2	0	0	0	2	0	0	0	477	0	803	1	696	2	108	121771	793	1	121512	25	70403	50276	10128	10000	40010	10000	10000	1076818	4607009	4658281	1	121897	0	121809	121754	115047	0	3	115464	60010	30020	10000	10000	60020	10000	10000	121834	121799	1	1	50021	10	9	10	40010	10000	10000	1	10	10920	2	112	549	10698	217	12	900	78	15	10891	130	3	114	2	0	7	3140	7	82	0	0	9	4	121471	50232	1024	1044	893	10000	50010	121814	121970	121861	121888	121762
50024	121936	912	2	0	0	0	0	0	0	0	507	0	775	1	728	2	100	121675	779	1	121489	25	70367	50240	10126	10000	40010	10000	10000	1077079	4601788	4652218	1	121997	0	121781	121786	115099	0	3	115443	60010	30020	10000	10049	60020	10000	10000	121983	121781	1	1	50021	10	9	10	40010	10000	10000	1	10	10911	2	120	540	10696	188	9	886	76	24	10888	121	3	125	2	0	4	3140	3	82	0	0	3	4	121550	50252	1000	1134	881	10000	50010	122056	121629	121926	121807	121796
50024	121743	913	2	0	0	0	0	0	0	0	502	0	771	1	712	2	108	121785	793	1	121474	25	70400	50268	10127	10000	40010	10000	10000	1076791	4602806	4652533	1	122018	0	121598	121823	114943	0	3	115425	60010	30020	10000	10000	60020	10000	10000	121707	121705	1	1	50021	10	9	10	40010	10000	10000	0	10	10955	3	104	523	10698	206	8	961	72	16	10972	129	4	120	3	6	9	3140	4	17	0	0	7	4	121504	50252	911	1074	900	10000	50010	121802	121886	121873	121749	121862
50024	121840	912	2	0	0	0	0	0	0	0	433	0	803	1	704	3	100	121613	744	1	121351	25	70340	50250	10123	10000	40010	10000	10000	1078402	4607092	4650318	0	121802	0	122044	121849	115266	0	3	115491	60010	30020	10000	10000	60020	10000	10000	121750	121697	1	1	50021	10	9	10	40010	10000	10000	0	10	10916	4	117	522	10736	201	10	899	80	32	10917	118	5	127	4	0	3	3140	4	82	0	0	4	4	121448	50248	994	935	945	10000	50010	121855	121766	121806	121601	121883
50024	121777	914	4	0	1	0	0	0	0	0	427	0	809	1	712	3	100	121791	789	1	121547	25	70412	50238	10127	10000	40010	10000	10000	1081880	4617199	4659027	1	121838	0	122035	121872	114972	0	3	115450	60010	30020	10000	10000	60020	10000	10000	121890	121882	1	1	50021	10	9	10	40010	10000	10000	0	10	10906	2	115	516	10722	203	11	916	76	21	10904	128	3	127	2	0	5	3140	3	82	0	0	6	4	121389	50250	1009	1059	876	10000	50010	121837	121837	121895	121824	121815
50024	121897	912	2	0	0	0	0	1	0	0	415	0	811	1	720	2	108	121559	776	1	121223	25	70394	50266	10155	10000	40010	10000	10000	1078915	4605103	4653444	1	121814	0	121895	121891	115116	0	3	115591	60010	30020	10000	10000	60020	10000	10000	121746	122078	1	1	50021	10	9	10	40010	10000	10000	0	10	10904	6	112	510	10730	196	8	876	74	16	10929	134	4	117	3	0	4	3140	4	82	0	0	4	7	121571	50230	1002	1083	907	10000	50010	121759	121842	121728	121874	121730
50024	121759	913	2	0	0	2	0	0	0	0	423	0	815	1	688	2	108	121828	776	2	121386	25	70367	50248	10112	10000	40010	10000	10000	1076485	4608091	4657612	1	121887	0	121990	121924	115035	0	3	115539	60010	30020	10000	10000	60020	10000	10000	121614	121874	1	1	50021	10	9	10	40010	10000	10000	0	10	10913	2	108	500	10687	210	10	872	68	12	10913	131	3	114	2	0	13	3140	4	82	0	0	4	3	121454	50248	1085	1065	828	10000	50010	121799	121885	121814	121691	121809
50024	121973	913	2	0	0	0	0	0	0	0	472	0	808	1	688	3	108	121818	781	1	121331	25	70370	50256	10120	10000	40010	10000	10000	1079239	4605913	4655375	1	121785	0	121997	121781	115033	0	3	115665	60010	30020	10000	10000	60020	10000	10000	121834	121891	1	1	50021	10	9	10	40010	10000	10000	0	10	10927	3	112	540	10688	198	8	903	70	25	10885	131	5	112	4	0	13	3140	3	82	0	0	4	3	121462	50248	965	1001	855	10000	50010	121894	121902	121814	121953	121721
50024	121852	913	4	0	0	0	1	0	1	0	445	0	871	1	744	3	68	122013	800	1	121529	25	70418	50254	10136	10000	40010	10000	10000	1077745	4606804	4648088	1	121827	0	122287	121831	115177	0	3	115480	60010	30020	10000	10000	60020	10000	10000	121838	121943	1	1	50021	10	9	10	40010	10000	10000	0	10	10870	6	110	525	10694	206	8	914	74	15	10883	121	3	117	2	0	3	3140	3	82	0	0	4	3	121648	50244	920	1017	967	10000	50010	121830	121945	121764	121812	121830

Test 3: throughput

Count: 8

Code:

  ldr d0, [x6], #8
  ldr d0, [x7], #8
  ldr d0, [x8], #8
  ldr d0, [x9], #8
  ldr d0, [x10], #8
  ldr d0, [x11], #8
  ldr d0, [x12], #8
  ldr d0, [x13], #8

Initialization

  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.3664

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	09	l2 tlb miss data (0b)	0e	0f	18	19	1e	20	22	29	3a	3e	3f	40	43	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	67	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	92	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	l1d cache miss ld (a3)	a5	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ab	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	c3	branch mispred nonspec (cb)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	e7	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
80209	29981	220	0	0	0	0	0	1	0	0	7110	828	1	760	121	144	29164	879	463	2087	2109	2189	25	160145	80139	80000	80100	80000	400810	1297851	1	56	29124	29111	29242	19055	3	19227	160100	200	80000	200	80000	29251	29487	1	1	80201	100	99	21	100	100	80000	80000	0	100	80914	0	438	4923	32	84967	774	16	942	30	5416	85790	734	147	4641	5174	0	0	0	0	5110	1	17	1	1	29226	32	80044	541	431	75	80000	80100	29206	29180	29245	29335	29082
80204	29334	218	1	0	1	0	0	0	0	0	6566	846	1	792	114	296	29227	886	501	2100	2043	2186	25	160152	80136	80000	80100	80000	400809	1289810	1	46	29442	29153	29305	19375	3	19424	160100	200	80000	200	80000	29392	29128	1	1	80201	100	99	11	100	100	80000	80000	0	100	80984	0	420	5437	0	85251	762	8	940	36	5333	85912	742	138	5000	5041	0	0	3	0	5110	1	16	1	1	29252	36	80039	468	438	74	80000	80100	29294	29357	29269	29304	29295
80204	29350	218	0	0	0	0	0	0	0	0	6424	838	1	736	107	104	29235	871	408	2077	2108	1839	25	160148	80143	80000	80100	80000	400745	1288059	1	38	29196	29288	29178	19333	3	19142	160100	200	80000	200	80000	29047	29130	1	1	80201	100	99	11	100	100	80000	80000	0	100	80908	0	399	5070	0	84866	797	10	960	24	4762	85640	766	130	5140	5043	0	0	3	0	5110	1	17	1	1	29397	36	80043	500	440	66	80000	80100	29176	29314	29227	29325	29172
80204	29157	220	0	0	0	0	0	0	0	0	6961	817	1	728	107	100	29344	840	462	2114	2238	2091	25	160146	80155	80000	80100	80000	400742	1296933	1	53	29296	29183	29278	19267	3	19302	160100	200	80000	200	80000	29341	29119	1	1	80201	100	99	21	100	100	80000	80000	0	100	80893	0	440	5671	0	85270	718	13	950	38	4917	86258	802	129	4515	5510	0	0	9	0	5110	1	17	1	1	29344	32	80042	442	448	66	80000	80100	29233	29250	29300	29460	29355
80204	29280	220	0	0	0	0	1	0	0	0	6883	843	1	696	113	124	29852	856	452	2079	2016	2122	25	160154	80146	80000	80100	80000	400798	1295039	0	41	29196	29147	29527	19310	3	19308	160100	200	80000	200	80000	29274	29288	1	1	80201	100	99	15	100	100	80000	80000	0	100	80938	0	484	5760	30	85051	792	9	930	80	4781	85268	764	152	4974	4869	0	0	6	0	5110	1	25	1	1	29186	33	80050	501	433	90	80000	80100	29332	29600	29325	29310	29292
80204	29434	218	0	0	0	0	0	0	0	0	6791	820	1	736	108	108	29231	854	438	2167	1988	2089	60	160460	80137	80000	80100	80178	401648	1287702	0	56	29203	29052	29366	19310	3	19399	160100	200	80000	202	80192	29335	29306	1	1	80201	100	99	23	100	100	80000	80000	0	100	80928	0	412	5072	0	85119	773	9	916	76	4974	86156	844	136	4862	5180	0	3	3	0	5110	1	17	1	1	29381	34	80038	403	449	51	80000	80100	29230	29268	29333	29232	29265
80204	29304	218	0	0	0	0	0	0	0	0	6801	837	1	752	106	152	29314	856	404	2082	2210	2100	25	160141	80155	80000	80100	80000	400733	1290823	0	41	29252	29391	29400	19232	3	19152	160100	200	80000	200	80000	29215	29407	1	1	80201	100	99	19	100	100	80000	80000	0	100	80956	19	432	5102	0	85447	780	13	943	78	5716	85967	820	132	5282	5503	19	0	6	0	5110	1	17	1	1	29490	32	80045	468	416	64	80000	80100	29172	29267	29173	29379	29462
80204	29393	221	1	0	1	0	0	0	0	0	7049	847	1	744	121	136	29240	855	431	1916	2275	2024	25	160146	80147	80000	80100	80000	400747	1284945	0	39	29211	29389	29172	19237	3	19194	160100	200	80000	200	80000	29517	29088	1	1	80201	100	99	32	100	100	80000	80000	0	100	80958	21	485	5434	0	85671	767	10	953	80	4773	85961	834	141	5249	5071	19	0	5	0	5110	1	16	1	1	29348	23	80040	504	483	69	80000	80100	29463	29321	29224	29221	29419
80204	29357	219	1	0	0	1	0	0	0	0	6611	822	1	736	103	156	29286	842	447	1954	1916	1954	25	160142	80148	80000	80100	80000	400718	1293499	0	42	29175	29168	29270	19532	3	19068	160100	200	80000	200	80000	29381	29378	1	1	80201	100	99	22	100	100	80000	80000	0	100	80963	19	418	5278	0	85517	764	14	868	30	5040	85828	794	116	5311	5560	19	1	8	0	5110	1	16	1	1	29233	49	80043	436	462	80	80000	80100	29155	29445	29371	29371	29531
80204	29449	220	1	1	1	1	0	1	1	1	7143	855	1	680	136	92	29337	850	415	1998	2195	2182	25	160155	80341	80000	80100	80356	401711	1283302	0	47	29300	29110	29296	19113	18	19209	160100	200	80000	200	80000	29317	29361	1	1	80201	100	99	30	100	100	80000	80000	0	100	80962	19	464	5057	0	85142	721	13	920	34	5451	85999	844	149	4660	5564	19	4	4	0	5110	1	17	1	1	29435	47	80051	489	450	77	80000	80100	29275	29333	29198	29245	29131

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.3679

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	l2 tlb miss data (0b)	0e	0f	1e	20	22	29	3a	3e	3f	40	43	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	67	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	92	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	l1d cache miss ld (a3)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ab	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	c3	cf	d5	map dispatch bubble (d6)	d9	dd	fetch restart (de)	e0	e7	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
80029	30008	220	1	0	0	0	1	6706	818	1	720	124	144	29603	809	579	1849	1775	2109	25	160058	80059	80000	80010	80000	400295	1294411	51	29402	29493	29420	19449	3	19500	160010	20	80000	20	80000	29364	29492	1	1	80021	10	9	35	10	10	80000	80000	0	10	80949	20	409	5874	85301	666	13	908	48	4796	86027	904	137	5352	5502	34	1	3	5020	9	16	0	4	3	29299	40	80043	632	628	84	80000	80010	29328	29403	29505	29642	29698
80024	29597	219	2	0	0	0	0	6464	812	1	720	119	112	29568	796	533	1926	1895	2171	25	160046	80060	80000	80010	80000	400267	1296459	38	29343	29503	29492	19164	3	19326	160010	20	80000	20	80000	29504	29497	1	1	80021	10	9	41	10	10	80000	80000	0	10	80935	37	351	5062	85407	615	10	905	48	4642	86249	790	127	5422	5316	36	3	7	5020	3	16	0	4	3	29474	24	80051	584	628	105	80000	80010	29548	29610	29544	29522	29512
80024	29371	220	2	2	2	1	0	6654	794	1	736	122	352	29396	798	614	1760	1636	2105	25	160050	80055	80000	80010	80000	400319	1297254	53	29496	29555	29396	19439	3	19396	160010	20	80000	20	80000	29420	29538	1	1	80021	10	9	45	10	10	80000	80000	0	10	80953	38	404	5266	85445	648	10	903	42	5222	86178	779	123	5198	5514	34	0	4	5020	4	16	0	6	4	29473	25	80040	657	596	124	80000	80010	29605	29325	29440	29440	29580
80024	29607	220	2	1	0	0	1	6363	828	1	680	108	140	29549	762	523	1740	1969	2263	25	160051	80063	80000	80010	80000	400268	1310290	44	29431	29487	29480	19366	3	19552	160010	20	80000	20	80000	29591	29548	1	1	80021	10	9	40	10	10	80000	80000	0	10	80911	40	413	4895	85259	668	8	914	138	4684	85783	777	137	5593	5189	37	3	316	5020	6	16	0	3	4	29385	32	80042	584	658	103	80000	80010	29478	29739	29432	29545	29466
80024	29479	221	2	1	0	0	0	6767	807	1	768	119	112	29451	796	560	1543	1908	2275	25	160043	80061	80000	80010	80000	400330	1292802	49	29430	29425	29513	19471	3	19245	160010	20	80000	20	80000	29338	29227	1	1	80021	10	9	37	10	10	80000	80000	0	10	80943	36	406	4958	85263	612	13	882	74	5325	85449	818	125	5039	5400	32	0	8	5020	4	16	0	3	4	29539	27	80047	609	571	104	80000	80010	29460	29540	29395	29296	29423
80024	29343	222	2	0	0	0	0	6160	822	1	672	125	124	29517	782	534	1568	1904	2191	25	160048	80054	80000	80010	80000	400326	1295485	46	29250	29368	29492	19392	3	19197	160010	20	80000	20	80000	29385	29444	1	1	80021	10	9	20	10	10	80000	80000	1	10	80970	37	376	5506	85333	695	13	852	74	5326	85951	747	137	5467	5464	38	3	7	5020	7	16	0	3	5	29411	30	80043	580	573	99	80000	80010	29475	29440	29476	29426	29542
80024	29518	220	2	0	0	0	0	7079	811	1	664	115	112	29410	773	516	1709	1785	2227	25	160065	80061	80000	80010	80000	400253	1304301	38	29470	29234	29262	19576	3	19375	160010	20	80000	20	80000	29327	29476	1	1	80021	10	9	43	10	10	80000	80000	0	10	80916	40	391	6093	85963	696	12	928	48	5161	86020	738	118	5004	5148	34	0	3	5020	7	16	0	6	6	29480	40	80045	568	608	108	80000	80010	29341	29478	29559	29637	29416
80024	29560	220	2	0	1	0	0	6867	832	1	744	121	104	29273	794	522	1505	1928	2390	25	160060	80056	80000	80010	80000	400310	1306047	49	29310	29447	29355	19569	3	19420	160010	20	80000	20	80000	29439	29390	1	1	80021	10	9	37	10	10	80000	80000	0	10	80936	35	369	5267	85439	689	8	956	42	5180	86060	721	127	5666	5208	37	4	4	5020	6	16	0	7	4	29503	24	80047	596	652	105	80000	80010	29311	29444	29375	29800	29369
80024	29376	220	2	0	0	0	0	6853	814	1	704	114	132	29379	766	464	1668	1961	2106	25	160049	80059	80000	80010	80000	400340	1295121	46	29394	29382	29405	19478	3	19461	160010	20	80000	20	80000	29405	29398	1	1	80021	10	9	52	10	10	80000	80000	0	10	80973	33	436	5763	84562	679	8	948	80	4544	85825	747	126	4776	5224	37	0	6	5020	7	16	0	3	4	29467	33	80048	596	596	119	80000	80010	29382	29501	29338	29732	29502
80024	29395	220	2	0	1	0	0	6849	798	1	696	125	92	29431	748	543	1530	1834	2139	25	160053	80057	80000	80010	80000	400275	1301003	29	29402	29466	29565	19432	3	19482	160010	20	80000	20	80000	29493	29317	1	1	80021	10	9	39	10	10	80000	80000	0	10	80943	37	364	5820	85545	629	9	887	74	5750	86176	730	139	5387	5435	36	3	7	5020	6	16	0	6	9	29579	35	80040	675	602	108	80000	80010	29443	29436	29399	29446	29442

LDR (post-index, D)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->2 roundtrip

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations