Firestorm: LDR (post-index, Q) measurements

Code:

  ldr q0, [x6], #8

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 2.000

Integer unit issues: 1.000

Load/store unit issues: 1.000

SIMD/FP unit issues: 0.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	l2 tlb miss data (0b)	0e	0f	1e	20	22	23	29	3a	3e	3f	40	43	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map ldst uop (7d)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst simd load (98)	inst ldst (9b)	9d	l1d tlb access (a0)	l1d cache miss st (a2)	l1d cache miss ld (a3)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	aa	ab	ac	af	ldst x64 uop (b1)	b5	b6	bb	l1d cache miss ld nonspec (bf)	c2	c3	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	e7	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
1005	1059	8	1	0	0	0	97	0	0	0	0	3	12	1025	62	5	6	14	37	25	2000	1000	1000	1000	1000	50746	45823	1	1015	1041	1040	824	3	897	2000	1000	1000	1040	1040	1	1	1001	1000	1000	0	1036	2	85	1054	8	1	35	0	8	34	1055	125	67	8	38	85	0	0	73	2	16	2	2	1037	0	1000	47	35	0	1000	1000	1041	1041	1041	1041	1041
1004	1040	7	0	0	0	0	96	24	1	0	0	5	0	1025	43	4	4	10	25	25	2000	1000	1000	1000	1000	50738	45824	1	1015	1040	1040	824	3	898	2000	1000	1000	1040	1040	1	1	1001	1000	1000	0	1024	0	80	1047	6	0	25	0	0	57	1035	125	39	9	32	78	0	0	73	2	16	2	2	1037	0	1000	35	29	0	1000	1000	1041	1041	1041	1041	1041
1004	1040	8	0	0	0	0	88	0	1	0	0	5	24	1025	42	5	6	6	24	25	2000	1000	1000	1000	1000	50738	45823	0	1015	1040	1040	824	3	898	2000	1000	1000	1040	1040	1	1	1001	1000	1000	0	1008	0	96	1062	10	0	19	0	8	41	1049	125	58	9	43	87	0	0	73	2	16	2	2	1037	0	1000	16	29	0	1000	1000	1041	1041	1041	1041	1041
1004	1040	7	0	0	0	0	75	12	0	0	0	3	0	1025	16	5	12	19	26	25	2000	1000	1000	1000	1000	50722	45816	0	1015	1040	1040	824	3	898	2000	1000	1000	1040	1040	1	1	1001	1000	1000	0	1021	6	103	1047	19	0	29	0	6	25	1046	125	44	5	47	52	0	0	73	2	16	2	2	1037	0	1000	29	39	0	1000	1000	1041	1041	1041	1041	1041
1004	1040	8	0	0	0	0	91	25	1	0	0	3	0	1025	32	3	4	11	30	25	2000	1000	1000	1000	1000	50722	45823	0	1015	1040	1040	824	3	898	2000	1000	1000	1040	1040	1	1	1001	1000	1000	0	1023	2	75	1054	9	1	23	0	10	35	1083	125	41	8	31	81	0	0	73	2	16	2	2	1037	0	1000	40	21	0	1000	1000	1041	1041	1041	1041	1041
1004	1040	7	0	0	0	0	87	27	1	0	0	4	24	1025	22	4	5	5	23	25	2000	1000	1000	1000	1000	50746	45824	1	1015	1040	1040	824	3	898	2000	1000	1000	1040	1040	1	1	1001	1000	1000	0	1019	0	58	1036	6	0	19	0	8	37	1042	125	47	7	30	69	0	0	73	2	16	2	2	1037	0	1000	44	34	0	1000	1000	1041	1041	1041	1041	1041
1004	1040	8	0	0	0	0	92	0	0	0	0	2	0	1025	23	4	6	1	21	25	2000	1000	1000	1000	1000	50754	45823	0	1015	1040	1040	824	3	897	2000	1000	1000	1040	1040	1	1	1001	1000	1000	0	1028	3	57	1053	6	1	23	0	14	36	1054	125	43	5	31	59	0	0	73	2	16	2	2	1037	1	1000	43	30	0	1000	1000	1041	1041	1041	1041	1041
1004	1040	7	0	0	0	0	93	0	0	0	0	4	0	1025	37	2	6	7	26	25	2000	1000	1000	1000	1000	50714	45823	0	1015	1040	1040	824	3	897	2000	1000	1000	1040	1040	1	1	1001	1000	1000	0	1031	0	76	1056	7	0	36	0	16	41	1053	125	42	6	24	52	0	0	73	2	16	2	2	1037	0	1000	37	30	0	1000	1000	1041	1041	1041	1041	1041
1004	1040	7	0	0	0	0	77	0	0	0	0	4	0	1025	24	6	8	6	21	25	2000	1000	1000	1000	1000	50674	45815	1	1015	1040	1040	824	3	898	2000	1000	1000	1040	1040	1	1	1001	1000	1000	0	1000	0	70	1027	0	0	0	0	0	32	1032	125	47	8	37	69	0	0	73	2	16	2	2	1037	1	1000	48	39	0	1000	1000	1041	1041	1041	1041	1041
1004	1040	8	0	0	0	0	76	19	1	0	0	3	4	1025	18	6	11	7	19	25	2000	1000	1000	1000	1000	50730	45824	0	1015	1040	1040	824	3	898	2000	1000	1000	1040	1040	1	1	1001	1000	1000	0	1020	0	99	1038	0	0	0	0	0	43	1084	125	57	8	31	69	0	0	73	2	17	2	2	1037	0	1000	26	23	0	1000	1000	1041	1041	1041	1041	1041

Test 2: Latency 1->2 roundtrip

Chain cycles: 3

Code:

  ldr q0, [x6], #8
  fmov x0, d0
  eor x8, x8, x0
  eor x8, x8, x0
  add x6, x6, x8

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 10.0801

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	09	0e	0f	18	1e	1f	20	22	24	3a	3f	40	43	46	49	4d	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	69	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	af	ldst x64 uop (b1)	ldst xpg uop (b2)	b5	bb	be	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c3	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
50209	134349	999	0	0	1	0	214	0	7	1	0	542	130656	10	58	0	8	129565	25	71891	51304	10600	10000	40100	10000	10000	1157361	4935505	5012279	0	129955	0	129557	130069	123699	3	124608	60100	30200	10000	10000	60200	10000	10000	129330	129617	1	1	50201	100	99	100	40100	10000	10000	0	100	10015	0	548	10071	13	6	69	10074	1250	4	640	68	4	528	0	0	0	3210	1	76	1	1	128999	51120	5450	5660	5244	10000	50100	129653	129656	129687	129470	129380
50204	129125	986	0	0	0	0	195	0	7	1	0	549	130462	7	59	0	16	129584	25	71924	51304	10595	10000	40100	10000	10000	1159494	4951753	4981377	0	129580	0	130136	130960	123966	3	123442	60100	30200	10000	10000	60200	10000	10000	129859	129603	1	1	50201	100	99	100	40100	10000	10000	0	100	10015	0	542	10074	33	7	83	10078	1250	4	494	67	4	502	0	0	0	3210	1	76	1	1	129391	51212	5887	6145	5487	10000	50100	129561	129745	129828	130171	130005
50204	129906	989	0	0	0	0	206	0	7	1	0	574	129779	7	58	0	12	130099	25	71906	51322	10619	10000	40100	10000	10000	1153522	4899631	4936246	1	129189	0	129243	129755	122992	3	123340	60100	30200	10000	10000	60200	10000	10000	129834	129457	1	1	50201	100	99	100	40100	10000	10000	0	100	10014	0	545	10073	29	6	70	10074	1250	4	530	68	4	531	0	0	0	3210	1	76	1	1	130095	51182	5974	5981	5283	10000	50100	129809	129281	129649	130273	130144
50204	129547	987	0	0	0	0	198	0	9	1	0	508	129814	11	55	0	15	129502	25	71897	51471	10701	10056	44235	11114	11135	1218814	4984465	5043134	1	131671	0	130919	132074	124294	227	125689	66514	33762	11177	11237	67404	11218	11196	132632	132345	31	1	50201	100	99	100	40100	10000	10000	0	100	10047	2	577	10109	16	9	6097	10074	1250	4	536	65	4	566	0	0	0	3874	1	294	1	3	131423	51495	5932	6269	5662	10000	50100	132760	131956	133297	132669	132551
50204	132993	1006	0	0	0	1	3394	4132	7	1	0	568	129555	12	60	0	16	129460	47	72014	51388	10616	10000	40100	10000	10000	1158027	4897163	4999258	0	130295	0	129673	123363	123741	3	123571	60100	30200	10000	10000	60486	10000	10000	129320	128980	2	1	50201	100	99	100	40100	10000	10000	0	100	10017	0	524	10023	17	7	300	10024	1250	4	535	15	4	531	0	0	0	3210	1	76	1	1	128964	51104	6043	5961	5214	10000	50100	129300	129229	129057	129085	128787
50204	130976	972	0	0	0	0	167	0	7	0	1	553	129936	10	10	0	9	129066	25	71717	51350	10633	10004	40100	10082	10000	1151272	4882465	4944157	1	129070	0	129694	129492	122907	3	122817	60100	30200	10000	10000	60450	10080	10082	129556	129252	1	1	50201	100	99	100	40100	10000	10000	0	100	10014	0	522	10022	20	7	295	10022	1250	4	534	16	4	486	0	0	0	3210	1	76	1	1	128994	50992	5222	5542	5113	10000	50100	128876	128792	128722	128661	128643
50204	130552	967	0	0	0	0	177	176	9	0	1	547	129515	7	8	0	6	129218	25	71795	51228	10587	10000	40100	10000	10000	1148154	4878498	4939162	0	128774	0	129482	129402	122482	3	123091	60100	30200	10000	10000	60200	10000	10000	129185	129049	1	1	50201	100	99	100	40100	10000	10000	0	100	10017	0	573	10030	16	9	103	10027	1250	4	518	18	4	512	0	0	0	3210	1	76	1	1	128908	51040	5657	5526	4905	10000	50100	128761	129132	128773	128678	128840
50204	131028	971	0	1	1	0	151	0	7	0	1	521	129445	11	9	1	6	128453	25	71813	51158	10520	10000	40100	10000	10000	1142453	4887542	4932721	1	129822	0	129653	129157	123284	3	122862	60100	30200	10000	10000	60200	10000	10000	129060	128729	1	1	50201	100	99	100	40100	10000	10000	0	100	10016	0	516	10026	12	7	284	10027	1250	4	517	17	4	521	0	0	0	3210	1	76	1	1	128763	50986	5547	5750	5047	10000	50100	129199	128541	129018	130055	129108
50204	131669	970	0	1	0	0	165	0	7	0	1	530	129297	10	8	0	5	128820	25	71804	51254	10543	10000	40100	10000	10000	1141929	4894553	4951974	1	129989	0	129966	129399	122710	3	122403	60100	30200	10000	10000	60200	10000	10000	129056	128445	1	1	50201	100	99	100	40100	10000	10000	0	100	10017	0	542	10029	10	9	188	10026	1250	4	473	16	4	536	1	0	0	3210	1	76	1	1	129252	51038	6102	5648	5114	10000	50100	129061	129923	129190	129098	129132
50204	130953	968	0	1	1	0	175	0	12	0	1	506	129267	6	7	0	6	128818	25	71618	51180	10602	10000	40100	10000	10000	1150678	4901320	4950645	1	128848	0	130043	129861	122460	3	123555	60100	30200	10000	10000	60200	10000	10000	129110	128612	1	1	50201	100	99	100	40100	10000	10000	0	100	10015	0	551	10029	16	9	47	10026	1250	4	511	16	4	570	0	0	0	3210	1	76	1	1	129320	51044	5689	5875	5644	10000	50100	128561	128280	128958	128894	128928

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 9.9254

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	09	l2 tlb miss data (0b)	0e	0f	18	19	1e	1f	20	22	24	3a	3f	40	43	49	4d	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	69	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst ldst (9b)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	af	ldst x64 uop (b1)	ldst xpg uop (b2)	b5	bb	be	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	c3	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
50029	133181	974	1	0	0	0	0	0	0	0	145	0	7	1	0	522	128963	7	4	4	128848	25	71573	51080	10543	10000	40010	10000	10000	1154564	4911809	4967011	1	129838	0	128897	129175	122519	3	122805	60010	30020	10000	10000	60020	10000	10000	128571	128983	1	1	50021	10	9	10	40010	10000	10000	10	10017	0	550	10021	18	10	18	10021	1250	4	634	13	4	525	0	0	0	0	3140	4	82	3	3	128675	51132	6319	5962	5653	10000	50010	129318	129236	129566	129592	129029
50024	129833	971	0	0	0	0	0	0	0	0	145	0	10	1	0	492	129371	10	1	4	128844	25	71681	51098	10561	10000	40010	10000	10000	1146774	4882641	4950762	1	129476	0	129361	129569	122356	3	123338	60010	30020	10000	10000	60020	10000	10049	130185	129407	1	1	50021	10	9	10	40010	10000	10000	10	10015	0	563	10018	17	7	15	10021	1250	4	512	12	4	556	0	0	0	0	3140	3	82	3	3	129190	51070	5884	5991	5340	10000	50010	129246	129556	129430	129065	129509
50024	129133	962	0	0	0	0	0	0	0	0	139	0	9	1	0	505	129221	10	4	2	130259	25	71591	51130	10508	10000	40010	10000	10000	1146064	4911243	4953936	1	129342	0	129410	128927	122325	3	123111	60010	30020	10000	10000	60020	10000	10000	129327	128979	1	1	50021	10	9	10	40010	10000	10000	10	10017	0	537	10019	15	7	18	10019	1250	4	519	13	4	513	0	0	0	0	3140	3	82	2	3	128654	51064	5698	6409	5737	10000	50010	130818	129944	129008	129104	130079
50024	128068	968	1	0	0	1	0	0	0	0	217	0	9	1	0	514	129331	7	1	3	129897	25	71774	51058	10568	10000	40010	10000	10000	1151926	4931540	4968316	0	128889	0	129134	129667	122670	3	122435	60010	30020	10000	10000	60020	10000	10000	129155	129683	1	1	50021	10	9	10	40010	10000	10000	10	10021	2	567	10020	12	9	19	10018	1250	4	532	12	4	504	0	0	0	0	3140	2	82	3	3	128620	51016	6096	5980	5335	10000	50010	128844	129463	129063	128962	131068
50024	128924	967	0	0	0	0	0	0	0	0	157	0	7	1	0	541	128261	7	4	2	129084	25	71648	51062	10516	10000	40010	10000	10000	1150999	4911395	4983988	0	129626	0	129271	128978	122395	3	122258	60010	30020	10000	10000	60020	10000	10000	128916	128890	1	1	50021	10	9	10	40010	10000	10000	10	10014	0	526	10021	15	6	17	10018	1250	4	533	11	4	573	0	0	0	0	3140	3	82	2	4	129307	51138	5882	5635	6172	10000	50010	128469	128632	128887	128538	129389
50024	129148	966	0	0	0	0	0	0	0	0	181	0	6	1	0	525	129191	10	4	3	128743	25	71561	51058	10539	10000	40010	10000	10000	1146405	4880600	4941735	1	129641	0	128934	129229	122183	3	122853	60010	30020	10000	10000	60020	10000	10000	129039	129124	1	1	50021	10	9	10	40010	10000	10000	10	10017	0	576	10021	15	7	23	10020	1250	4	529	12	4	570	1	1	0	0	3140	3	82	3	4	128618	51096	5846	6360	5856	10000	50010	129165	129257	131115	129448	128716
50024	128358	963	0	0	0	0	0	0	0	0	163	0	11	1	0	519	129342	9	3	4	128894	25	71483	51006	10499	10000	40010	10000	10000	1143804	4868821	4951350	1	129694	0	128853	128944	122313	3	122557	60010	30020	10000	10000	60020	10000	10000	128535	129322	1	1	50021	10	9	10	40010	10000	10000	10	10017	0	571	10018	16	9	25	10018	1250	4	521	10	4	548	0	0	0	0	3140	3	82	3	3	128933	51154	5601	6129	5522	10000	50010	128332	128805	129077	129105	129763
50024	128728	972	0	0	0	0	0	0	0	0	171	0	7	1	0	513	129171	12	4	2	129037	25	71645	51106	10542	10000	40010	10000	10000	1144434	4903390	4938621	1	129466	0	128744	129443	122250	3	123059	60010	30020	10000	10000	60020	10000	10000	129630	129279	1	1	50021	10	9	10	40010	10000	10000	10	10020	1	563	10020	17	8	21	10021	1250	4	576	11	4	560	0	0	0	0	3140	3	82	3	3	129653	51116	5721	5831	5181	10000	50010	128687	129092	129192	129650	128979
50024	129690	965	1	1	1	0	0	0	0	0	161	0	11	1	0	557	128945	10	4	4	129030	25	71606	51094	10533	10000	40010	10000	10000	1158635	4987545	4961117	1	129420	0	129343	130157	122486	3	122543	60010	30020	10000	10000	60020	10000	10000	129607	129330	1	1	50021	10	9	10	40010	10000	10000	10	10019	1	514	10026	16	7	22	10020	1250	4	517	11	4	526	1	1	0	0	3140	3	82	3	2	128643	51088	5806	5775	5288	10000	50010	129627	129140	129343	128841	129850
50024	128625	961	1	1	1	0	0	0	0	0	141	0	7	1	0	482	129075	7	4	3	128460	25	71579	51066	10542	10000	40010	10000	10000	1142625	4877998	4933448	1	129398	0	129497	129124	122932	3	122955	60010	30020	10000	10000	60020	10000	10000	129321	129111	1	1	50021	10	9	10	40010	10000	10000	10	10017	0	516	10019	23	11	18	10021	1250	4	563	11	4	509	0	0	141	0	3140	3	125	3	2	128744	51080	5939	6298	5353	10000	50010	129625	130422	129216	129679	129203

Test 3: throughput

Count: 8

Code:

  ldr q0, [x6], #8
  ldr q0, [x7], #8
  ldr q0, [x8], #8
  ldr q0, [x9], #8
  ldr q0, [x10], #8
  ldr q0, [x11], #8
  ldr q0, [x12], #8
  ldr q0, [x13], #8

Initialization

  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.3790

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	09	l2 tlb miss data (0b)	0e	18	19	1e	1f	20	22	29	3a	3e	3f	40	43	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	67	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	92	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	l1d cache miss ld (a3)	a5	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ab	ac	af	ldst x64 uop (b1)	ldst xpg uop (b2)	b5	b6	bb	be	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	c3	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	e7	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
80209	30831	228	1	0	0	1	0	0	0	7637	0	852	1	624	416	308	30361	802	571	1380	1681	2958	25	160132	80147	80000	80100	80000	400741	1341381	1	39	30270	30433	30294	20125	3	20392	160100	200	80000	200	80000	30355	30213	1	1	80201	100	99	47	100	100	80000	80000	0	100	81003	36	385	5566	606	86315	786	15	872	68	5429	85936	10000	32	642	132	5556	32	5656	16	0	4	5110	1	17	1	1	30426	179	80044	406	409	74	80000	80100	30185	30022	30099	30348	30203
80204	30210	225	1	0	0	0	0	0	0	7542	0	774	1	568	448	408	30271	776	541	1477	1263	2923	25	160145	80130	80000	80100	80000	400771	1349065	1	43	30046	30359	30486	20249	3	20236	160100	200	80000	200	80000	30361	30260	1	1	80201	100	99	55	100	100	80000	80000	0	100	81002	35	408	5643	631	85815	788	9	892	76	5973	87003	10000	32	660	125	6142	32	4705	34	0	3	5110	1	17	1	1	30409	153	80041	324	369	75	80000	80100	29956	30309	30465	30353	30273
80204	30507	226	2	2	0	2	0	0	0	7854	0	804	1	552	419	100	30289	799	543	1526	1446	2993	25	160141	80131	80000	80100	80000	400759	1327947	1	46	30101	30453	30414	20147	3	20173	160100	200	80000	200	80000	30361	30166	1	1	80201	100	99	38	100	100	80000	80000	0	100	80985	35	425	5528	614	86219	760	8	898	80	5880	86822	10000	32	606	113	5852	32	4994	33	0	3	5110	1	16	1	1	30112	161	80038	360	402	85	80000	80100	30412	30308	30340	30522	30196
80204	30244	224	1	0	0	1	0	0	0	7141	0	812	1	568	392	160	30130	821	539	1225	1349	2816	25	160150	80137	80000	80100	80000	400808	1327789	1	38	30255	30232	30266	20171	3	20306	160100	200	80000	200	80000	30361	30486	1	1	80201	100	99	46	100	100	80000	80000	0	100	81040	41	413	5580	604	85926	703	7	948	64	5874	86703	10000	32	650	125	5734	32	4884	37	2	3	5110	1	17	1	1	30429	182	80046	343	401	85	80000	80100	30495	30416	30078	30356	30150
80204	30319	227	1	1	0	1	0	0	0	7247	0	784	1	448	434	200	30020	759	548	1393	1431	2994	25	160140	80142	80000	80100	80000	400732	1330854	1	49	30327	30503	30490	20323	3	20071	160100	200	80000	200	80000	30207	30305	1	1	80201	100	99	54	100	100	80000	80000	0	100	80987	36	396	5019	621	86171	738	11	871	36	5765	86575	10000	32	632	132	5734	32	5132	37	1	5	5110	1	16	1	1	30523	164	80037	380	400	96	80000	80100	30254	30402	30546	30037	30698
80204	30252	226	2	0	2	0	0	0	0	7507	0	863	1	608	426	236	30151	785	648	1534	1827	3049	25	160146	80140	80000	80100	80000	400745	1327970	1	43	30284	30134	30376	20469	3	20214	160100	200	80000	200	80000	30421	30337	1	1	80201	100	99	34	100	100	80000	80000	0	100	81180	36	431	5342	671	86006	738	9	870	54	5762	86223	10000	32	712	112	5722	32	4827	15	0	2	5110	1	17	1	1	30245	152	80055	372	428	74	80000	80100	30174	30179	30318	30241	30378
80204	30340	227	3	3	0	0	0	0	0	7752	0	846	1	632	436	200	30409	778	541	1592	1540	2959	25	160156	80143	80000	80100	80000	400713	1344572	1	38	30325	30470	30217	20393	3	20220	160100	200	80000	200	80000	30092	30256	1	1	80201	100	99	37	100	100	80000	80000	0	100	80948	17	423	5529	605	85710	759	11	872	34	5809	86298	10000	32	618	120	5704	32	5082	18	1	3	5110	1	17	1	1	30228	180	80036	391	312	73	80000	80100	30396	30075	30580	30166	30353
80204	30427	227	1	1	0	0	0	0	0	7089	0	823	1	568	438	240	30407	769	607	1608	1375	2826	25	160135	80130	80000	80100	80000	400825	1326148	1	40	30296	30123	30326	20321	3	20148	160100	200	80000	200	80000	30309	30463	1	1	80201	100	99	44	100	100	80000	80000	0	100	81009	36	420	5342	605	86313	756	10	888	40	6135	86411	10000	32	555	127	5836	32	5467	35	3	6	5110	1	17	1	1	30212	181	80062	444	394	79	80000	80100	30088	29923	30178	30373	30550
80204	30294	226	1	0	0	0	0	0	0	6896	0	785	1	560	463	104	30166	807	605	1699	1466	3028	25	160145	80136	80000	80100	80000	400767	1341265	1	40	30320	30271	30265	20273	3	20607	160100	200	80000	200	80000	30387	30273	1	1	80201	100	99	50	100	100	80000	80000	0	100	80958	35	417	5038	627	85631	742	7	900	42	6398	86328	10000	32	597	127	5741	32	4952	31	0	1	5110	1	17	1	1	30392	189	80044	285	367	79	80000	80100	30148	30328	30117	30226	30198
80204	30108	227	2	0	0	0	0	2	0	7855	0	836	1	640	437	212	30683	770	607	1442	1495	2944	25	160135	80142	80000	80100	80000	400745	1351006	0	43	30436	30214	30289	20248	3	20384	160100	200	80000	200	80000	30087	30199	1	1	80201	100	99	43	100	100	80000	80000	0	100	80965	17	405	5073	583	85689	730	13	866	30	5293	86465	10000	32	631	126	6031	32	5327	17	0	9	5110	1	17	1	1	30480	165	80045	324	431	82	80000	80100	30438	30258	30122	30333	30248

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.3765

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l2 tlb miss data (0b)	0f	19	1e	20	22	29	3a	3e	3f	40	43	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	67	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	92	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d cache miss st (a2)	l1d cache miss ld (a3)	a5	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ab	ac	af	ldst x64 uop (b1)	ldst xpg uop (b2)	b5	b6	bb	be	l1d cache miss ld nonspec (bf)	c2	c3	cf	d0	d5	map dispatch bubble (d6)	da	dd	fetch restart (de)	e0	e7	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
80029	31009	228	0	0	0	7023	799	1	592	418	96	30077	827	474	1813	1713	2820	25	160051	80054	80000	80010	80000	400248	1328874	0	44	30163	30276	30160	20381	3	20419	160010	20	80000	20	80000	30054	30315	1	1	80021	10	9	30	10	10	80000	80000	0	10	80933	460	4899	643	85770	856	14	930	24	5277	86290	10000	32	598	123	4685	32	4912	0	9	5020	15	3	16	0	3	2	30032	169	80042	295	292	52	80000	80010	30248	30230	30126	30119	30359
80024	29994	226	0	0	0	7743	791	1	624	461	168	29961	766	511	1656	1541	2923	25	160052	80054	80000	80010	80000	400270	1337487	1	41	29928	29976	29941	20072	3	20207	160010	20	80000	20	80000	30234	30185	1	1	80021	10	9	3	10	10	80000	80000	0	10	80969	472	5197	621	85728	833	15	851	46	5374	86243	10000	32	605	131	5020	32	5355	3	5	5020	0	3	16	0	3	3	30087	149	80043	304	258	64	80000	80010	29950	30399	30372	30158	30135
80024	29982	226	0	0	0	7172	842	1	760	470	212	30134	784	514	1722	1490	2900	25	160048	80054	80000	80010	80000	400259	1343881	0	46	29839	30032	30202	20061	3	20191	160010	20	80000	20	80000	30125	29833	1	1	80021	10	9	7	10	10	80000	80000	0	10	80934	442	5066	644	85212	807	11	889	42	5532	86113	10000	32	561	117	4729	32	5492	3	6	5020	0	3	16	1	3	4	30260	168	80044	326	303	69	80000	80010	29965	29986	30211	30135	30156
80024	30334	225	0	0	0	7722	850	1	280	455	268	30276	831	456	1674	1762	2824	25	160039	80051	80000	80010	80000	400299	1326969	0	41	30178	30257	30093	20148	3	20419	160010	20	80000	20	80000	30274	30213	1	1	80021	10	9	16	10	10	80000	80000	0	10	80968	468	5065	629	85063	902	14	932	50	5552	86290	10000	32	562	128	5571	32	4691	0	3	5020	0	3	16	0	3	3	30132	152	80062	336	328	76	80000	80010	30149	30268	30033	30216	30226
80024	30032	225	0	0	0	7788	843	1	752	359	368	29816	758	442	1869	1813	3002	25	160049	80050	80000	80010	80000	400252	1342680	0	40	29894	29838	30087	20332	3	20413	160372	20	80000	20	80000	30232	30390	1	1	80021	10	9	34	10	10	80000	80000	0	10	80988	482	5587	653	84927	892	15	935	132	5700	86405	10000	32	571	121	4854	32	4918	0	4	5031	3	3	16	0	3	3	29898	155	80039	296	273	70	80000	80010	30074	30345	30233	30116	30101
80024	29971	226	0	0	0	6778	823	1	752	455	244	30124	815	513	1817	1806	2610	25	160054	80055	80000	80010	80000	400225	1324737	0	38	30323	30545	30162	20071	3	20207	160010	20	80000	20	80000	30228	30171	1	1	80021	10	9	17	10	10	80000	80000	0	10	81012	460	4841	673	86402	805	11	957	40	5795	87008	10000	32	696	128	4820	32	4983	3	7	5020	0	3	16	0	3	3	30292	180	80032	287	333	51	80000	80010	30275	30113	30347	30324	30300
80024	29872	224	0	0	0	6668	770	1	624	394	548	30203	779	477	1852	2013	3017	25	160055	80056	80000	80010	80000	400369	1345279	0	34	30345	30332	30242	20282	3	20054	160010	20	80000	20	80000	30035	30136	1	1	80021	10	9	20	10	10	80000	80000	0	10	80948	436	5339	625	85172	847	11	878	50	5915	86244	10000	32	613	115	5064	32	4232	0	3	5020	0	3	16	0	3	3	30172	146	80033	283	272	57	80000	80010	29968	30075	30241	30261	30421
80024	30094	225	0	0	0	6665	793	1	736	502	128	30274	820	523	1673	1762	2656	25	160051	80048	80000	80010	80000	400253	1323298	0	45	30214	30247	30217	20415	3	20314	160010	20	80000	20	80000	30003	30217	1	1	80021	10	9	15	10	10	80000	80000	0	10	80934	452	5362	615	85215	827	9	898	70	5808	86176	10000	32	642	122	5280	32	4686	6	5	5020	0	3	16	0	3	3	30112	160	80045	311	337	61	80000	80010	30397	30385	30299	30274	30162
80024	30226	226	0	0	0	8004	820	1	416	371	208	29728	799	537	1563	1753	3039	25	160048	80048	80000	80010	80000	400272	1326819	0	44	30167	30150	30055	20221	3	19894	160010	20	80000	20	80000	30344	30296	1	1	80021	10	9	2	10	10	80000	80000	0	10	80984	487	5480	630	85872	851	13	924	88	6013	86447	10000	32	578	120	5439	32	4582	6	0	5020	0	3	16	0	3	3	30050	169	80043	353	331	58	80000	80010	30129	30022	30174	30037	30276
80024	30142	225	0	0	0	7330	826	1	752	399	200	30237	774	602	2016	1879	2985	25	160049	80066	80000	80010	80000	400258	1337646	0	36	30161	30131	30045	20115	3	20167	160010	20	80000	20	80000	30228	30206	1	1	80021	10	9	7	10	10	80000	80000	0	10	80990	438	5416	623	85481	832	13	886	44	5434	86625	10000	32	562	127	5461	32	5221	0	2	5020	3	3	16	0	3	3	30075	175	80044	307	305	57	80000	80010	30207	30104	30316	30089	30105

LDR (post-index, Q)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->2 roundtrip

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations