Firestorm: LDR (post-index, S) measurements

Code:

  ldr s0, [x6], #8

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 2.000

Integer unit issues: 1.000

Load/store unit issues: 1.000

SIMD/FP unit issues: 0.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	l2 tlb miss data (0b)	0e	0f	1e	20	22	3a	3e	3f	40	43	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map ldst uop (7d)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst simd load (98)	inst ldst (9b)	9d	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	l1d cache miss ld (a3)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	aa	ab	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	c2	c3	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
1005	1040	8	0	1	0	0	56	12	1	1	0	1025	11	1	6	7	14	25	2000	1000	1000	1000	1000	50746	45824	1	1015	1040	1040	824	3	898	2000	1000	1000	1040	1040	1	1	1001	1000	1000	0	1016	0	0	62	1026	0	0	13	0	8	31	1023	40	6	28	48	0	0	73	2	16	1	1	1037	1000	27	27	1000	1000	1041	1044	1041	1041	1041
1004	1040	7	0	0	0	0	51	20	0	3	0	1025	0	1	4	7	15	25	2000	1000	1000	1000	1000	50762	45824	1	1015	1040	1040	824	3	898	2000	1000	1000	1040	1040	1	1	1001	1000	1000	0	1000	0	0	37	1025	0	0	0	0	0	60	1041	22	4	24	48	0	0	73	1	16	1	1	1037	1000	27	28	1000	1000	1041	1041	1041	1041	1041
1004	1043	8	0	0	0	0	43	13	0	1	0	1025	7	1	3	5	16	25	2000	1000	1000	1000	1000	50762	45824	1	1015	1040	1040	824	3	898	2000	1000	1000	1040	1040	1	1	1001	1000	1000	0	1020	12	0	46	1029	2	0	16	0	18	29	1037	27	5	16	32	0	0	73	1	16	1	1	1037	1000	28	23	1000	1000	1041	1041	1041	1041	1041
1004	1040	8	1	0	0	0	44	20	0	1	0	1025	7	1	5	1	21	25	2000	1000	1000	1000	1000	50770	45824	1	1015	1040	1040	824	3	898	2000	1000	1000	1040	1040	1	1	1001	1000	1000	0	1007	0	0	37	1035	0	0	0	0	12	25	1039	21	3	18	32	0	0	73	1	16	1	1	1037	1000	27	34	1000	1000	1041	1041	1041	1041	1041
1004	1045	8	0	1	0	0	56	10	0	4	0	1025	17	1	1	2	11	25	2000	1000	1000	1000	1000	50778	45824	1	1015	1040	1040	824	3	898	2000	1000	1000	1040	1040	1	1	1001	1000	1000	0	1019	0	0	69	1031	2	2	15	0	0	22	1031	29	2	20	56	0	0	73	1	16	1	1	1037	1000	30	32	1000	1000	1041	1041	1041	1041	1041
1004	1055	8	0	0	0	0	79	0	0	1	0	1043	0	1	1	1	22	25	2000	1000	1000	1000	1000	50746	45824	1	1015	1040	1040	824	3	897	2000	1000	1000	1040	1040	1	1	1001	1000	1000	0	1000	0	0	61	1034	0	0	0	0	0	27	1023	36	6	16	64	0	0	73	1	17	1	1	1037	1000	35	35	1000	1000	1041	1041	1041	1041	1041
1004	1051	8	0	0	0	0	61	0	0	1	0	1025	7	1	4	4	18	25	2000	1000	1000	1000	1000	50706	45822	1	1016	1040	1040	824	3	898	2000	1000	1000	1040	1040	1	1	1001	1000	1000	0	1000	0	0	42	1028	0	0	0	0	0	35	1027	28	5	25	24	0	9	73	1	16	1	1	1037	1000	20	30	1000	1000	1041	1041	1041	1041	1041
1004	1040	8	0	0	0	0	63	12	1	5	0	1025	0	2	4	4	15	25	2000	1000	1000	1000	1000	50746	45828	1	1015	1040	1040	824	3	898	2000	1000	1000	1040	1040	1	1	1001	1000	1000	0	1000	0	2	67	1034	13	2	0	32	12	38	1035	28	6	22	56	0	0	73	1	16	1	1	1037	1000	20	42	1000	1000	1041	1041	1041	1041	1041
1004	1040	7	0	0	0	0	65	24	1	1	0	1025	7	2	7	4	19	25	2000	1000	1000	1000	1000	50762	45824	1	1015	1040	1040	824	3	898	2000	1000	1000	1040	1040	1	1	1001	1000	1000	0	1034	0	0	45	1026	4	0	12	0	22	24	1045	21	6	21	32	0	0	73	1	16	1	1	1037	1000	27	35	1000	1000	1041	1041	1041	1041	1041
1004	1044	7	0	0	0	0	55	13	0	1	20	1025	0	1	3	1	11	25	2000	1000	1000	1000	1000	50698	45824	1	1015	1040	1040	824	3	898	2000	1000	1000	1040	1040	1	1	1001	1000	1000	0	1000	0	0	58	1020	0	1	46	0	14	46	1043	55	7	17	40	0	23	73	1	16	1	1	1037	1000	25	33	1000	1000	1041	1041	1041	1041	1057

Test 2: Latency 1->2 roundtrip

Chain cycles: 3

Code:

  ldr s0, [x6], #8
  fmov x0, d0
  eor x8, x8, x0
  eor x8, x8, x0
  add x6, x6, x8

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 9.1914

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	09	l2 tlb miss data (0b)	0e	0f	18	19	1e	1f	20	22	23	24	29	3a	3e	3f	40	43	49	4d	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	l1d cache miss ld (a3)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ab	ac	af	b5	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	c3	branch mispred nonspec (cb)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
50209	122018	913	1	0	0	0	1	0	0	0	596	0	839	1	0	0	792	0	148	121756	792	3	7	121455	25	70496	50358	10127	10000	40100	10000	10000	1083586	4604050	4646791	1	121913	121733	121766	115201	3	115557	60100	30200	10000	10000	61194	10000	10168	121733	121764	2	1	50201	100	99	100	40100	10000	10000	0	100	10915	1	117	528	10711	208	13	954	86	45	10961	139	3	134	1	0	12	0	3210	1	76	1	1	121503	50340	1004	916	856	10000	50100	121783	121656	121762	121644	122255
50204	121680	912	1	0	0	0	0	1	0	0	576	176	826	1	0	0	752	2	108	121707	809	2	1	121395	25	70543	50388	10135	10002	40100	10000	10000	1077714	4606574	4653825	1	122178	121744	121834	115073	3	115426	60100	30200	10000	10000	60200	10000	10000	121898	121849	1	1	50201	100	99	100	40100	10000	10000	0	100	10896	2	128	552	10717	218	10	930	84	34	10947	132	11	121	2	0	4	0	3210	1	76	1	1	121738	50290	858	932	794	10000	50100	121705	121783	121553	121689	121630
50204	121782	914	1	0	0	0	0	0	0	0	506	0	852	1	0	0	736	1	116	121803	811	1	2	121433	25	70505	50336	10144	10000	40100	10000	10000	1076742	4605004	4656036	1	121729	121775	121769	115131	3	115369	60100	30200	10000	10000	60200	10000	10000	121728	121602	1	1	50201	100	99	100	40100	10000	10000	0	100	10933	1	116	551	10717	206	11	944	84	33	10912	125	3	119	1	0	3	0	3210	1	17	1	1	121594	50262	914	866	829	10000	50100	121786	121813	121639	121879	121840
50204	121788	911	2	1	0	0	0	0	0	0	531	0	860	1	0	0	752	2	168	121816	820	2	2	121473	25	70508	50370	10128	10000	40100	10000	10000	1077180	4605653	4655278	1	121805	122051	121953	114973	3	115381	60100	30200	10000	10000	60200	10000	10000	121873	121727	1	1	50201	100	99	100	40100	10000	10000	0	100	10934	3	115	532	10730	209	10	927	82	41	10976	126	4	136	2	0	3	1	3210	1	76	1	1	121496	50281	942	918	724	10000	50100	121852	122160	121603	121745	121696
50204	122024	913	1	0	0	0	0	0	0	0	546	0	829	1	0	0	552	1	108	121653	810	3	2	121376	25	70478	50368	10123	10000	40100	10000	10000	1076517	4597875	4650869	1	121712	121686	121582	114915	3	115290	60100	30200	10000	10000	60200	10000	10000	121673	121792	1	1	50201	100	99	100	40100	10000	10000	1	100	10956	3	115	522	10736	220	13	924	68	30	10905	133	4	118	1	0	7	0	3210	1	76	1	1	121484	50252	962	1056	965	10000	50100	121906	121810	121809	121970	121625
50204	121878	913	2	0	0	0	0	0	0	0	546	0	842	1	0	0	736	1	108	121929	829	3	3	121354	25	70478	50350	10130	10000	40100	10000	10000	1086161	4601550	4648183	1	121772	121860	121815	114889	3	115514	60100	30200	10000	10000	60200	10000	10000	121802	121783	1	1	50201	100	99	100	40100	10000	10000	0	100	10948	1	115	565	10707	209	9	946	32	27	10899	134	2	121	2	0	5	0	3210	1	76	1	1	121641	50238	904	856	773	10000	50100	121704	121790	121882	121757	121767
50204	121749	911	1	1	0	0	0	0	0	0	486	0	857	1	0	0	736	2	104	121760	811	4	1	121250	25	70490	50376	10142	10000	40100	10000	10000	1077030	4600060	4646341	1	121692	121824	121758	114940	3	115524	60100	30200	10000	10000	60200	10000	10000	121687	121727	1	1	50201	100	99	100	40100	10000	10000	0	100	10919	1	99	539	10730	216	19	941	86	132	10942	126	5	124	2	0	596	0	3210	1	76	1	1	121605	50258	922	998	787	10000	50100	121727	121839	121773	121793	121744
50204	121762	913	1	0	0	1	0	0	0	0	503	0	836	1	0	0	720	2	136	121865	802	1	3	121460	25	70484	50358	10140	10000	40100	10635	11024	1149001	4652015	4703168	1	123708	124160	124304	116131	211	116961	66095	33542	11139	11149	67128	11176	11154	124796	124337	30	1	50201	100	99	100	40100	10000	10000	0	100	10978	1	121	544	10781	219	11	906	46	84163	10937	124	2	122	1	3	3	0	3495	4	307	2	3	123513	50544	980	902	815	10000	50100	124041	124654	124892	124220	124999
50204	124420	935	0	0	0	0	0	0	33	31	602	0	817	1	0	0	568	1	100	124305	810	3	1	121435	25	70478	50364	10129	10000	40100	10000	10000	1077684	4604604	4650450	1	121927	121700	121634	114822	3	115369	60100	30200	10000	10000	60200	10000	10000	121636	121771	1	1	50201	100	99	100	40100	10000	10000	0	100	10900	4	115	529	10726	231	12	1240	74	43	10974	120	2	127	2	3	5	0	3210	1	76	1	2	121589	50264	1119	1164	922	10000	50100	121898	121936	121851	121987	121996
50204	121951	913	1	0	0	0	0	0	0	0	392	0	810	0	1	0	744	2	100	121929	840	2	2	121688	25	70514	50370	10131	10000	40100	10000	10000	1079147	4608233	4655576	1	121830	121856	121808	115217	3	115527	60100	30200	10000	10000	60200	10000	10000	122117	121974	1	1	50201	100	99	100	40100	10000	10000	0	100	10959	3	121	586	10739	203	13	982	72	16	10952	123	4	141	2	6	14	0	3210	1	76	1	1	121815	50262	1117	1040	907	10000	50100	121881	122026	121841	121978	122011

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 9.1893

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	09	l2 tlb miss data (0b)	0e	0f	18	1e	1f	20	22	29	3a	3e	3f	40	43	49	4d	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	69	6b	6d	6e	map stall dispatch (70)	int prf full (71)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	l1d cache miss ld (a3)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ab	ac	af	b5	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	c3	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cf	l1i cache miss demand (d3)	d5	map dispatch bubble (d6)	da	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
50029	122026	915	5	0	0	0	0	1	0	415	0	837	1	760	3	120	122050	763	4	1	121438	25	70379	50290	10121	10000	40010	10000	10000	1079824	4620685	4653114	0	121778	0	121700	121728	115160	0	3	115596	60010	30020	10000	10000	60020	10000	10000	121992	122058	1	1	50021	10	9	10	40010	10000	10000	0	10	10883	2	111	535	10696	199	11	879	44	30	10875	124	5	136	2	3	5	0	0	3140	0	9	82	0	5	7	121717	50260	1128	1073	1005	10000	50010	121832	121847	121836	121828	121778
50024	122054	913	2	1	0	0	0	0	0	393	0	808	1	712	2	252	121961	832	4	0	121698	25	70400	50272	10135	10000	40010	10000	10000	1078969	4602654	4661476	0	121782	0	121877	121930	115300	0	3	115583	60010	30020	10000	10000	60020	10000	10000	121987	121963	1	1	50021	10	9	10	40010	10000	10000	0	10	10880	12	98	535	10722	209	9	954	68	34	10904	117	8	131	4	3	3	0	1	3140	0	7	82	0	6	7	121674	50254	982	988	955	10000	50010	121980	121824	121772	121818	122019
50024	121828	914	4	4	0	0	0	0	0	451	0	804	1	784	4	108	121801	787	4	0	121695	25	70421	50262	10133	10000	40010	10000	10000	1078267	4608412	4660575	0	121829	0	121921	121803	115240	0	3	115512	60010	30020	10000	10000	60020	10000	10000	121741	121975	1	1	50021	10	9	10	40010	10000	10000	0	10	10908	8	116	529	10720	203	9	910	78	33	10931	123	8	122	4	4	3	0	0	3140	0	6	82	0	7	6	121629	50274	1150	1026	865	10000	50010	121808	121900	121758	121899	121933
50024	122057	914	3	0	0	0	0	0	0	480	0	805	1	720	3	120	121845	797	3	1	121340	25	70418	50272	10132	10000	40010	10000	10000	1078429	4600013	4659154	0	121896	0	121852	122103	115254	0	3	115426	60010	30020	10000	10000	60020	10000	10000	121918	121794	1	1	50021	10	9	10	40010	10000	10000	0	10	10932	3	109	533	10703	208	10	913	46	31	10959	117	7	128	3	0	9	0	0	3140	0	6	82	0	6	10	121687	50292	980	1114	929	10000	50010	121967	121685	122064	122086	121973
50024	122017	914	3	0	0	3	0	0	0	455	0	791	1	752	4	140	121877	807	5	1	121577	25	70412	50282	10143	10000	40010	10000	10000	1079140	4615918	4658089	0	121818	0	121756	121921	115218	0	3	115653	60010	30020	10000	10000	60020	10000	10000	121761	121840	1	1	50021	10	9	10	40010	10000	10000	0	10	10918	3	108	538	10708	209	15	978	50	37	10921	121	5	120	3	9	3	0	0	3140	0	10	82	0	10	10	121654	50244	972	995	876	10000	50010	121846	121900	121964	121868	121999
50024	122027	912	5	0	0	0	0	1	0	474	0	778	1	712	4	108	121735	808	5	0	121363	45	70436	50278	10139	10000	40010	10000	10000	1079428	4609476	4657552	0	122049	0	121939	121876	115323	0	3	115449	60010	30020	10000	10000	60020	10000	10000	121999	121936	1	1	50021	10	9	10	40010	10000	10000	0	10	10896	4	120	530	10735	212	7	914	48	29	10919	126	7	130	4	9	8	0	0	3140	0	6	82	0	9	7	121621	50282	1059	1133	981	10000	50010	121833	121835	121989	121795	122092
50024	121799	913	3	0	0	0	0	0	0	443	0	821	1	704	3	92	121912	785	5	0	121554	25	70388	50270	10124	10000	40010	10000	10000	1077259	4604969	4654888	0	121745	0	121808	121799	115009	0	3	115452	60010	30020	10000	10000	60020	10000	10000	122046	121865	1	1	50021	10	9	10	40010	10000	10000	0	10	10878	6	101	527	10691	194	13	899	64	31	10921	116	6	134	3	0	3	0	0	3140	0	8	82	0	8	9	121585	50246	1068	1098	958	10000	50010	121742	121887	121960	121938	122122
50024	121957	912	4	0	0	0	0	0	0	507	0	800	1	672	4	104	121910	777	5	0	121650	25	70418	50252	10133	10000	40010	10000	10000	1079239	4606699	4665775	0	121876	0	121810	121971	115540	0	3	115481	60010	30020	10000	10000	60020	10000	10000	121822	121884	1	1	50021	10	9	10	40010	10000	10000	0	10	10901	4	101	534	10712	193	11	914	72	30	10893	135	8	129	4	0	12	0	0	3140	0	7	82	0	7	6	121527	50250	1051	992	934	10000	50010	121872	121872	121815	121919	121800
50024	121921	912	4	0	0	4	0	0	0	422	0	830	1	720	3	136	121949	768	3	0	121691	25	70430	50300	10130	10000	40010	10000	10000	1077844	4605650	4658579	0	121787	0	121914	121652	115073	0	3	115400	60010	30020	10048	10000	60020	10000	10000	121932	121947	1	1	50021	10	9	10	40010	10000	10000	0	10	10875	4	111	522	10694	211	11	895	46	24	10922	121	7	123	3	3	11	0	0	3140	0	11	82	0	10	7	121693	50256	1014	1115	966	10000	50010	121693	121854	121861	122028	122061
50024	121853	913	3	0	0	0	0	0	0	464	0	822	1	712	3	100	121874	791	4	0	121568	25	70382	50284	10140	10000	40010	10000	10000	1078159	4608016	4660084	0	121719	0	121878	122119	115273	0	3	115570	60010	30020	10000	10000	60020	10000	10000	121812	121770	1	1	50021	10	9	10	40010	10000	10000	0	10	10879	3	115	525	10691	213	12	903	68	32	10876	123	7	114	3	0	3	0	0	3140	0	7	82	0	10	10	121546	50260	1074	1021	925	10000	50010	121907	122055	121707	122039	121948

Test 3: throughput

Count: 8

Code:

  ldr s0, [x6], #8
  ldr s0, [x7], #8
  ldr s0, [x8], #8
  ldr s0, [x9], #8
  ldr s0, [x10], #8
  ldr s0, [x11], #8
  ldr s0, [x12], #8
  ldr s0, [x13], #8

Initialization

  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.3683

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	l2 tlb miss data (0b)	0f	18	1e	20	22	29	3a	3e	3f	40	43	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	67	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	92	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	l1d cache miss ld (a3)	a5	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ab	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	c3	branch cond mispred nonspec (c5)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	e7	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
80209	30174	221	1	1	0	1	0	6917	776	1	760	115	116	29511	820	659	1923	1923	2221	25	160158	80152	80000	80100	80000	400849	1301368	1	46	29355	29572	29435	19066	3	19370	160100	200	80000	200	80000	29191	29426	1	1	80201	100	99	27	100	100	80000	80000	1	100	80889	17	349	5784	0	85439	661	16	872	42	5819	86350	803	133	5414	5192	17	0	3	0	5110	1	17	1	1	29352	25	80059	526	506	120	80000	80100	29444	29667	29429	29468	29474
80204	29477	221	1	0	0	0	0	7329	815	1	784	98	152	29569	792	683	1945	2028	2109	25	160149	80146	80000	80100	80000	400759	1301481	1	50	29646	29467	29602	19326	3	19350	160100	200	80000	200	80000	29474	29558	1	1	80201	100	99	46	100	100	80000	80000	1	100	80912	18	393	5902	0	85671	604	16	874	36	5424	86005	703	127	5054	5298	18	0	3	0	5110	1	17	1	1	29579	20	80046	583	590	118	80000	80100	29471	29506	29392	29375	29612
80204	29324	222	0	0	0	0	0	7255	768	1	712	98	144	29466	777	545	1864	1914	2077	25	160152	80156	80000	80100	80000	400841	1300236	1	54	29471	29301	29204	19127	3	19414	160100	200	80000	200	80000	29300	29351	1	1	80201	100	99	26	100	100	80000	80000	1	100	80896	0	392	5328	0	86203	696	18	877	86	5597	86128	716	116	5556	4603	0	0	10	0	5110	1	17	1	1	29515	24	80038	691	581	124	80000	80100	29831	29447	29510	29407	29448
80204	29406	220	0	0	0	0	0	6910	778	1	656	118	132	29400	772	560	2075	1966	2230	25	160137	80152	80000	80100	80000	400806	1295906	1	52	29728	29353	29246	19495	3	19377	160100	200	80000	200	80000	29461	29462	1	1	80201	100	99	18	100	100	80000	80000	1	100	80878	0	366	5359	0	85872	646	14	903	64	5420	86265	794	122	5600	5089	0	0	3	0	5110	1	17	1	1	29376	21	80052	506	457	96	80000	80100	29395	29478	29346	29273	29277
80204	29398	221	0	0	0	0	0	7087	796	1	680	99	100	29472	744	622	1884	1950	2176	25	160153	80155	80000	80100	80000	400750	1306662	1	61	29585	29545	29569	19348	3	19605	160100	200	80000	200	80000	29472	29254	1	1	80201	100	99	30	100	100	80000	80000	1	100	80880	0	387	5541	0	85368	655	14	850	30	4697	86438	750	137	5199	5273	0	9	3	0	5110	1	16	1	1	29471	17	80044	563	481	110	80000	80100	29580	29750	29591	29352	29662
80204	29501	222	0	0	0	1	0	7012	835	1	672	103	116	29291	779	735	1956	2143	2187	165	160140	80145	80000	80100	80000	400777	1289060	1	52	29240	29749	29559	19420	3	19465	160100	200	80000	200	80000	29496	29290	1	1	80201	100	99	21	100	100	80000	80000	1	100	80914	0	337	5701	0	85870	598	14	894	56	5610	86587	747	123	4846	4649	0	3	3	0	5110	1	16	1	1	29337	31	80049	548	606	132	80000	80100	29399	29595	29663	29597	29520
80204	29497	222	0	0	0	0	0	7668	846	1	712	93	112	29513	781	695	1892	1855	2050	25	160154	80141	80000	80100	80000	400809	1287518	1	43	29368	29331	29297	19158	3	19459	160100	200	80000	200	80000	29233	29339	1	1	80201	100	99	24	100	100	80000	80000	1	100	80856	0	389	5913	0	85623	653	15	912	30	5822	86486	769	126	5497	5086	0	0	6	0	5110	1	16	1	1	29469	24	80053	519	505	110	80000	80100	29505	29285	29320	29308	29321
80204	29473	221	0	0	0	0	0	7262	825	1	744	121	248	29400	813	850	1912	1911	2302	25	160153	80154	80000	80100	80000	400757	1301731	1	48	29663	29264	29388	19558	3	19237	160100	200	80000	200	80000	29495	29579	1	1	80201	100	99	26	100	100	80000	80000	1	100	80874	0	415	5318	0	85747	641	15	868	66	5100	86105	730	123	5165	5025	0	0	3	0	5110	1	16	1	1	29403	27	80047	556	580	113	80000	80100	29349	29467	29488	29507	29356
80204	29466	221	0	0	0	0	0	7646	808	1	616	112	144	29510	750	796	1812	2112	2159	25	160152	80151	80000	80100	80000	400784	1301274	1	40	29593	29319	29509	19413	3	19403	160100	200	80000	200	80000	29272	29358	1	1	80201	100	99	32	100	100	80000	80000	1	100	80900	0	371	5186	0	85610	707	11	913	28	5694	86267	780	114	5602	5391	0	0	3	0	5110	1	17	1	1	29280	30	80053	555	534	120	80000	80100	29578	29718	29311	29627	29487
80204	29329	221	0	0	0	0	0	7023	787	1	712	101	152	29448	795	523	1902	1856	2292	25	160155	80144	80000	80100	80000	400814	1302743	1	49	29598	29662	29262	19217	3	19598	160100	200	80000	200	80000	29250	29556	1	1	80201	100	99	44	100	100	80000	80000	1	100	80914	0	345	5890	0	85191	681	18	906	100	5811	86138	742	130	5393	5226	0	0	0	0	5110	1	17	1	1	29416	21	80052	628	555	91	80000	80100	29487	29403	29484	29562	29419

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.3641

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	09	l2 tlb miss data (0b)	0e	0f	18	1e	1f	20	22	24	29	3a	3e	3f	40	43	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	67	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	92	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	l1d cache miss ld (a3)	a5	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ab	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	c3	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	e7	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
80029	29419	218	2	0	0	0	1	1	0	6232	0	821	1	0	720	97	168	29003	785	420	1951	2019	1997	25	160050	80063	80000	80010	80000	400285	1283383	0	38	29063	29197	29077	19193	3	19086	160010	20	80000	20	80000	29027	28896	1	1	80021	10	9	24	10	10	80000	80000	1	10	80887	0	439	5405	0	84851	763	10	897	42	4909	85627	614	142	5464	5567	0	0	3	5020	9	16	5	4	29265	28	80058	383	376	59	80000	80010	29173	29209	29202	29254	29373
80024	29331	218	0	0	0	0	0	0	0	7025	0	788	1	0	720	121	108	29050	812	475	1934	1956	2027	25	160059	80060	80000	80010	80000	400281	1281646	0	43	29065	29038	29256	19129	3	19011	160010	20	80000	20	80000	29098	29054	1	1	80021	10	9	26	10	10	80000	80000	1	10	80905	0	436	4562	0	84563	778	12	915	80	4673	85430	780	126	4064	4433	0	0	3	5020	3	16	2	4	28923	31	80048	354	311	69	80000	80010	29109	29056	29224	29142	29208
80024	29148	219	0	0	0	1	0	0	0	6555	0	788	1	0	752	90	116	29074	793	383	1846	2024	1814	25	160050	80058	80000	80010	80000	400263	1286383	0	47	29114	29088	29109	19155	3	18960	160010	20	80000	20	80000	29025	29213	1	1	80021	10	9	19	10	10	80000	80000	1	10	80897	0	434	4441	0	84447	732	11	902	80	4725	85476	763	117	4753	4619	0	0	3	5020	4	16	4	4	29018	41	80039	411	273	69	80000	80010	29181	29015	29171	29160	29017
80024	29017	216	1	1	0	0	0	0	0	6131	0	799	1	0	720	118	96	29129	791	382	2136	2063	1746	25	160048	80057	80000	80010	80000	400338	1278524	0	30	28960	29115	28938	19034	3	19045	160010	20	80000	20	80000	29003	29093	1	1	80021	10	9	16	10	10	80000	80000	1	10	80890	18	423	5159	0	84707	732	8	904	44	4350	85384	765	135	5054	4992	18	0	3	5020	4	16	4	5	29037	27	80030	414	355	53	80000	80010	29191	29173	29242	29188	28949
80024	29230	218	0	0	0	0	0	0	0	6313	0	816	1	0	704	109	144	29204	794	389	1967	2002	1882	25	160364	80052	80000	80010	80000	400269	1274437	0	45	29122	29072	29261	19206	3	19047	160010	20	80000	20	80000	29147	28937	1	1	80021	10	9	17	10	10	80000	80000	1	10	80912	0	433	4837	0	84538	769	6	881	122	4616	85032	762	117	4876	4361	0	0	3	5020	4	16	4	3	28978	19	80040	323	358	54	80000	80010	29057	29061	29129	28974	29150
80024	29125	217	1	0	0	0	0	0	0	6672	0	824	1	0	720	108	92	28937	806	380	1809	2160	1750	25	160054	80048	80000	80010	80000	400255	1285421	1	39	29155	29122	29025	19076	3	19276	160010	20	80000	20	80000	29170	29071	1	1	80021	10	9	15	10	10	80000	80000	1	10	80918	0	475	5078	0	84959	764	8	909	32	4950	85431	749	127	4292	4815	13	3	9	5020	2	16	2	4	29094	38	80036	313	349	65	80000	80010	29104	28932	29258	28970	28896
80024	28852	217	0	0	0	0	0	0	0	6749	0	807	1	0	728	103	112	28955	781	369	1890	2140	1789	25	160060	80054	80000	80010	80000	400228	1279093	1	35	29106	29085	29133	19350	3	19057	160010	20	80000	20	80000	29101	29142	1	1	80021	10	9	25	10	10	80000	80000	1	10	80912	0	436	5243	0	84816	775	6	897	36	4697	85743	712	127	4832	4867	0	0	3	5020	3	16	4	6	29055	26	80045	403	353	64	80000	80010	29196	29234	29129	28876	29157
80024	29201	217	0	0	0	0	0	0	0	5978	0	818	1	0	712	101	144	29011	794	389	1889	1911	1890	25	160053	80053	80000	80010	80000	400318	1280351	0	36	29281	29169	28980	19130	3	19018	160010	20	80000	20	80000	29099	29199	1	1	80021	10	9	20	10	10	80000	80000	1	10	80918	18	428	4826	0	84682	782	10	936	32	4484	86182	740	121	4609	4953	17	0	4	5020	4	16	4	4	29099	27	80035	376	373	53	80000	80010	29210	29144	29133	29196	29238
80024	29104	218	0	0	0	0	0	0	0	6389	0	804	1	0	744	96	112	28941	795	420	1659	1802	1781	25	160048	80050	80000	80010	80000	400293	1285697	1	39	28851	29183	29124	19203	3	19096	160010	20	80000	20	80000	29121	29135	1	1	80021	10	9	25	10	10	80000	80000	1	10	80911	0	461	5536	0	84986	748	7	903	48	4459	85857	769	122	4202	5110	0	0	3	5020	2	16	6	6	28950	32	80036	385	363	58	80000	80010	29109	29092	29117	29173	29135
80024	29154	218	0	0	0	0	0	0	0	6221	0	805	1	0	768	95	112	29048	770	409	2102	2067	1991	25	160054	80052	80000	80194	80000	400277	1282842	1	43	28985	29313	29089	19074	3	19129	160010	20	80000	20	80000	29189	29164	1	1	80021	10	9	21	10	10	80000	80000	1	10	80882	0	489	5069	0	84754	738	8	890	38	4706	85297	674	123	4628	5450	0	0	15	5020	6	16	6	6	28981	31	80050	350	354	60	80000	80010	29009	29056	29017	29284	29162

LDR (post-index, S)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->2 roundtrip

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations