Firestorm: LDR (pre-index, D) measurements

Code:

  ldr d0, [x6, #8]!

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 2.000

Integer unit issues: 1.000

Load/store unit issues: 1.000

SIMD/FP unit issues: 0.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	09	l2 tlb miss data (0b)	0e	0f	1e	20	22	23	24	3a	3e	3f	40	43	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map ldst uop (7d)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst simd load (98)	inst ldst (9b)	9d	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	l1d cache miss ld (a3)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ab	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	c2	c3	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
1005	1056	8	1	1	1	1	0	1	105	37	1	0	0	1	0	1025	23	33	2	4	19	25	2000	1000	1000	1000	1000	50730	45826	1	1015	1040	1040	824	3	899	2000	1000	1000	1040	1040	1	1	1001	1000	1000	0	1016	0	1	84	1073	2	2	28	14	49	1066	46	6	53	79	0	1	75	5	16	6	6	1037	1000	53	44	1000	1000	1041	1041	1041	1041	1041
1004	1040	8	0	0	0	0	0	1	95	16	1	0	0	1	4	1025	20	37	0	5	15	25	2000	1000	1000	1000	1000	50714	45824	0	1015	1040	1040	824	3	897	2000	1000	1000	1040	1040	1	1	1001	1000	1000	0	1010	6	0	38	1074	2	0	31	14	72	1071	36	6	52	58	0	0	75	5	16	5	6	1037	1000	39	37	1000	1000	1041	1041	1041	1041	1041
1004	1040	8	0	0	0	1	0	1	120	0	0	0	0	2	0	1025	10	37	0	1	28	25	2000	1000	1000	1000	1000	50690	45824	1	1015	1040	1040	824	3	898	2000	1000	1000	1040	1040	1	1	1001	1000	1000	0	1020	0	0	48	1059	2	0	20	14	47	1058	30	6	51	55	0	1	75	5	16	5	5	1037	1000	42	40	1000	1000	1041	1041	1090	1041	1041
1004	1040	8	0	0	0	0	0	1	84	0	0	0	0	1	0	1025	0	32	0	0	23	25	2000	1000	1000	1000	1000	50722	45823	1	1015	1040	1040	824	3	898	2000	1000	1000	1040	1040	1	1	1001	1000	1000	0	1020	0	0	41	1073	3	0	30	8	54	1058	36	5	54	55	0	0	75	6	16	5	5	1037	1000	31	30	1000	1000	1041	1041	1041	1041	1041
1004	1040	8	0	0	0	0	0	1	97	14	1	0	0	1	8	1025	9	32	0	6	20	25	2000	1000	1000	1000	1000	50754	45824	0	1015	1040	1040	824	3	897	2000	1000	1000	1040	1040	1	1	1001	1000	1000	0	1014	0	2	63	1071	5	0	20	10	62	1062	36	4	47	47	0	0	75	5	16	5	5	1037	1000	28	24	1000	1000	1041	1041	1041	1041	1041
1004	1040	7	0	0	0	0	0	1	102	16	1	0	0	3	0	1025	14	37	2	1	22	25	2000	1000	1000	1000	1000	50746	45824	1	1015	1040	1040	824	3	897	2000	1000	1000	1040	1040	1	1	1001	1000	1000	0	1028	0	0	52	1050	0	0	0	0	48	1062	30	7	52	52	0	1	77	6	17	6	6	1037	1000	38	30	1000	1000	1041	1041	1041	1041	1041
1004	1040	8	0	0	0	0	0	1	102	0	0	0	0	2	4	1025	10	33	4	7	31	25	2000	1000	1000	1000	1000	50762	45823	1	1015	1040	1040	824	3	897	2000	1000	1000	1040	1040	1	1	1001	1000	1000	0	1040	0	0	49	1074	1	2	29	18	48	1083	36	5	51	61	0	0	75	6	16	5	5	1037	1000	32	23	1000	1000	1041	1041	1041	1041	1041
1004	1040	8	0	0	0	0	0	1	102	21	1	0	0	2	0	1025	17	33	3	5	24	25	2000	1000	1000	1000	1000	50706	45825	0	1015	1040	1040	824	3	898	2000	1000	1000	1040	1040	1	1	1001	1000	1000	0	1038	0	1	60	1054	0	0	20	6	47	1056	36	5	56	39	0	0	77	5	17	6	6	1037	1000	38	42	1000	1000	1041	1041	1041	1041	1041
1004	1040	8	0	0	0	0	0	1	93	18	1	0	0	1	12	1025	5	37	2	2	22	25	2000	1000	1000	1000	1000	50738	45819	1	1015	1040	1040	824	3	897	2000	1000	1000	1040	1040	1	1	1001	1000	1000	0	1000	0	0	76	1069	3	1	12	0	46	1048	30	7	57	80	0	1	75	6	17	6	6	1037	1000	44	43	1000	1000	1041	1041	1041	1041	1041
1004	1040	8	0	0	0	0	0	1	79	19	0	0	0	2	0	1025	17	37	2	8	21	25	2000	1000	1000	1000	1000	50738	45824	1	1015	1040	1040	824	3	897	2000	1000	1000	1040	1040	1	1	1001	1000	1000	0	1024	0	0	63	1063	3	0	22	14	49	1078	36	5	53	34	0	1	75	6	16	6	5	1037	1000	51	39	1000	1000	1041	1041	1041	1041	1041

Test 2: Latency 1->2 roundtrip

Chain cycles: 3

Code:

  ldr d0, [x6, #8]!
  fmov x0, d0
  eor x8, x8, x0
  eor x8, x8, x0
  add x6, x6, x8

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 9.1857

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	09	l2 tlb miss data (0b)	0e	0f	18	1e	1f	20	22	29	3a	3e	3f	40	43	49	4d	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	69	6b	6d	6e	map stall dispatch (70)	int prf full (71)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	l1d cache miss ld (a3)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ab	ac	af	b5	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	c3	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
50209	122373	912	0	0	2	0	0	0	0	447	0	815	1	704	0	112	122008	812	3	3	121792	25	70520	50350	10124	10000	40100	10000	10000	1077579	4612446	4655921	0	121687	0	121838	121854	115162	0	3	115543	60100	30200	10000	10000	60200	10000	10000	121778	121777	1	1	50201	100	99	100	40100	10000	10000	1	100	10936	0	118	531	10709	213	9	937	36	20	10957	117	2	134	0	15	5	0	3210	1	76	1	1	121557	50242	1020	1147	896	10000	50100	121780	121726	121849	121905	121902
50204	121805	913	0	0	0	0	0	0	0	444	0	830	1	736	1	116	121927	786	2	2	121576	25	70499	50374	10129	10002	40100	10000	10000	1078479	4606477	4651872	0	121757	0	121925	121774	114997	0	3	115484	60100	30200	10000	10000	60200	10000	10000	121752	121811	1	1	50201	100	99	100	40100	10000	10000	0	100	10958	0	112	531	10711	224	12	928	32	20	10947	120	2	122	0	0	3	0	3210	1	76	1	1	121832	50262	982	1032	876	10000	50100	121736	121706	121847	121757	122152
50204	121759	912	0	0	0	0	0	0	0	437	0	825	1	720	0	92	121923	808	3	3	121630	25	70478	50362	10125	10000	40100	10000	10000	1079613	4607395	4655303	0	121706	0	121848	122052	115294	0	3	115386	60100	30200	10000	10000	60200	10000	10000	121811	121910	1	1	50201	100	99	100	40100	10000	10000	0	100	10891	0	110	519	10742	207	8	918	32	18	10947	133	3	125	0	9	11	0	3210	1	76	1	1	121509	50236	1085	1082	945	10000	50100	121893	122071	121971	121926	121731
50204	121877	914	1	0	0	0	0	0	0	413	0	811	1	696	1	108	121635	800	2	3	121495	25	70487	50346	10131	10000	40100	10000	10000	1077363	4610332	4653556	0	121795	0	121852	122032	114877	0	3	115315	60100	30200	10000	10000	60200	10000	10000	121647	121838	1	1	50201	100	99	100	40100	10000	10000	0	100	10942	1	121	525	10707	214	6	912	34	25	10940	111	4	116	1	0	5	0	3210	1	76	1	1	121590	50250	1107	1010	989	10000	50100	121903	121922	121933	121905	121913
50204	121701	912	1	1	1	1	0	0	0	458	0	788	1	728	1	108	121860	782	2	2	121527	25	70475	50366	10124	10000	40100	10000	10000	1078146	4604589	4651950	0	121899	0	121927	121880	115094	0	3	115541	60100	30200	10000	10000	60200	10000	10000	121758	122001	1	1	50201	100	99	100	40100	10000	10000	0	100	10899	1	113	534	10728	207	9	934	52	18	10910	125	3	122	1	3	11	0	3210	1	76	1	1	121650	50296	1081	1179	974	10000	50100	121922	121771	121727	121863	122063
50204	121955	914	1	0	0	0	0	0	0	437	0	812	1	712	1	124	121905	788	2	3	121556	25	70487	50350	10130	10000	40100	10000	10000	1079766	4607840	4656832	0	121830	0	121969	121777	115040	0	3	115651	60100	30200	10000	10000	60200	10000	10000	121933	121784	1	1	50201	100	99	100	40100	10000	10000	0	100	10911	1	113	515	10792	211	11	931	36	21	10940	130	4	133	1	3	3	0	3210	1	76	1	1	121606	50254	1107	1155	944	10000	50100	121793	121913	122063	122005	121720
50204	121806	912	1	0	0	0	0	0	0	460	0	819	1	728	1	104	121759	798	3	3	122635	638	70873	50633	10162	10056	44001	11239	11182	1138695	4671317	4719589	0	123903	0	124283	124463	116201	0	226	116887	66198	33708	10121	11158	68612	11133	11188	124268	124511	30	1	50201	100	99	100	40100	10000	10000	0	100	10926	1	127	529	10712	216	8	937	78	36	10925	118	3	129	0	6	18	0	3895	1	291	4	2	124235	50584	1141	1059	918	10000	50100	124940	124436	124939	125201	124929
50204	124365	936	1	1	0	0	0	0	21	430	0	827	1	736	0	144	121982	801	3	4	121409	25	70460	50344	10132	10000	40100	10000	10000	1078722	4602592	4656028	0	121918	0	121910	122036	115121	0	3	115413	60100	30200	10000	10000	60200	10000	10000	122011	121575	1	1	50202	100	99	100	40100	10000	10000	0	100	10947	0	118	538	10720	208	9	945	72	15	10970	128	2	123	0	3	10	0	3210	1	76	1	1	121492	50252	1078	1042	885	10000	50100	121784	121626	121783	122024	121924
50204	121813	912	0	0	0	0	0	0	0	439	0	831	1	768	0	108	121820	821	3	2	121524	25	70493	50332	10128	10000	40100	10000	10000	1077480	4601170	4655681	0	121928	0	121892	121888	115160	0	3	115496	60100	30200	10000	10000	60200	10000	10000	121770	121774	1	1	50201	100	99	100	40100	10000	10000	0	100	10908	0	120	537	10725	213	10	914	76	21	10948	130	4	120	1	0	9	0	3210	1	76	1	1	121608	50254	1081	1058	933	10000	50100	121912	121815	121819	121926	121885
50204	121941	913	1	0	0	0	0	0	0	455	0	867	1	800	1	108	121877	794	3	2	121466	25	70523	50380	10134	10000	40100	10000	10000	1079748	4606414	4657596	0	121997	0	121767	121916	115131	0	3	115519	60100	30200	10000	10000	60200	10000	10000	121918	122065	1	1	50201	100	99	100	40100	10000	10000	0	100	10932	0	100	520	10742	206	8	914	36	11	10917	124	2	126	0	0	12	0	3210	1	76	1	1	121712	50266	1154	1030	977	10000	50100	121933	121680	121867	121860	121802

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 9.1879

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk instruction (07)	mmu table walk data (08)	09	l2 tlb miss instruction (0a)	l2 tlb miss data (0b)	0e	0f	19	1e	1f	20	22	29	3a	3e	3f	40	43	49	4d	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	69	6b	6d	6e	map stall dispatch (70)	int prf full (71)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	l1d cache miss ld (a3)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ab	ac	af	b5	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	c3	cd	cf	d0	d5	map dispatch bubble (d6)	da	db	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
50029	121946	912	0	0	0	0	0	0	0	0	0	428	0	841	1	696	2	120	121771	804	3	2	121419	25	70418	50260	10129	10000	40010	10000	10000	1080706	4611101	4654356	121958	0	121814	121690	115128	0	3	115385	60010	30020	10000	10000	60020	10000	10000	121760	121841	1	1	50021	10	9	10	40010	10000	10000	0	10	10923	1	109	530	10713	208	13	920	72	36	10914	116	3	116	1	19	17	0	3140	0	17	82	0	0	12	9	121635	50266	1065	1172	962	10000	50010	121815	121870	121947	122076	121848
50024	121919	913	2	0	0	0	0	2	0	0	0	456	0	825	1	736	1	112	121984	787	2	2	121741	25	70418	50252	10128	10000	40010	10000	10000	1078483	4612968	4655004	121867	0	121888	121935	115321	0	3	115538	60010	30020	10000	10000	60020	10000	10000	121978	121816	1	1	50021	10	9	10	40010	10000	10000	0	10	10919	1	112	530	10708	209	11	890	74	30	10890	126	3	130	1	3	13	0	3140	0	10	82	0	0	12	11	121749	50274	1050	1094	992	10000	50010	121837	122031	121818	122004	121894
50024	121808	911	0	0	0	0	0	0	0	0	0	439	0	840	1	728	1	104	121952	812	2	2	121595	25	70397	50274	10128	10000	40010	10000	10000	1079167	4612449	4656770	121934	0	121953	121870	115183	0	3	115644	60010	30020	10000	10000	60020	10000	10000	121751	121831	1	1	50021	10	9	10	40010	10000	10000	0	10	10919	1	88	550	10718	211	11	945	72	27	10932	139	3	122	0	3	12	0	3140	0	9	82	0	1	12	9	121761	50272	1011	1079	967	10000	50010	121916	121991	122033	122000	121922
50024	121802	913	0	0	0	0	0	0	0	0	0	453	0	838	1	712	0	80	121936	809	2	2	121630	25	70421	50260	10136	10000	40010	10000	10000	1079329	4611519	4661539	121860	0	121821	121814	115144	0	3	115672	60010	30020	10000	10000	60020	10000	10000	121984	121817	1	1	50021	10	9	10	40010	10000	10000	0	10	10891	1	115	536	10703	185	12	953	80	39	10906	134	3	126	1	6	9	0	3140	0	8	82	0	0	10	8	121564	50252	1025	1047	946	10000	50010	121783	122012	121805	122034	121892
50024	121841	913	1	0	0	0	0	1	0	0	0	456	0	829	1	696	1	136	121863	801	2	2	121542	25	70418	50268	10135	10000	40161	10000	10000	1079284	4609254	4652237	121828	0	121817	122003	115204	0	3	115509	60010	30020	10000	10000	60020	10000	10000	121921	121835	1	1	50021	10	9	10	40010	10000	10000	0	10	10936	1	114	535	10712	204	14	940	70	45	10925	150	4	119	0	0	9	0	3140	0	10	82	0	0	15	11	121652	50262	1089	1023	923	10000	50010	121750	121862	121768	121841	121826
50024	121760	912	0	0	0	0	0	0	1	0	0	442	0	845	1	616	1	132	122002	808	2	2	121542	25	70382	50254	10128	10000	40010	10000	10000	1078807	4602225	4655833	121833	0	121895	121880	115106	0	3	115506	60010	30020	10000	10000	60020	10000	10000	121949	121886	1	1	50021	10	9	10	40010	10000	10000	0	10	10900	0	110	536	10689	206	8	1019	72	35	10924	122	2	124	0	3	8	0	3140	0	7	82	0	0	11	15	121508	50250	992	964	947	10000	50010	121934	121966	121936	121934	122021
50024	121895	913	2	0	0	0	0	0	0	1	0	440	0	825	1	784	2	108	121929	790	2	2	121597	25	70382	50272	10127	10000	40010	10000	10000	1078816	4609229	4662530	121991	0	121872	121901	115135	0	3	115625	60010	30020	10000	10000	60020	10000	10000	122172	121970	5	1	50021	10	9	10	40010	10000	10000	1	10	10869	2	111	547	10717	214	8	917	72	26	10912	126	4	125	2	6	9	0	3140	0	10	82	0	0	11	10	121636	50254	1022	1148	900	10000	50010	121900	122002	121850	121834	121901
50024	121738	913	2	0	1	2	0	2	0	0	0	440	0	826	1	704	2	96	121893	798	2	2	121729	25	70451	50288	10130	10000	40010	10000	10000	1078717	4610374	4660480	122037	0	121941	122200	115258	0	20	115542	60010	30266	10080	10082	60750	10000	10040	122066	122663	3	1	50021	10	9	10	40010	10000	10000	1	10	10859	4	115	530	10717	211	11	928	118	28	10921	129	5	130	2	3	3	0	3140	0	9	82	0	0	13	12	121834	50290	1051	1174	968	10000	50010	121867	121842	121854	121937	121908
50024	122051	914	2	0	0	0	0	0	0	0	0	501	0	882	1	712	2	112	121914	813	3	4	121595	25	70385	50254	10137	10000	40010	10000	10000	1077952	4608179	4662537	122007	0	121814	121904	115140	0	3	115668	60010	30020	10000	10000	60020	10000	10000	121913	122031	1	1	50021	10	9	10	40010	10000	10000	0	10	10932	2	109	530	10713	201	10	934	86	40	10940	136	5	127	2	0	16	0	3140	0	9	82	0	0	15	9	121648	50244	1062	1043	968	10000	50010	121915	121883	121927	121987	121899
50024	121993	913	2	0	0	1	0	0	0	0	0	399	0	813	1	728	0	116	121752	784	3	2	121592	25	70409	50270	10117	10000	40010	10000	10000	1077169	4605456	4664988	121825	0	121934	121849	115248	0	3	115547	60010	30020	10000	10000	60020	10000	10000	121900	121823	1	1	50021	10	9	10	40010	10000	10000	0	10	10910	0	107	545	10699	206	10	912	46	23	10942	127	2	124	0	3	14	0	3140	0	8	82	0	0	14	10	121627	50262	1064	1087	904	10000	50010	122048	121901	121842	122028	121876

Test 3: throughput

Count: 8

Code:

  ldr d0, [x6, #8]!
  ldr d0, [x7, #8]!
  ldr d0, [x8, #8]!
  ldr d0, [x9, #8]!
  ldr d0, [x10, #8]!
  ldr d0, [x11, #8]!
  ldr d0, [x12, #8]!
  ldr d0, [x13, #8]!

Initialization

  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.3667

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	09	0e	0f	1e	1f	20	22	29	3a	3e	3f	40	43	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	67	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	92	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	l1d cache miss ld (a3)	a5	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ab	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	c3	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	e7	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
80209	29458	219	1	0	1	0	0	6831	0	829	1	744	130	112	29336	791	334	1637	1644	2038	25	160140	80144	80000	80100	80000	400707	1287278	1	53	29383	29154	29349	19105	3	19303	160100	200	80000	200	80000	29461	29416	1	1	80201	100	99	41	100	100	80000	80000	0	100	80914	0	411	4719	0	85221	639	15	910	74	5357	85329	754	119	4761	4695	0	0	0	5110	1	17	1	1	29356	39	80045	583	546	90	80000	80100	29366	29480	29231	29411	29229
80204	29423	219	0	0	0	0	0	6925	0	812	1	792	128	140	29388	795	400	1588	1634	2285	25	160152	80133	80000	80100	80000	400721	1286393	1	47	29363	29380	29451	19329	3	19429	160100	200	80000	200	80000	29281	29374	1	1	80201	100	99	50	100	100	80000	80000	0	100	80909	0	409	5328	0	85185	634	11	929	78	4606	85556	753	135	4446	4900	0	0	3	5110	1	17	1	1	29284	37	80034	551	552	91	80000	80100	29316	29266	29496	29362	29294
80204	29297	219	0	0	0	0	0	6330	0	823	1	712	117	68	29140	815	299	1539	1591	2083	25	160136	80138	80000	80100	80000	400733	1291177	1	43	29286	29445	29222	19128	3	19275	160100	200	80766	200	80000	29605	29378	1	1	80201	100	99	35	100	100	80000	80000	0	100	80926	0	371	5322	0	85150	693	16	905	44	5243	85284	876	139	4469	5272	0	0	0	5110	1	17	1	1	29361	38	80035	557	562	87	80000	80100	29238	29391	29277	29304	29383
80204	29409	219	0	0	0	0	1	6596	0	817	1	712	135	112	29220	837	377	1613	1822	2140	25	160139	80151	80000	80100	80000	400749	1291220	1	40	29377	29215	29375	19166	3	19502	160100	200	80000	200	80000	29486	29411	1	1	80201	100	99	30	100	100	80000	80000	0	100	80936	0	421	5399	0	84727	701	14	934	32	4473	85849	832	123	4572	5229	0	0	3	5110	1	17	1	1	29108	26	80051	530	625	90	80000	80100	29319	29372	29285	29318	29237
80204	29320	220	0	0	0	1	0	6710	0	856	1	664	123	100	29280	819	324	1676	1887	1952	25	160140	80144	80000	80100	80000	400763	1298728	1	46	29267	29347	29519	19378	3	19177	160100	200	80000	200	80000	29372	29380	1	1	80201	100	99	39	100	100	80000	80000	0	100	80934	0	411	5620	0	85011	668	12	961	76	5176	85906	896	126	4478	4784	0	0	3	5110	1	17	1	1	29384	23	80044	562	533	90	80000	80100	29351	29239	29223	29457	29389
80204	29401	219	0	0	0	0	0	6660	0	849	1	736	95	104	29261	817	359	1524	1888	2130	25	160154	80140	80000	80100	80000	400749	1295576	1	52	29341	29346	29532	19222	3	19227	160100	200	80000	200	80000	29538	29378	1	1	80201	100	99	54	100	100	80000	80000	0	100	80951	0	414	5311	0	85324	654	10	952	80	5679	85591	738	120	4833	5389	0	3	3	5110	1	17	1	1	29489	33	80042	592	623	104	80000	80100	29376	29333	29461	29369	29195
80204	29402	218	0	0	0	1	1	6566	0	858	1	744	109	116	29506	838	340	1687	1695	2174	25	160143	80143	80000	80100	80000	400728	1298801	1	43	29359	29256	29263	19362	3	19293	160100	200	80000	200	80000	29383	29225	1	1	80201	100	99	23	100	100	80000	80000	0	100	80897	0	392	5301	0	84873	699	9	936	134	4738	85650	868	122	4614	4821	0	0	9	5110	1	17	1	1	29131	31	80056	583	547	108	80000	80100	29289	29274	29298	29402	29290
80204	29269	219	0	0	0	1	0	6675	0	823	1	712	124	184	29315	818	373	1741	1806	2158	25	160145	80136	80000	80100	80000	400733	1285708	1	46	29432	29190	29391	19078	3	19262	160100	200	80000	200	80000	29434	29320	1	1	80201	100	99	49	100	100	80000	80000	0	100	80945	0	391	4502	0	84608	676	10	895	54	4877	85511	879	133	4843	4875	0	0	7	5110	1	17	1	1	29389	41	80045	612	554	102	80000	80100	29380	29454	29248	29288	29384
80204	29264	219	0	0	0	1	0	6659	0	833	1	712	113	116	29390	805	340	1857	1602	1988	25	160140	80146	80000	80100	80000	400727	1290870	1	55	29255	29328	29349	19182	3	19407	160100	200	80000	200	80000	29371	29350	1	1	80201	100	99	45	100	100	80000	80000	0	100	80934	0	419	5169	0	84981	690	13	905	78	5096	86038	809	141	4677	5135	0	0	7	5110	1	17	1	1	29609	24	80036	594	617	87	80000	80100	29585	29404	29497	29311	29109
80204	29418	218	0	0	0	1	0	7021	0	829	1	768	136	120	29295	799	356	1952	1654	1935	25	160153	80154	80000	80100	80000	400797	1302968	1	46	29613	29363	29288	19175	3	19230	160100	200	80000	200	80000	29360	29217	1	1	80201	100	99	44	100	100	80000	80000	0	100	80930	0	405	5768	0	84931	633	11	944	48	5223	85948	746	118	4943	5305	0	0	0	5110	1	16	1	1	29484	25	80048	522	599	91	80000	80100	29445	29216	29488	29579	29478

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.3762

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	l2 tlb miss data (0b)	0e	0f	19	1e	20	22	29	3a	3e	3f	40	43	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	5f	60	67	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	92	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst ldst (9b)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	l1d cache miss ld (a3)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ab	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	c3	cf	d0	d2	l1i cache miss demand (d3)	d5	map dispatch bubble (d6)	db	dd	fetch restart (de)	e0	e7	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
80029	30485	224	3	0	0	0	1	0	8525	853	1	704	135	140	30060	780	1992	1662	2024	2450	25	160071	80068	80000	80010	80000	400430	1323035	0	1	69	30037	30049	30077	19884	3	20166	160010	20	80000	20	80000	30211	30144	1	1	80021	10	9	28	10	10	80000	80000	10	80980	51	312	5803	86789	572	11	882	42	6636	87903	757	126	6797	6039	53	0	3	5020	0	0	0	1	16	0	1	1	29953	29	80079	781	716	153	80000	80010	29989	30191	30045	30079	30225
80024	30202	225	3	0	0	0	1	0	8685	806	1	664	123	120	30062	798	2276	1906	2054	2535	25	160067	80067	80000	80010	80000	400351	1324454	0	0	66	29712	29826	30040	19840	3	19964	160010	20	80000	20	80000	30068	30112	1	1	80021	10	9	41	10	10	80000	80000	10	80961	36	387	5479	87316	621	8	907	48	7294	87061	811	131	6378	5083	35	0	5	5020	0	0	0	1	16	1	1	1	29783	31	80065	704	672	144	80000	80010	30252	29978	30278	30112	29859
80024	30144	226	2	0	0	0	1	0	8783	836	1	744	123	144	30403	802	2113	1628	1972	2813	25	160062	80074	80000	80010	80000	400307	1329203	0	0	56	30218	30222	30225	20121	3	19957	160010	20	80000	20	80000	30011	30295	1	1	80021	10	9	39	10	10	80000	80000	10	80955	17	383	5829	86796	640	15	950	52	6484	88464	748	128	6761	5893	18	2	0	5020	0	0	0	1	16	0	1	1	30378	35	80059	688	680	127	80000	80010	29979	30317	30166	30359	30080
80024	30053	226	1	1	0	0	1	0	8692	819	1	712	117	108	30143	791	2298	1466	2169	2768	25	160081	80085	80000	80010	80000	400411	1325491	0	1	67	30120	30261	29883	20160	3	20131	160010	20	80000	20	80000	29958	29793	1	1	80021	10	9	39	10	10	80000	80000	10	80929	15	319	6496	87344	623	10	911	46	6711	88225	800	139	7093	5892	18	0	3	5020	0	0	0	1	16	0	1	2	30029	36	80069	687	689	134	80000	80010	30177	30059	30271	30222	30106
80024	29985	225	2	0	0	0	1	0	8951	805	1	704	121	148	30062	806	2047	1769	2057	2598	25	160066	80071	80000	80010	80000	400415	1328027	0	1	66	29976	29889	30040	20080	21	19856	160010	20	80000	20	80000	30277	30115	1	1	80021	10	9	58	10	10	80000	80000	10	80923	35	344	5462	87237	620	12	974	76	6994	87184	734	119	7188	5320	33	0	10	5020	0	0	0	1	16	0	1	1	29564	24	80056	700	658	140	80000	80010	29970	29979	29984	30223	30132
80024	30032	226	2	0	0	0	1	0	8974	790	1	696	128	140	30254	806	2132	1817	1821	2323	25	160070	80076	80000	80010	80000	400324	1321228	0	1	69	30153	30345	30163	20133	3	20043	160010	20	80000	20	80000	29824	30147	1	1	80021	10	9	31	10	10	80000	80000	10	80956	32	342	5601	86811	658	13	883	46	6894	87624	765	126	7024	5630	37	3	4	5020	0	0	0	1	16	0	1	1	29983	33	80059	705	703	130	80000	80010	30032	30053	30360	30298	29996
80024	30152	224	2	0	0	0	1	0	7966	788	1	632	105	140	30079	824	2138	1801	1924	2803	25	160078	80079	80000	80010	80000	400418	1313565	0	1	65	30324	30161	29831	20159	3	20156	160010	20	80000	20	80000	29940	29784	1	1	80021	10	9	41	10	10	80000	80000	10	80980	30	341	6495	88020	603	13	936	42	7101	88038	779	132	7380	5477	31	6	3	5020	0	0	0	1	16	0	1	1	29973	33	80054	655	669	133	80000	80010	30212	30101	30126	30111	30345
80024	30026	224	2	0	2	0	1	0	8322	771	1	736	121	100	29939	815	1993	1718	2128	2518	25	160072	80073	80000	80010	80000	400381	1321466	0	1	53	30266	30383	30373	20047	3	20039	160010	20	80000	20	80000	30283	30202	1	1	80021	10	9	48	10	10	80000	80000	10	80983	51	330	6161	87572	678	9	960	98	7074	87701	767	122	6391	4619	54	3	8	5020	0	0	0	1	16	0	1	1	30133	40	80057	606	632	145	80000	80010	30027	29980	30149	29920	30122
80024	30025	223	3	0	0	0	1	0	9223	858	1	712	130	128	30017	791	2219	1579	2087	2761	25	160068	80080	80000	80010	80000	400325	1330631	0	0	70	30146	30143	30180	20015	3	20085	160010	20	80000	20	80000	29933	30010	1	1	80021	10	9	35	10	10	80000	80000	10	81128	57	322	6110	87110	674	12	916	82	7277	87450	802	132	7306	5294	51	0	3	5020	0	0	0	1	16	0	1	1	30115	34	80060	681	676	143	80000	80010	30259	30328	30292	30446	30069
80024	30286	226	3	2	0	0	1	0	8610	808	1	704	143	104	30131	823	2076	1945	2050	2586	25	160072	80069	80000	80010	80000	400421	1337075	0	0	62	29977	30608	30112	20022	3	20318	160010	20	80000	20	80000	30110	29766	1	1	80021	10	9	42	10	10	80000	80000	10	80950	54	363	6082	87447	646	7	888	46	6833	87561	796	129	6949	5643	52	0	3	5020	0	0	0	1	16	0	1	1	30168	28	80074	643	697	120	80000	80010	30198	29967	29908	30163	30259

LDR (pre-index, D)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->2 roundtrip

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations