Firestorm: LDR (pre-index, Q) measurements

Code:

  ldr q0, [x6, #8]!

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 2.000

Integer unit issues: 1.000

Load/store unit issues: 1.000

SIMD/FP unit issues: 0.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	09	l2 tlb miss data (0b)	0e	0f	1e	20	22	23	29	2b	3a	3e	3f	40	43	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map ldst uop (7d)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst simd load (98)	inst ldst (9b)	9d	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	l1d cache miss ld (a3)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ab	ac	af	ldst x64 uop (b1)	b5	b6	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	c3	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
1005	1040	8	1	1	1	0	0	0	93	28	1	0	0	3	4	12	1029	13	4	5	7	25	25	2000	1000	1000	1000	1000	50754	45823	1	1015	1040	1040	824	3	898	2000	1000	1000	1040	1040	1	1	1001	1000	1000	1	1034	6	2	74	1051	1	0	55	12	38	1069	125	73	11	57	92	7	0	0	73	1	16	1	1	1037	1000	25	22	1000	1000	1041	1041	1041	1041	1041
1004	1040	8	1	1	1	0	0	0	99	19	0	0	0	0	5	0	1025	12	2	1	6	23	25	2000	1000	1000	1000	1000	50770	45824	1	1015	1040	1040	824	3	898	2000	1000	1000	1040	1040	1	1	1001	1000	1000	0	1008	8	0	50	1052	4	1	30	6	23	1033	125	56	10	30	54	7	27	0	73	1	16	1	1	1037	1000	25	24	1000	1000	1041	1041	1041	1041	1041
1004	1040	8	1	1	0	0	0	1	87	19	1	0	0	0	4	0	1025	7	1	2	2	26	25	2000	1000	1000	1000	1000	50754	45824	1	1015	1040	1040	824	3	898	2000	1000	1000	1040	1040	1	1	1001	1000	1000	0	1030	7	0	86	1049	6	0	33	6	33	1057	125	35	11	28	69	6	1	0	73	1	16	1	1	1037	1000	37	22	1000	1000	1041	1041	1041	1041	1041
1004	1040	8	1	1	1	0	0	0	72	24	0	0	0	0	5	0	1025	15	2	9	2	30	25	2000	1000	1000	1000	1000	50730	45824	1	1015	1040	1040	824	3	898	2000	1000	1000	1040	1040	1	1	1001	1000	1000	0	1037	7	0	78	1073	14	1	24	0	33	1044	125	83	12	29	60	6	0	0	73	1	16	1	1	1037	1000	23	16	1000	1000	1041	1041	1041	1041	1041
1004	1040	8	1	1	1	0	0	0	64	14	1	0	0	0	1	0	1025	11	1	2	4	29	25	2000	1000	1000	1000	1000	50746	45825	1	1015	1040	1040	824	3	898	2000	1000	1000	1040	1040	1	1	1001	1000	1000	0	1022	8	2	91	1058	4	0	17	22	33	1034	125	72	6	34	85	6	0	3	73	1	16	1	1	1037	1000	31	25	1000	1000	1041	1041	1041	1041	1041
1004	1040	7	1	1	1	0	0	0	80	0	0	0	0	0	4	40	1025	32	2	2	2	20	25	2000	1000	1000	1000	1000	50754	45824	1	1015	1040	1040	824	3	898	2000	1000	1000	1040	1040	1	1	1001	1000	1000	0	1023	8	2	47	1054	1	1	24	6	25	1036	125	65	9	38	69	7	13	0	73	1	16	1	1	1037	1000	39	47	1000	1000	1041	1041	1041	1041	1041
1004	1040	7	1	1	1	0	0	0	62	16	0	0	0	0	4	0	1025	20	0	3	7	29	25	2000	1000	1000	1000	1000	50762	45824	1	1015	1040	1040	824	3	898	2000	1000	1000	1040	1040	1	1	1001	1000	1000	0	1043	9	0	99	1057	2	1	34	10	50	1056	125	55	8	39	50	7	0	46	73	1	16	1	1	1037	1000	37	46	1000	1000	1041	1041	1041	1041	1041
1004	1040	7	1	1	1	0	0	0	97	28	1	0	0	0	1	0	1025	8	5	2	3	21	25	2000	1000	1000	1000	1000	50738	45824	1	1015	1040	1040	824	3	898	2000	1000	1000	1040	1040	1	1	1001	1000	1000	0	1018	14	0	115	1063	6	1	32	18	41	1063	125	88	7	52	108	7	11	1	73	1	16	1	1	1036	1000	25	44	1000	1000	1041	1045	1041	1041	1041
1004	1040	8	1	1	0	0	1	0	53	18	1	0	0	0	2	0	1025	0	2	2	2	23	25	2000	1000	1000	1000	1000	50746	45824	1	1015	1040	1040	824	3	898	2000	1000	1000	1040	1040	1	1	1001	1000	1000	0	1029	8	0	83	1061	13	1	10	12	41	1046	125	59	8	34	59	7	0	0	73	1	16	1	1	1037	1000	49	38	1000	1000	1041	1041	1041	1041	1041
1004	1040	7	1	0	0	0	0	0	81	22	2	0	0	0	4	0	1025	10	3	0	3	21	25	2000	1000	1000	1000	1000	50754	45824	0	1015	1040	1040	824	3	898	2000	1000	1000	1040	1040	1	1	1001	1000	1000	0	1049	8	1	105	1046	6	1	13	0	50	1069	125	74	8	37	42	6	2	44	73	1	16	1	1	1037	1000	25	16	1000	1000	1041	1041	1041	1041	1041

Test 2: Latency 1->2 roundtrip

Chain cycles: 3

Code:

  ldr q0, [x6, #8]!
  fmov x0, d0
  eor x8, x8, x0
  eor x8, x8, x0
  add x6, x6, x8

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 9.8889

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk instruction (07)	mmu table walk data (08)	09	l2 tlb miss instruction (0a)	l2 tlb miss data (0b)	0e	0f	18	19	1e	1f	20	22	23	3a	3f	40	43	46	49	4d	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	69	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	af	ldst x64 uop (b1)	ldst xpg uop (b2)	b5	bb	be	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	c3	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
50209	133470	987	4	1	0	0	0	4	0	0	0	0	178	0	11	1	0	583	129285	7	12	0	9	128499	25	71711	51134	10525	10000	40100	10000	10000	1147644	4887430	4939164	0	128781	0	130536	129371	122459	3	124598	60100	30200	10000	10000	60200	10000	10000	129472	129228	1	1	50201	100	99	100	40100	10000	10000	0	100	10019	8	571	10037	15	11	33	10029	1250	4	635	21	4	522	4	8	0	3211	5	76	5	4	129268	51344	6284	6161	5158	10000	50100	129514	129626	129795	129419	129679
50204	129389	968	2	1	2	0	0	0	0	1	0	0	143	0	9	1	0	542	129996	10	10	0	6	128693	25	71900	51250	10542	10000	40100	10000	10000	1147950	4901354	4947606	0	129312	0	129471	129222	122994	3	123459	60100	30200	10000	10000	60200	10000	10000	129749	129211	1	1	50201	100	99	100	40100	10000	10000	0	100	10023	3	577	10031	9	16	22	10027	1250	4	526	24	4	533	4	0	0	3211	4	76	4	4	128960	51124	5881	5789	5062	10000	50100	128995	129543	129046	128696	132023
50204	131678	990	2	8	0	0	7	0	0	0	27	28	3946	2548	7	1	0	530	131694	7	11	0	10	130609	704	72177	51439	10586	10000	40244	10000	10000	1146429	4906064	4934342	1	130044	0	130628	130977	123203	233	125527	64147	33926	11090	10948	67582	11219	11067	132209	131633	24	1	50201	100	99	100	40100	10000	10000	0	100	10062	2	542	10073	12	9	92950	10069	1254	4	511	22	4	527	3	0	0	4402	4	124	14	14	130858	51098	6233	5943	5172	10000	50100	129638	129245	128849	130794	131161
50204	130619	1020	3	12	2	0	0	3	0	2	0	0	343	0	10	1	0	517	129092	6	12	0	6	129417	25	71747	51212	10551	10000	40100	10000	10000	1137852	4846617	4911327	0	129082	0	129728	128841	121734	3	122639	60100	30200	10000	10000	60200	10000	10000	128458	129478	1	1	50201	100	99	100	40100	10000	10000	0	100	10018	4	568	10032	8	11	23	10024	1250	4	549	21	4	511	2	0	0	3211	4	91	4	4	128848	51090	5485	5254	5365	10000	50100	129223	129563	129426	128932	129279
50204	129001	966	3	0	0	3	0	3	1	0	0	0	315	0	7	0	1	516	128120	9	12	0	6	128006	25	71705	51094	10484	10000	40100	10000	10000	1142646	4868387	4928409	0	128753	0	128379	128695	121779	3	122808	60100	30200	10000	10000	60200	10000	10000	128732	128725	1	1	50201	100	99	100	40100	10000	10000	1	100	10017	4	537	10029	11	7	34	10029	1250	4	547	23	4	507	3	3	0	3211	4	76	4	4	128160	51134	5582	5584	4805	10000	50100	129151	128817	128745	129392	129334
50204	128754	964	3	0	0	3	0	0	0	0	0	0	320	0	7	0	1	536	129251	7	11	0	9	128089	25	71840	51172	10554	10000	40100	10000	10000	1139205	4869399	4951167	0	128640	0	128786	129300	121959	3	122721	60100	30200	10000	10000	60200	10000	10000	129104	127994	1	1	50201	100	99	100	40100	10000	10000	0	100	10017	3	553	10034	14	12	18	10024	1250	4	517	20	4	498	3	3	0	3211	4	76	4	4	127983	51026	5012	4741	4333	10000	50100	128270	128402	128545	128463	128546
50204	128773	965	3	1	0	0	1	0	0	0	0	0	318	0	9	0	1	665	129772	7	8	0	6	129098	25	71855	51266	10520	10000	40100	10000	10000	1137144	4882238	4918224	0	128917	0	128139	129036	122387	3	122577	60100	30200	10000	10000	60200	10000	10000	128913	128437	1	1	50201	100	99	100	40100	10000	10000	0	100	10024	2	578	10028	12	7	23	10026	1250	4	553	18	4	518	2	0	0	3211	4	76	4	4	128611	51086	5248	5100	4547	10000	50100	128186	128448	128766	128423	128336
50204	128255	962	3	0	0	3	0	3	0	0	0	0	349	0	10	0	1	506	128889	7	13	1	7	128718	25	71705	51186	10498	10000	40100	10000	10000	1138458	4859603	4911760	0	128454	0	129086	128704	122420	3	122500	60100	30200	10000	10000	60200	10000	10000	129448	128962	1	1	50201	100	99	100	40100	10000	10000	0	100	10017	2	515	10030	15	9	24	10027	1250	4	628	24	4	548	2	0	0	3211	4	76	4	4	128507	51178	5676	5180	4965	10000	50100	128988	128828	129728	128716	129258
50204	129547	963	2	0	0	0	0	2	0	0	0	0	339	0	9	0	1	551	129318	7	8	0	5	128229	25	71693	51140	10559	10000	40100	10000	10000	1143921	4893655	4932131	1	128968	0	129443	128934	121544	3	121729	60100	30200	10000	10000	60200	10000	10000	129164	129296	1	1	50201	100	99	100	40100	10000	10000	0	100	10025	6	591	10032	15	14	29	10025	1250	4	487	23	4	505	3	0	0	3211	4	76	5	4	129318	51140	5381	5843	5073	10000	50100	127801	128148	128979	128546	130791
50204	129102	969	3	0	3	0	0	0	0	0	0	0	346	0	9	0	1	511	128899	7	13	1	5	128161	25	71621	51106	10511	10002	40100	10000	10000	1140501	4857401	4932662	0	128616	0	128527	128562	122392	3	122800	60100	30200	10000	10000	60200	10000	10000	128507	128566	1	1	50202	100	99	100	40100	10000	10000	0	100	10017	9	519	10028	11	7	25	10029	1250	4	503	24	4	535	3	3	0	3211	4	76	4	4	128145	51098	5195	5958	4789	10000	50100	128599	128738	128664	129160	128183

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 9.9504

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	09	l2 tlb miss data (0b)	0e	0f	1e	1f	20	22	24	2b	3a	3f	40	43	46	49	4d	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	69	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	af	ldst x64 uop (b1)	ldst xpg uop (b2)	b5	bb	be	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	c3	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	d9	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
50029	133484	976	2	0	0	0	1	0	377	0	7	1	0	0	530	129885	6	111	0	73	128625	25	72104	51332	10601	10000	40010	10000	10000	1144894	4896121	4947376	0	129443	0	129233	128975	123283	3	122838	60010	30020	10000	10000	60020	10000	10000	129404	129061	1	1	50021	10	9	10	40010	10000	10000	0	10	10017	4	610	10130	14	7	120	10126	1250	4	639	127	4	485	2	0	0	0	0	0	3140	4	82	1	1	1	128362	51260	5031	5028	4601	10000	50010	129236	129623	129213	128999	129158
50024	129163	965	2	0	2	0	0	0	392	0	7	1	0	0	502	129314	11	115	0	60	129176	25	71957	51244	10688	10000	40010	10000	10000	1145374	4882345	4952257	0	129252	0	129900	129876	122576	3	123536	60010	30020	10000	10000	60020	10000	10000	130224	129830	1	1	50021	10	9	10	40010	10000	10000	0	10	10016	6	649	10131	31	9	143	10131	1250	4	512	119	4	533	2	0	0	0	0	0	3140	1	85	0	1	1	129469	51298	5480	5507	5151	10000	50010	129472	129372	129621	129316	129638
50024	129235	970	2	0	0	2	0	0	434	0	8	1	0	0	607	129685	7	127	0	63	130447	25	71936	51442	10651	10000	40010	10000	10000	1149694	4913476	4968172	0	130063	0	129177	128935	122374	3	123404	60010	30020	10000	10000	60020	10000	10000	129393	130638	1	1	50021	10	9	10	40010	10000	10000	0	10	10019	2	576	10132	20	9	136	10128	1250	4	520	124	4	500	2	0	0	0	0	0	3140	1	97	0	1	1	129564	51276	5295	5006	4659	10000	50010	129487	130248	131072	129787	129307
50024	129545	967	2	0	2	2	0	1	395	0	7	1	0	0	533	130238	9	118	1	78	130466	25	71951	51296	10643	10000	40010	10000	10000	1147387	4923710	4990041	0	130216	0	130226	129910	122368	3	122829	60010	30020	10000	10000	60020	10000	10000	130949	130925	1	1	50021	10	9	10	40010	10000	10000	0	10	10019	2	676	10130	15	11	127	10126	1250	4	513	119	4	553	2	4	0	0	0	0	3140	1	82	0	1	2	129177	51366	5618	5894	4911	10000	50010	129259	129790	129708	129786	129784
50024	129744	969	2	0	0	0	0	0	406	0	10	1	0	0	577	129511	6	108	0	69	129200	25	72020	51264	10616	10000	40010	10000	10000	1148629	4912900	4966760	0	129650	0	129630	129417	122662	3	122826	60010	30020	10000	10000	60020	10000	10000	129600	129474	1	1	50021	10	9	10	40010	10000	10000	0	10	10021	2	590	10143	16	9	126	10125	1250	4	500	117	4	657	2	0	0	1	0	0	3140	1	82	0	1	1	129317	51202	5062	4902	4503	10000	50010	129273	129416	129214	128900	129097
50024	129436	967	2	2	0	0	0	0	383	0	7	3	0	0	541	129930	7	117	0	77	129966	25	71861	51254	10613	10000	40010	10000	10000	1145314	4918837	4954399	0	129880	0	130394	129764	122898	3	122397	60010	30020	10000	10000	60020	10000	10000	129199	128966	1	1	50021	10	9	10	40010	10000	10000	0	10	10019	2	585	10127	16	8	127	10130	1250	4	526	129	4	501	2	0	0	0	0	0	3140	1	82	0	1	1	130171	51258	5364	5456	4925	10000	50010	129850	129105	129013	129362	130129
50024	129504	974	2	2	2	0	0	0	401	0	7	1	0	0	550	130170	9	113	0	67	129333	25	71906	51434	10655	10000	40010	10000	10000	1146430	4933505	4967057	0	129329	0	129208	129655	122493	3	122947	60010	30020	10000	10000	60020	10000	10000	129878	129709	1	1	50021	10	9	10	40010	10000	10000	0	10	10024	2	628	10130	13	9	122	10125	1250	4	487	122	4	524	2	2	0	0	0	0	3140	1	82	1	2	2	129477	51246	4985	4713	4999	10000	50010	129672	130325	130504	130225	130085
50024	129235	971	2	2	0	2	0	0	399	0	7	1	0	0	527	130028	9	112	0	77	129390	25	72023	51294	10614	10000	40010	10000	10000	1152955	4907717	4955341	0	129508	0	129694	129963	122860	3	123274	60010	30020	10048	10000	60020	10000	10000	129366	129252	1	1	50021	10	9	10	40010	10000	10000	0	10	10021	4	620	10135	12	12	127	10128	1250	4	528	119	4	568	2	4	8	0	0	0	3140	1	82	0	3	3	129467	51274	5891	5465	4907	10000	50010	129368	129712	129638	130451	130591
50024	129603	971	2	0	0	2	0	0	398	0	10	3	0	0	511	129846	8	115	0	69	128683	25	71888	51288	10608	10000	40010	10000	10000	1152292	4913083	4960079	0	129880	0	129375	129664	123355	3	123457	60010	30020	10000	10000	60020	10000	10000	129519	129235	1	1	50021	10	9	10	40010	10000	10000	0	10	10019	2	555	10130	14	9	121	10135	1250	4	515	119	4	452	2	1	0	0	0	0	3140	1	82	0	1	1	129786	51344	5149	5571	4801	10000	50010	129220	129782	129783	130140	129438
50024	129179	969	2	0	2	0	0	0	388	0	9	1	0	0	504	129496	7	117	0	74	129658	25	72122	51404	10691	10000	40010	10000	10000	1144522	4915118	4948847	0	130364	0	129475	130100	123276	3	122745	60010	30020	10000	10000	60020	10000	10000	129526	129670	1	1	50021	10	9	10	40010	10000	10000	0	10	10031	6	593	10151	12	8	123	10134	1250	4	515	121	4	544	2	0	0	0	0	0	3140	1	82	0	1	1	129957	51258	4988	5163	4993	10000	50010	130221	129058	130235	129736	129468

Test 3: throughput

Count: 8

Code:

  ldr q0, [x6, #8]!
  ldr q0, [x7, #8]!
  ldr q0, [x8, #8]!
  ldr q0, [x9, #8]!
  ldr q0, [x10, #8]!
  ldr q0, [x11, #8]!
  ldr q0, [x12, #8]!
  ldr q0, [x13, #8]!

Initialization

  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.3781

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	09	l2 tlb miss data (0b)	0e	0f	18	19	1e	1f	20	22	29	3a	3e	3f	40	43	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	67	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	92	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d cache miss st (a2)	l1d cache miss ld (a3)	a5	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ab	ac	af	ldst x64 uop (b1)	ldst xpg uop (b2)	b5	b6	bb	be	l1d cache miss ld nonspec (bf)	c2	c3	branch cond mispred nonspec (c5)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	e7	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
80209	30949	227	0	0	0	0	0	0	0	0	7569	0	857	1	624	396	100	30050	771	605	1464	1396	2916	96	160461	80325	80000	80100	80000	400766	1351748	1	44	30919	30189	30467	20086	3	20130	160100	200	80388	200	80000	30252	30300	1	1	80201	100	99	29	100	100	80000	80000	0	100	81223	434	5078	630	86087	729	11	900	70	5956	86318	10000	32	707	123	5274	32	5111	0	3	0	5287	1	72	1	1	30771	161	81325	408	395	73	80000	80100	30827	31452	31643	31435	31374
80204	31504	235	0	1	0	0	0	0	7	7	7587	264	791	1	624	396	408	31343	807	514	1494	1403	3768	269	161680	81246	81026	81388	81246	407194	1369513	0	43	31257	31313	31233	21041	150	21139	162963	202	81344	204	81342	31470	31422	8	1	80201	100	99	52	100	100	80000	80000	0	100	81831	458	4975	939	86687	715	12	921	86	11083	87246	10118	32	589	118	5374	32	4535	0	4	0	5265	1	81	1	1	31068	166	81511	367	355	76	80000	80100	31343	31696	31200	31531	31544
80204	31746	234	0	0	0	0	0	0	8	8	7787	704	771	1	600	450	180	31270	799	567	1450	1182	3697	381	161399	82160	81170	82065	81602	409910	1368934	1	52	30891	31786	31684	21037	181	21370	163720	208	81886	208	81890	31710	31835	11	1	80201	100	99	49	100	100	80000	80000	0	100	81740	435	5572	887	87267	721	6	911	134	13912	87065	10144	32	607	119	5459	32	4818	0	7	0	5269	1	105	2	1	31282	168	81882	376	414	73	80000	80100	32098	31807	31525	32241	31854
80204	32024	237	0	1	1	0	0	0	9	10	8266	704	797	1	712	437	116	31943	789	563	1563	1590	3570	415	163145	82134	80388	81924	81911	410944	1391503	1	48	31549	31893	31537	20857	188	21384	161151	202	81344	204	81148	31344	31010	8	1	80201	100	99	41	100	100	80000	80000	0	100	80928	460	5739	634	86675	794	7	912	52	5859	86810	10000	32	639	136	5705	32	5001	0	3	0	5110	1	17	1	1	30255	190	80052	444	387	67	80000	80100	30141	30204	30025	30182	30406
80204	30307	228	0	0	0	0	0	0	0	0	7031	0	808	1	568	391	220	30103	790	533	1309	1389	2789	25	160143	80146	80000	80100	80000	400742	1347219	1	45	30294	30451	30316	20128	3	20029	160100	200	80000	200	80000	30282	30310	1	1	80201	100	99	32	100	100	80000	80000	0	100	80947	447	4946	644	85696	758	10	953	70	5807	86642	10000	32	622	107	6062	32	5672	0	3	0	5110	1	17	1	1	30354	163	80044	400	348	92	80000	80100	30122	29985	30362	30203	30242
80204	30036	226	0	0	0	0	1	0	0	0	6467	0	841	1	584	412	184	30268	782	565	1353	1471	2829	45	160151	80150	80000	80100	80000	400725	1343391	0	42	30342	30269	30541	19985	3	20414	160100	200	80000	200	80000	30336	30453	1	1	80201	100	99	24	100	100	80000	80000	0	100	80948	410	5483	623	85199	771	13	923	76	5325	86665	10000	32	639	120	5302	32	4689	0	3	0	5110	1	16	1	1	30029	150	80031	377	350	79	80000	80100	30147	30266	30055	30106	30077
80204	30192	226	0	0	0	0	0	0	0	0	7003	0	815	1	520	453	188	30121	778	547	1382	1224	2759	25	160145	80144	80000	80100	80000	400711	1337941	0	45	30071	29987	30078	20243	3	20383	160100	200	80000	200	80000	30292	30313	1	1	80201	100	99	48	100	100	80000	80000	0	100	80967	422	5268	649	86053	778	8	912	48	6123	86416	10000	32	681	127	4954	32	4708	3	3	0	5110	1	17	1	1	30238	163	80046	365	361	83	80000	80100	30254	29967	30227	30282	30331
80204	30334	226	0	0	0	0	0	0	0	0	6655	0	818	1	616	415	124	30401	842	508	1345	1501	3028	25	160142	80144	80000	80100	80000	400688	1341253	0	43	30463	30610	30210	20208	3	20183	160100	200	80000	200	80000	30166	30164	1	1	80201	100	99	23	100	100	80000	80000	0	100	80950	413	4845	618	85356	786	7	875	46	5447	86465	10000	32	638	114	5569	32	4910	0	3	0	5110	1	16	1	1	30242	154	80048	422	319	75	80000	80100	30242	30437	30237	30033	30443
80204	30222	227	0	0	0	0	0	1	0	0	6868	0	819	1	288	438	152	30368	835	491	1332	1646	3036	25	160151	80136	80000	80100	80000	400756	1328661	1	39	30228	30265	30498	20259	3	20172	160100	200	80000	200	80000	30294	30477	1	1	80201	100	99	24	100	100	80000	80000	0	100	80935	496	5116	653	85205	808	10	900	52	5641	86626	10000	32	621	117	5651	32	4556	0	5	0	5110	1	17	1	1	30254	165	80044	400	434	78	80000	80100	30470	30310	30330	30258	30236
80204	30218	227	0	0	0	0	0	0	0	0	7596	0	839	1	624	493	224	30717	835	487	1339	1528	2921	25	160142	80141	80000	80100	80000	400711	1335537	0	49	30097	30444	30222	20146	3	20402	160100	200	80000	200	80000	30101	30413	1	1	80201	100	99	56	100	100	80000	80000	0	100	80936	426	5619	657	85904	722	10	917	74	5505	86664	10000	32	661	118	5839	32	5209	0	3	0	5110	1	17	1	1	30279	171	80049	377	407	71	80000	80100	30333	30184	30313	30326	30305

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.3787

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	l2 tlb miss data (0b)	0e	0f	1e	20	22	29	3a	3e	3f	40	43	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	5f	60	67	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	92	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst ldst (9b)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	l1d cache miss ld (a3)	a5	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ab	ac	af	ldst x64 uop (b1)	ldst xpg uop (b2)	b5	b6	bb	be	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	c3	cf	d0	d2	l1i cache miss demand (d3)	d5	map dispatch bubble (d6)	d9	da	db	dd	fetch restart (de)	df	e0	e7	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
80029	30772	228	1	0	0	0	1	7105	791	1	656	450	100	30515	790	462	1366	1511	3194	25	160052	80071	80000	80010	80000	400240	1338692	0	1	35	30038	30304	30175	20047	3	20311	160010	20	80000	20	80000	30590	30680	1	1	80021	10	9	85	10	10	80000	80000	10	80945	0	452	5068	616	85477	751	14	928	44	5222	86599	10000	32	585	134	6008	32	4456	18	1	5	5024	0	0	0	3	16	0	0	0	2	3	4	30504	166	80244	420	411	86	80000	80010	30332	30280	30267	30557	30355
80024	30342	228	2	0	0	1	0	7556	786	1	632	390	200	30206	788	551	1650	1459	3030	25	160058	80053	80000	80010	80000	400315	1335874	0	1	36	30224	30185	30296	20145	3	20382	160010	20	80000	20	80000	30212	30291	1	1	80021	10	9	44	10	10	80000	80000	10	80998	31	476	5102	590	85565	732	9	902	24	5419	86434	10000	32	597	117	5648	32	4609	37	15	5	5024	3	0	0	3	16	0	0	0	3	3	5	30392	161	80036	329	386	83	80000	80010	30110	30251	30554	30185	30347
80024	30397	225	1	0	1	1	0	7273	845	1	776	408	224	29940	801	521	1424	1473	2846	25	160053	80044	80000	80010	80000	400255	1337277	0	0	43	30299	30365	30512	20386	3	20290	160010	20	80000	20	80000	30305	30387	1	1	80021	10	9	34	10	10	80000	80000	10	80971	0	401	5720	628	86080	747	9	876	36	5791	86698	10000	32	658	113	6119	32	5320	0	0	5	5024	0	0	0	4	16	0	0	0	2	3	4	30364	182	80049	379	350	88	80000	80010	30252	30288	30053	30227	30285
80024	30160	227	0	0	0	1	0	7392	819	1	784	440	192	30205	839	543	1429	1393	2819	25	160054	80053	80000	80010	80000	400306	1345581	1	1	35	30260	30311	30152	20066	3	20204	160010	20	80000	20	80000	30245	30350	1	1	80021	10	9	21	10	10	80000	80000	10	80928	0	388	4971	647	85570	766	13	913	36	6450	87003	10000	32	631	133	5745	32	5380	0	0	9	5024	0	0	0	3	16	0	0	0	2	3	4	30363	170	80044	345	338	84	80000	80010	30039	30350	30152	30316	30201
80024	30166	228	0	0	0	0	0	7440	820	1	680	379	112	30442	811	628	1551	1463	3068	25	160058	80057	80130	80010	80000	400245	1329377	1	1	40	30254	30389	30197	20313	3	20117	160010	20	80000	20	80000	30646	30352	1	1	80021	10	9	57	10	10	80000	80000	10	80938	0	402	5166	622	86136	742	9	879	48	5650	86718	10000	32	617	116	5961	32	5079	0	0	3	5024	0	0	0	3	16	0	0	0	2	3	4	30515	150	80037	378	377	82	80000	80010	30292	30231	30240	30290	30594
80024	30351	229	0	0	0	0	0	7408	787	1	488	431	116	30145	781	514	1596	1590	2968	25	160047	80046	80000	80010	80000	400293	1328970	0	1	38	30070	30158	30377	20113	3	20158	160010	20	80000	20	80000	30550	30108	1	1	80021	10	9	65	10	10	80000	80000	10	80969	0	430	5343	629	84833	734	7	885	42	5213	86031	10000	32	699	126	5230	32	5209	0	0	7	5024	0	0	0	3	16	0	0	0	3	3	5	30334	160	80034	458	392	94	80000	80010	30100	30183	30372	30061	30178
80024	30049	226	0	0	0	0	0	7658	813	1	624	399	228	30291	815	562	1326	1543	3052	25	160054	80049	80000	80010	80000	400276	1344611	0	1	42	30013	30126	30437	20588	3	20174	160010	20	80000	20	80000	30464	30389	1	1	80021	10	9	40	10	10	80000	80000	10	80964	13	438	5104	608	85230	702	14	882	76	5213	86513	10000	32	599	109	5189	32	4887	16	0	10	5025	0	0	0	3	16	0	0	0	3	3	4	30180	176	80037	301	339	75	80000	80010	30071	30300	30513	30279	30192
80024	30286	227	1	0	0	0	0	7047	851	1	624	405	204	29872	794	463	1511	1611	3012	25	160051	80055	80000	80010	80000	400238	1329217	0	1	49	30425	30603	30332	20161	3	20284	160010	20	80000	20	80000	30290	30351	1	1	80021	10	9	44	10	10	80000	80000	10	80993	15	447	5268	602	85745	784	5	905	28	6052	85828	10000	32	603	116	5661	32	5079	0	6	6	5024	0	0	0	2	16	0	0	0	2	3	4	30387	200	80034	383	354	79	80000	80010	30110	30290	29877	30350	30242
80024	30173	227	1	1	0	0	0	7600	843	1	264	439	96	30268	805	530	1321	1462	2900	25	160058	80044	80000	80010	80000	400274	1318465	0	1	43	30388	30312	30333	20281	3	20548	160010	20	80000	20	80000	30458	30132	1	1	80021	10	9	73	10	10	80000	80000	10	80966	18	425	5311	653	85539	758	9	885	38	5217	86688	10000	32	658	130	6030	32	4751	16	0	5	5024	0	0	0	3	16	0	0	0	3	2	4	30153	180	80048	367	343	104	80000	80010	30233	30388	30027	30224	30420
80024	30196	225	1	0	1	0	0	6973	813	1	616	456	172	30162	796	521	1433	1480	2894	25	160048	80058	80130	80010	80000	400290	1342102	0	1	42	30078	30273	30208	20329	3	20132	160010	20	80000	20	80000	30354	30246	1	1	80021	10	9	40	10	10	80000	80000	10	81009	18	421	5271	632	85475	757	10	860	40	5523	86084	10000	32	647	119	5202	32	4745	18	1	0	5024	3	0	0	2	16	0	0	0	3	2	4	30152	159	80037	388	357	66	80000	80010	30302	30504	30303	30163	30379

LDR (pre-index, Q)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->2 roundtrip

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations