Firestorm: LDR (pre-index, S) measurements

Code:

  ldr s0, [x6, #8]!

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 2.000

Integer unit issues: 1.000

Load/store unit issues: 1.000

SIMD/FP unit issues: 0.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	09	l2 tlb miss data (0b)	0e	0f	1e	20	22	29	2b	3a	3e	3f	40	43	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map ldst uop (7d)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst simd load (98)	inst ldst (9b)	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	l1d cache miss ld (a3)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	aa	ab	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	c3	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
1005	1052	7	0	0	0	0	1	1	93	0	1	0	0	4	0	1025	16	3	11	15	23	25	2000	1000	1000	1000	1000	50730	45824	1	1015	1040	1040	824	3	913	2000	1000	1000	1040	1040	1	1	1001	1000	1000	1026	0	2	75	1026	14	1	12	0	10	30	1038	51	9	23	79	0	0	0	73	2	16	2	2	1037	1000	33	21	0	1000	1000	1041	1041	1041	1041	1041
1004	1040	8	0	0	0	1	0	0	72	36	1	0	0	5	0	1025	6	5	7	9	12	45	2000	1000	1000	1000	1000	49210	45824	0	1015	1040	1040	824	3	898	2000	1000	1000	1040	1040	1	1	1001	1000	1000	1025	0	2	51	1028	5	1	26	0	22	13	1023	40	3	15	63	0	0	0	73	2	16	2	2	1038	1000	21	33	0	1000	1000	1041	1041	1041	1041	1041
1004	1040	8	0	1	0	0	0	1	57	26	1	0	0	2	0	1025	6	5	14	14	19	25	2000	1000	1000	1000	1000	50754	45824	1	1015	1040	1040	824	3	898	2000	1000	1000	1040	1040	1	1	1001	1000	1000	1043	7	2	48	1040	9	1	12	0	0	33	1028	30	4	17	39	7	4	0	73	2	16	2	2	1037	1000	24	25	0	1000	1000	1041	1041	1041	1041	1041
1004	1040	7	1	1	1	1	0	0	71	6	1	0	0	2	20	1025	9	3	12	9	18	25	2000	1000	1000	1000	1000	50754	45824	1	1015	1040	1040	824	3	898	2000	1000	1000	1040	1040	1	1	1001	1000	1000	1029	12	1	68	1047	7	1	10	0	0	29	1020	30	4	25	71	0	0	0	73	2	16	2	2	1037	1000	21	28	0	1000	1000	1041	1041	1041	1041	1041
1004	1040	8	0	0	0	0	0	0	52	6	1	0	0	3	0	1025	0	3	7	11	19	25	2000	1000	1000	1000	1000	50746	45824	1	1015	1040	1040	824	3	898	2000	1000	1000	1055	1040	1	1	1001	1000	1000	1000	0	0	55	1035	9	1	0	0	0	22	1019	33	2	18	47	0	0	0	73	2	16	2	2	1037	1000	24	22	0	1000	1000	1054	1056	1041	1041	1041
1004	1040	7	1	0	0	1	0	0	58	0	1	0	0	3	0	1025	8	4	11	5	22	25	2000	1000	1000	1000	1000	50738	45825	1	1015	1040	1040	824	3	910	2000	1000	1000	1040	1040	1	1	1001	1000	1000	1017	0	0	31	1033	3	1	13	0	6	24	1015	29	4	17	40	0	0	0	73	2	16	2	2	1037	1000	21	19	0	1000	1000	1041	1041	1041	1041	1041
1004	1040	7	0	0	0	0	0	0	52	0	1	0	0	2	0	1040	20	4	8	5	21	25	2000	1000	1000	1000	1000	50738	45824	0	1015	1040	1040	824	3	898	2000	1000	1000	1040	1040	1	1	1001	1000	1000	1026	19	0	55	1037	9	1	1	0	0	22	1023	34	3	25	39	7	1	0	73	2	16	2	2	1038	1000	24	29	0	1000	1000	1041	1041	1041	1041	1041
1004	1040	8	1	1	0	1	0	0	58	26	1	0	0	4	0	1025	10	5	5	6	19	25	2000	1000	1000	1000	1000	50714	45824	1	1021	1040	1055	824	3	910	2000	1000	1000	1040	1040	1	1	1001	1000	1000	1022	7	2	48	1029	2	1	18	0	12	21	1030	36	5	29	47	7	0	3	73	2	16	2	2	1037	1000	24	22	0	1000	1000	1041	1041	1041	1041	1041
1004	1040	8	1	0	1	1	0	0	55	21	1	0	0	3	0	1025	0	1	10	7	23	25	2000	1000	1000	1000	1000	50746	45825	1	1015	1040	1040	824	3	913	2000	1000	1000	1040	1040	1	1	1001	1000	1000	1006	8	0	47	1034	0	0	1	0	0	27	1020	28	3	23	47	6	1	0	73	2	16	2	2	1037	1000	24	22	0	1000	1000	1041	1041	1041	1041	1041
1004	1040	8	1	1	1	1	0	1	73	15	1	0	0	3	0	1025	11	2	9	10	13	25	2000	1000	1000	1000	1000	50706	45824	0	1015	1040	1040	824	3	898	2000	1000	1000	1040	1040	1	1	1001	1000	1000	1030	8	3	80	1044	4	1	17	0	8	29	1040	41	4	26	55	6	0	0	73	2	16	2	2	1037	1000	29	27	0	1000	1000	1041	1041	1041	1041	1041

Test 2: Latency 1->2 roundtrip

Chain cycles: 3

Code:

  ldr s0, [x6, #8]!
  fmov x0, d0
  eor x8, x8, x0
  eor x8, x8, x0
  add x6, x6, x8

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 9.1888

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1i tlb fill (04)	l1d tlb fill (05)	09	l2 tlb miss data (0b)	0e	0f	18	19	1e	1f	20	22	23	24	29	3a	3e	3f	40	43	49	4d	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst ldst (9b)	9d	9e	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	l1d cache miss ld (a3)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ab	ac	af	b5	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	c3	branch mispred nonspec (cb)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
50209	121883	912	0	0	0	0	0	0	0	0	603	0	842	1	0	0	784	2	108	121689	792	2	1	121365	25	70469	50350	10117	10000	40100	10000	10000	1076841	4609072	4642614	0	121633	121688	121632	114965	3	115375	60100	30200	10000	10000	60200	10000	10000	121824	121692	1	1	50201	100	99	100	40100	10000	10000	0	0	100	10904	0	132	553	10681	217	13	911	72	29	10915	137	2	129	0	3	5	0	3213	7	76	9	8	121362	50260	862	908	776	10000	50100	121640	122121	121840	121763	121728
50204	121783	912	0	0	0	0	0	0	0	1	599	0	853	1	0	0	736	1	100	121692	820	2	1	121462	25	70457	50344	10123	10000	40100	10000	10046	1077939	4598704	4652878	0	121504	121757	121748	114897	3	115325	60100	30200	10000	10000	60200	10000	10000	121846	121769	1	1	50201	100	99	100	40100	10000	10000	0	0	100	10916	1	131	527	10724	214	14	938	72	30	10915	130	3	128	1	1	5	0	3213	7	76	6	8	121490	50276	926	940	763	10000	50100	121711	121580	122110	121744	121678
50204	121782	910	1	1	0	0	0	0	0	0	570	0	823	1	0	0	736	2	140	121699	776	2	1	121516	25	70514	50376	10135	10000	40100	10000	10000	1076670	4602753	4654528	0	121626	121530	121737	115005	3	115389	60100	30200	10000	10000	60200	10000	10000	121398	121697	1	1	50201	100	99	100	40100	10000	10000	0	0	100	10919	1	138	534	10707	208	12	900	72	30	10914	125	2	113	1	1	9	0	3213	8	76	9	8	121481	50240	858	890	775	10000	50100	121742	121796	121793	121944	121769
50204	121842	911	0	1	0	0	0	0	0	0	606	0	826	1	0	0	704	2	112	121625	794	2	1	121830	25	70463	50326	10139	10000	40100	10000	10000	1077012	4602388	4652180	0	121683	121719	121790	114929	3	115425	60100	30200	10000	10000	60200	10000	10000	121860	121675	1	1	50201	100	99	100	40100	10000	10000	0	0	100	10910	1	142	512	10687	214	10	929	50	36	10929	125	2	121	1	12	5	0	3213	6	76	6	8	121252	50264	950	860	842	10000	50100	121687	121703	121828	121841	121659
50204	121801	911	0	0	0	0	0	0	0	0	572	0	822	1	0	0	736	3	108	121623	807	1	1	121593	25	70472	50364	10133	10000	40100	10000	10000	1076445	4604718	4644276	0	121807	121544	121682	115114	3	115177	60100	30200	10000	10000	60200	10000	10000	121725	121649	1	1	50201	100	99	100	40100	10000	10000	0	0	100	10910	0	145	573	10723	212	11	899	72	40	10922	121	1	131	0	3	4	0	3215	8	76	8	8	121362	50264	920	940	794	10000	50100	121836	121532	121758	121908	121779
50204	121779	911	0	0	0	0	0	0	1	0	581	0	817	1	0	0	720	1	144	121508	799	1	1	121436	25	70472	50362	10114	10000	40100	10160	10000	1075482	4599836	4649301	0	121864	121754	121747	114840	3	115269	60100	30200	10000	10000	60200	10000	10000	121741	121641	1	1	50201	100	99	100	40100	10000	10000	1	0	100	10933	0	137	517	10696	217	15	927	34	32	10947	134	1	129	0	3	11	0	3213	8	76	8	7	121334	50256	954	900	839	10000	50100	121630	121743	121870	121647	121887
50204	121974	911	0	0	0	0	0	0	0	0	563	0	823	1	0	0	696	1	128	121739	799	2	1	121507	25	70502	50368	10132	10000	40100	10000	10000	1078452	4603716	4651309	0	121554	121742	121684	115216	214	116840	66099	33540	11097	11160	66798	11098	11155	124131	124131	28	1	50201	100	99	100	40100	10000	10000	0	0	100	10929	0	133	540	10694	214	12	955	30	79359	10889	122	1	122	0	3	11	0	3213	8	76	7	8	121498	50504	960	932	808	10000	50100	123881	124028	124300	124361	124436
50204	124153	931	2	0	0	0	0	0	28	29	3459	2640	796	1	0	0	768	3	136	121974	792	1	1	121610	390	70872	50606	10177	10062	44518	11227	11174	1147144	4663395	4713884	0	121607	121768	121768	114896	3	115426	60100	30325	10000	10000	60200	10000	10000	121592	121745	2	1	50201	100	99	100	40100	10000	10000	0	0	100	10949	3	131	566	10753	215	11	922	32	33	10923	130	2	124	1	6	7	0	3213	6	76	7	9	121457	50240	1093	1164	1002	10000	50100	121994	122097	121997	121900	121941
50204	121930	914	0	1	1	0	0	0	0	0	471	0	824	0	0	1	704	2	160	121940	801	1	1	121435	25	70526	50358	10132	10000	40100	10000	10000	1079010	4602148	4657458	1	121957	121851	121857	115013	3	115720	60100	30200	10000	10000	60200	10000	10000	121951	122001	1	1	50201	100	99	100	40100	10000	10000	0	0	100	10925	1	137	521	10688	219	11	922	34	42	10963	132	3	118	1	9	11	0	3213	7	76	8	8	121648	50260	1095	1056	936	10000	50100	121888	121914	121958	121994	121926
50204	121828	913	0	1	0	0	0	0	0	0	413	0	832	0	0	1	776	3	148	121999	823	2	1	121572	25	70484	50374	10136	10000	40100	10000	10000	1078848	4609828	4656607	1	121758	122027	122023	115241	3	115729	60100	30200	10000	10000	60200	10000	10000	121990	121868	2	1	50201	100	99	100	40100	10000	10000	1	0	100	10908	1	124	531	10725	211	14	952	38	30	10947	119	3	131	1	1	5	0	3213	5	76	7	9	121664	50278	1013	1062	938	10000	50100	121852	121993	122064	121867	121754

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 9.1921

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	l2 tlb miss data (0b)	0f	18	19	1e	1f	20	22	29	3a	3e	3f	40	43	49	4d	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	l1d cache miss ld (a3)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ab	ac	af	b5	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	c3	branch cond mispred nonspec (c5)	cf	d2	d5	map dispatch bubble (d6)	da	db	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
50029	122068	914	0	0	0	0	0	0	421	0	845	1	752	0	140	121906	785	1	0	121484	25	70421	50272	10132	10000	40010	10000	10000	1079905	4615042	4658281	0	121836	121922	121864	115152	3	115653	60010	30020	10000	10000	60020	10000	10000	121905	121790	1	1	50021	10	9	10	40010	10000	10000	0	10	10894	1	104	508	10782	204	12	926	48	11	10945	135	2	114	1	2	5	0	3140	0	4	82	0	0	2	4	121569	50260	1153	1066	981	10000	50010	121789	121956	121751	121937	121925
50024	121999	913	1	0	0	0	0	0	397	0	829	1	728	0	128	121999	809	2	0	121647	35	70430	50274	10126	10000	40010	10000	10000	1078663	4606121	4662617	0	121882	121836	121915	115198	3	115617	60010	30020	10000	10000	60020	10000	10000	121923	121911	1	1	50021	10	9	10	40010	10000	10000	0	10	10913	0	114	556	10766	216	14	920	44	26	10902	128	2	138	0	15	10	0	3140	0	4	82	0	0	4	2	121660	50266	1049	1173	976	10000	50010	122095	122123	121789	121974	121936
50024	121823	912	0	0	0	0	0	0	424	0	809	1	736	0	144	122080	791	2	0	121684	25	70379	50282	10135	10000	40010	10000	10000	1078240	4610327	4656360	0	121783	121866	122084	115013	3	115629	60010	30020	10000	10000	60020	10000	10000	121963	121780	1	1	50021	10	9	10	40010	10000	10000	0	10	10873	0	104	529	10753	194	20	959	48	15	10942	125	1	137	0	3	9	0	3140	0	2	82	0	0	4	2	121568	50256	1125	1131	1066	10000	50010	121935	122110	121826	122113	121940
50024	122084	913	0	0	0	0	0	0	418	0	829	1	704	0	96	121869	816	2	0	121707	25	70394	50290	10129	10000	40010	10000	10000	1080328	4610491	4661611	0	121830	121708	121994	115201	3	115631	60010	30020	10000	10000	60020	10000	10000	121912	121907	1	1	50021	10	9	10	40010	10000	10000	0	10	10919	1	105	535	10759	213	10	931	38	17	10969	133	2	137	0	0	7	0	3140	0	2	82	0	0	5	3	121622	50272	1106	1212	926	10000	50010	122020	121897	121871	121965	122346
50024	121805	914	0	0	0	0	0	0	415	0	819	1	720	0	128	121964	789	1	1	121801	25	70403	50306	10126	10000	40010	10000	10000	1078681	4611114	4666329	0	121751	121946	121648	115164	3	115338	60010	30020	10000	10000	60020	10000	10000	121954	121942	1	1	50021	10	9	10	40010	10000	10000	0	10	10892	1	109	523	10759	212	12	940	42	21	10924	125	2	128	1	3	10	0	3140	0	6	82	0	0	5	3	121672	50304	1170	1199	915	10000	50010	121769	121958	122132	121882	122115
50024	121772	914	0	0	0	0	0	0	400	0	805	2	640	0	124	121803	828	1	1	121522	25	70412	50286	10134	10000	40010	10000	10000	1079275	4609269	4661706	0	121998	121882	122015	115180	3	115566	60010	30020	10000	10000	60020	10000	10000	121999	121928	1	1	50021	10	9	10	40010	10000	10000	0	10	10904	0	113	532	10745	203	10	873	30	25	10937	135	1	144	0	0	8	0	3140	0	2	82	0	1	4	6	121739	50272	1060	1119	965	10000	50010	122013	122016	121816	121951	121940
50024	121820	913	0	0	0	0	0	0	433	0	852	1	752	0	112	122036	807	2	0	121502	25	70388	50270	10139	10000	40010	10000	10000	1079077	4605437	4662516	0	121990	122070	121881	115294	3	115554	60010	30020	10000	10000	60020	10000	10000	121824	121854	1	1	50021	10	9	10	40010	10000	10000	0	10	10928	0	105	537	10741	216	10	943	72	16	10927	131	2	132	0	0	8	0	3140	0	3	82	0	0	5	2	121898	50268	1157	1116	923	10000	50010	122191	122000	121985	121867	122055
50024	121838	912	0	0	0	0	0	0	453	0	837	1	720	0	104	122062	844	2	0	121554	25	70451	50262	10130	10000	40010	10000	10000	1078582	4610357	4665641	0	121861	121790	122045	115116	3	115627	60010	30020	10000	10000	60020	10000	10000	121874	122218	1	1	50021	10	9	10	40010	10000	10000	1	10	10973	1	114	540	10773	218	23	885	48	25	10904	120	2	130	0	3	7	0	3140	0	4	82	0	0	3	5	121731	50266	1170	989	1040	10000	50010	121909	122055	121902	121839	122032
50024	121949	914	0	0	0	0	0	0	410	0	848	1	760	0	84	122012	811	1	0	121671	25	70415	50306	10132	10000	40010	10000	10000	1078987	4607841	4660443	0	121905	121982	121911	115253	3	115624	60010	30020	10000	10000	60020	10000	10000	121968	122022	1	1	50021	10	9	10	40010	10000	10000	0	10	10915	0	124	535	10798	208	11	886	32	19	10896	142	2	119	0	3	11	0	3140	0	4	82	0	0	6	3	121621	50242	1090	982	915	10000	50010	121763	121997	121904	121916	122387
50024	122024	913	0	0	0	0	0	0	447	0	808	1	712	1	120	122056	811	1	0	121552	25	70418	50268	10127	10000	40010	10000	10000	1080580	4609196	4651543	0	121689	121958	121896	115152	3	115603	60010	30020	10000	10000	60020	10000	10000	121928	121884	1	1	50021	10	9	10	40010	10000	10000	0	10	10893	0	111	533	10759	204	13	896	74	25	10928	127	2	132	0	3	5	0	3140	0	2	82	0	0	2	4	121632	50244	1021	1082	893	10000	50010	121936	121976	121971	122018	122160

Test 3: throughput

Count: 8

Code:

  ldr s0, [x6, #8]!
  ldr s0, [x7, #8]!
  ldr s0, [x8, #8]!
  ldr s0, [x9, #8]!
  ldr s0, [x10, #8]!
  ldr s0, [x11, #8]!
  ldr s0, [x12, #8]!
  ldr s0, [x13, #8]!

Initialization

  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.3676

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	09	l2 tlb miss data (0b)	0e	18	19	1e	1f	20	22	29	3a	3e	3f	40	43	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	67	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	92	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	l1d cache miss ld (a3)	a5	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ab	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	c3	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	e7	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
80209	29686	220	2	0	0	0	0	0	0	7043	0	788	1	704	111	204	29376	773	530	1968	1838	2195	25	160147	80151	80000	80100	80000	400742	1298926	48	29500	29279	29332	19334	3	19505	160100	200	80000	200	80000	29215	29494	1	1	80201	100	99	33	100	100	80000	80000	0	100	80885	19	387	5537	0	85206	643	18	869	56	5007	86013	693	110	5498	5450	19	2	6	5110	1	17	1	1	29423	22	80043	515	524	116	80000	80100	29340	29293	29183	29202	29407
80204	29365	219	1	0	0	0	0	0	0	7128	0	767	1	696	110	188	29421	824	439	2130	2125	2276	25	160142	80149	80000	80100	80000	400749	1300728	42	29285	29589	29421	19401	3	19394	160100	200	80000	200	80000	29409	29544	1	1	80201	100	99	25	100	100	80000	80000	0	100	80889	19	411	6067	0	85169	652	12	870	38	5229	86014	794	114	5024	4519	19	0	5	5110	1	16	1	1	29594	28	80047	604	528	104	80000	80100	29409	29181	29340	29421	29315
80204	29341	220	1	0	1	0	0	0	0	6915	0	777	1	624	108	108	29475	770	462	1751	1591	2225	25	160475	80155	80000	80100	80000	400764	1288168	37	29720	29401	29524	19348	3	19444	160100	200	80000	200	80000	29411	29493	1	1	80201	100	99	30	100	100	80000	80000	0	100	80927	19	376	5894	0	85641	635	15	834	102	4836	85737	766	133	5399	4988	19	0	3	5110	1	16	1	1	29419	27	80050	510	509	116	80000	80100	29472	29239	29343	29381	29256
80204	29448	221	1	0	1	1	0	0	0	6895	0	791	1	552	105	100	29249	798	495	1712	1759	2002	25	160145	80153	80000	80100	80000	400790	1292021	48	29523	29230	29298	19307	3	19403	160100	200	80000	200	80000	29603	29338	1	1	80201	100	99	18	100	100	80000	80000	0	100	80910	19	371	5661	0	85067	641	14	853	204	5026	85539	730	120	5250	5460	19	0	9	5110	1	16	1	1	29563	22	80048	550	541	115	80000	80100	29462	29288	29478	29328	29579
80204	29394	218	1	0	0	0	0	0	0	7176	0	764	1	728	114	308	29360	789	447	1781	1742	2161	25	160150	80142	80000	80100	80000	400740	1302765	37	29334	29154	29561	19115	3	19433	160100	200	80000	200	80000	29404	29305	1	1	80201	100	99	24	100	100	80000	80000	0	100	80879	20	377	5162	0	85639	646	14	854	38	5632	86295	815	123	5176	4829	19	4	5	5110	1	17	1	1	29473	31	80053	481	580	117	80000	80100	29576	29262	29343	29197	29544
80204	29407	220	1	0	0	0	0	1	1	7074	0	770	1	600	105	112	29396	802	457	1786	1867	2068	25	160143	80157	80000	80100	80000	400818	1295049	58	29525	29412	29442	19271	3	19502	160100	200	80000	200	80000	29637	29338	1	1	80201	100	99	28	100	100	80000	80000	0	100	80902	37	396	5654	0	85276	655	13	851	52	5702	85942	773	139	5208	5603	37	0	4	5110	1	16	1	1	29147	19	80054	550	523	110	80000	80100	29486	29600	29636	29435	29177
80204	29643	220	2	2	2	2	1	0	0	6904	0	750	1	752	104	96	29444	823	513	1984	1975	2090	25	160156	80152	80000	80100	80000	400765	1304121	45	29517	29332	29344	19335	3	19224	160100	200	80000	200	80000	29391	29375	1	1	80201	100	99	35	100	100	80000	80000	0	100	80900	37	346	5745	0	85534	620	13	851	54	5283	85972	693	119	5190	4420	37	2	5	5110	1	17	1	1	29447	35	80055	519	545	127	80000	80100	29197	29490	29467	29328	29331
80204	29563	221	2	0	0	0	0	0	0	6834	0	787	1	728	105	116	29420	775	591	1783	1734	1958	25	160161	80152	80000	80100	80000	400834	1303531	46	29472	29243	29421	19515	3	19312	160100	200	80000	200	80000	29432	29189	1	1	80201	100	99	28	100	100	80000	80000	0	100	80876	37	386	5636	0	85303	680	15	863	36	5475	85657	726	122	5724	5047	37	3	0	5110	1	17	1	1	29444	34	80046	517	584	112	80000	80100	29418	29371	29536	29517	29410
80204	29304	219	2	0	2	0	0	0	0	7123	0	869	1	696	100	228	29450	803	426	1758	1900	2076	25	160154	80152	80000	80100	80000	400763	1292429	47	29579	29318	29435	19146	3	19272	160100	200	80000	200	80000	29377	29573	1	1	80201	100	99	32	100	100	80000	80000	0	100	80928	38	348	5489	0	85233	639	13	881	134	4987	85923	730	126	5126	5326	35	3	9	5110	1	16	1	1	29320	29	80050	573	604	123	80000	80100	29442	29223	29459	29468	29338
80204	29486	221	2	1	0	0	0	0	0	6936	0	779	1	600	100	116	29427	758	456	1660	1840	2017	25	160140	80142	80000	80100	80000	400764	1296804	55	29491	29531	29419	19323	3	19254	160100	200	80000	200	80000	29352	29352	1	1	80201	100	99	26	100	100	80000	80000	0	100	80877	36	353	5642	0	85335	661	15	880	40	5085	85962	846	125	4665	4733	36	0	3	5110	1	17	1	1	29476	29	80054	608	499	120	80000	80100	29480	29430	29252	29388	29437

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.3674

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk instruction (07)	l2 tlb miss instruction (0a)	0e	18	1e	1f	20	22	29	3a	3e	3f	40	43	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	61	67	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	92	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d cache miss st (a2)	l1d cache miss ld (a3)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ab	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	c2	c3	cf	d0	d2	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	e7	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
80029	29878	220	0	0	0	0	7145	0	844	1	712	113	136	29533	824	355	1848	1759	2174	25	160053	80062	80000	80010	80000	400240	1297695	1	0	46	29450	29469	29498	19530	3	19596	160010	20	80000	20	80000	29540	29350	1	1	80021	10	9	50	10	10	80000	80000	1	10	80963	403	5953	85241	684	11	968	62	4998	86111	725	135	4893	5240	0	3	5020	0	0	4	16	2	4	29592	23	80049	581	576	89	80000	80010	29485	29461	29378	29472	29372
80024	29368	221	0	0	0	0	6772	0	834	1	680	120	116	29628	806	357	1835	1724	2199	25	160050	80053	80000	80010	80000	400264	1304498	1	0	54	29657	29405	29451	19200	3	19474	160010	20	80000	20	80000	29278	29367	1	1	80021	10	9	52	10	10	80000	80000	0	10	80957	376	6060	85103	663	9	943	72	5028	86300	784	136	4720	5529	0	0	5020	0	0	2	16	4	4	29486	38	80036	584	576	98	80000	80010	29266	29353	29328	29113	29387
80024	29637	221	0	0	0	0	7036	0	830	1	728	135	96	29459	787	328	1810	1737	2164	25	160054	80061	80000	80010	80000	400275	1299432	1	5	50	29484	29423	29544	19491	3	19345	160010	20	80000	20	80000	29483	29574	1	1	80021	10	9	57	10	10	80000	80000	0	10	80883	385	5555	85515	672	9	935	70	5289	86322	777	130	4929	5871	0	2	5020	5	0	4	16	2	4	29475	26	80043	631	547	93	80000	80010	29444	29326	29412	29513	29338
80024	29597	221	0	0	0	0	6879	0	838	1	728	97	148	29212	827	349	1889	1986	2320	25	160060	80049	80000	80010	80000	400289	1286429	1	5	55	29464	29538	29459	19250	3	19567	160010	20	80000	20	80000	29581	29512	1	1	80021	10	9	58	10	10	80000	80000	0	10	80906	369	5312	85062	686	11	947	44	4575	85886	835	125	4778	5385	3	2	5020	5	0	4	16	4	4	29866	31	80046	637	576	94	80000	80010	29377	29586	29334	29495	29674
80024	29471	221	0	0	0	0	6557	88	831	1	816	120	128	29544	840	360	1922	1577	2283	25	160054	80044	80000	80010	80178	400335	1302972	0	5	42	29394	29378	29592	19424	3	19104	160010	20	80384	20	80000	29337	29631	1	1	80021	10	9	57	10	10	80000	80000	0	10	80955	386	5646	85071	692	10	941	72	5396	85745	806	126	4687	5981	0	0	5020	0	1	2	16	2	4	29519	43	80050	569	547	102	80000	80010	29526	29679	29314	29524	29635
80024	29307	220	0	0	0	2	6750	0	829	1	688	111	124	29486	801	347	1827	1806	1946	25	160050	80048	80000	80010	80000	400272	1298395	1	0	42	29241	29212	29465	19457	3	19441	160010	20	80000	20	80000	29404	29315	1	1	80021	10	9	47	10	10	80000	80000	0	10	80924	428	5287	85309	684	14	915	60	5493	86254	741	131	4462	5681	3	1	5020	0	4	4	16	7	3	29523	44	80043	651	607	104	80000	80010	29532	29535	29701	29581	29338
80024	29626	221	0	0	0	0	7485	0	854	1	720	115	128	29520	831	342	1732	1626	1991	25	160069	80057	80000	80010	80000	400286	1296929	1	10	42	29279	29284	29508	19393	3	19302	160010	20	80000	20	80000	29447	29425	1	1	80021	10	9	34	10	10	80000	80000	0	10	80943	407	5715	85431	713	11	927	62	5164	86113	840	135	4797	5556	0	6	5020	10	4	2	16	4	4	29393	24	80040	624	503	88	80000	80010	29476	29397	29398	29378	29399
80024	29358	221	0	0	0	0	6577	0	831	1	720	121	140	29381	810	312	1830	1779	2097	25	160049	80051	80000	80010	80000	400290	1299505	1	0	51	29372	29355	29176	19282	3	19485	160010	20	80000	20	80000	29303	29307	1	1	80021	10	9	60	10	10	80000	80000	0	10	80927	404	5640	85660	681	13	945	44	5073	86345	747	127	5158	5317	0	3	5020	0	0	2	16	2	4	29120	22	80043	554	548	94	80000	80010	29361	29322	29493	29357	29246
80024	29457	219	0	0	0	0	6948	0	859	1	776	128	116	29406	788	303	1976	1829	2148	25	160059	80052	80000	80010	80000	400246	1285739	1	10	40	29622	29647	29155	19428	3	19406	160010	20	80000	20	80000	29589	29384	1	1	80021	10	9	58	10	10	80000	80000	0	10	80954	385	5318	85207	719	19	928	42	5119	85914	850	143	4918	5541	0	0	5043	0	5	7	16	5	6	29603	34	80041	542	576	111	80000	80010	29475	29385	29371	29503	29443
80024	29307	220	0	0	1	0	6307	0	861	1	720	118	140	29479	837	337	1635	1868	2167	60	160060	80061	80260	80194	80000	400285	1301996	0	0	35	29360	29334	29500	19505	3	19461	160010	20	80000	20	80192	29332	29477	1	1	80021	10	9	44	10	10	80000	80000	0	10	80929	373	5625	84781	672	9	937	44	5136	86044	819	128	4710	5402	0	0	5020	0	0	4	16	4	2	29210	31	80035	593	549	97	80000	80010	29408	29527	29464	29384	29465

LDR (pre-index, S)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->2 roundtrip

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations