Firestorm: LDR (register, D) measurements

Code:

  ldr d0, [x6, x7]

Initialization

  mov x7, #4
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 1.000

SIMD/FP unit issues: 0.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	09	0e	0f	1e	22	24	3a	3f	43	46	49	4f	51	schedule uop (52)	schedule ldst uop (55)	dispatch ldst uop (58)	simd uops in schedulers (5a)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map ldst uop (7d)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst simd load (98)	inst ldst (9b)	9d	l1d tlb access (a0)	l1d cache miss ld (a3)	ld unit uop (a6)	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	ea	eb	ec	? ldst retires (ed)	f5	f6	f7	f8	fd
1005	394	2	1	1	0	0	0	0	1	379	3	12	12	16	25	1000	1000	1000	15037	1	369	394	394	220	3	252	1000	1000	2000	394	394	1	1	1001	1000	1000	1	1000	43	1039	39	1039	6	1	39	43	73	3	16	2	2	391	10	10	4	1000	395	395	395	395	396
1004	394	3	0	0	0	45	0	0	1	379	2	12	12	16	25	1000	1000	1000	15037	0	369	394	394	217	3	252	1000	1000	2000	394	394	1	1	1001	1000	1000	0	1000	43	1039	38	1038	6	1	39	43	73	3	16	3	3	395	10	10	7	1000	399	399	399	399	399
1004	394	3	0	1	0	44	1	0	1	383	2	12	12	19	25	1000	1000	1000	15274	0	373	394	398	221	3	252	1000	1000	2000	394	394	1	1	1001	1000	1000	0	1000	43	1038	38	1038	6	1	39	44	73	3	16	3	3	391	10	14	7	1000	399	399	399	399	399
1004	398	3	0	0	0	44	0	0	1	383	2	1	1	19	25	1000	1000	1000	15274	0	373	398	398	221	3	256	1000	1000	2000	398	394	1	1	1001	1000	1000	0	1000	43	1038	38	1038	6	1	39	44	73	3	16	3	3	395	14	14	4	1000	399	399	399	399	399
1004	398	3	0	0	0	44	0	0	1	379	0	1	1	19	25	1000	1000	1000	15267	0	373	398	398	221	3	256	1000	1000	2000	399	397	1	1	1001	1000	1000	0	1000	43	1038	38	1038	6	1	38	43	73	3	16	3	3	391	14	10	7	1000	399	399	399	399	399
1004	394	3	0	0	0	44	0	0	1	383	2	12	12	22	25	1000	1000	1000	15267	0	373	394	395	221	3	252	1000	1000	2000	394	394	1	1	1001	1000	1000	0	1000	43	1038	38	1038	6	1	39	44	73	3	16	3	3	395	10	10	7	1000	399	399	399	399	399
1004	398	2	0	0	0	44	0	0	1	383	2	1	1	19	25	1000	1000	1000	14989	0	373	398	398	221	3	256	1000	1000	2000	398	394	1	1	1001	1000	1000	0	1000	43	1039	38	1039	6	1	39	44	73	3	16	2	2	395	14	10	7	1000	399	399	399	399	399
1004	398	3	0	0	0	44	1	0	1	384	2	1	1	19	25	1000	1000	1000	15086	0	369	398	398	221	3	256	1000	1000	2000	394	394	1	1	1001	1000	1000	0	1000	43	1038	38	1000	6	1	39	44	73	3	16	3	3	395	14	14	7	1000	399	399	399	399	399
1004	398	3	0	0	0	44	0	0	1	383	2	12	1	19	25	1000	1000	1000	15267	0	369	398	394	221	3	256	1000	1000	2000	394	394	1	1	1001	1000	1000	0	1000	43	1039	38	1038	6	1	39	44	73	3	16	2	3	395	14	14	7	1000	399	399	399	395	399
1004	394	3	0	0	0	44	0	0	1	383	2	1	1	19	25	1000	1000	1000	15274	1	373	398	398	221	3	256	1000	1000	2000	398	395	1	1	1001	1000	1000	0	1000	43	1038	38	1040	6	1	39	44	73	3	16	3	3	395	14	10	7	1000	399	399	399	399	399

Test 2: Latency 1->2 roundtrip

Chain cycles: 3

Code:

  ldr d0, [x6, x7]
  fmov x0, d0
  eor x8, x8, x0
  eor x8, x8, x0
  add x6, x6, x8

Initialization

  mov x7, #4
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 9.0054

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	09	l2 tlb miss data (0b)	0e	0f	18	19	1e	1f	22	23	24	3a	3f	4d	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	69	6d	6e	map stall dispatch (70)	int prf full (71)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	af	b5	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
50205	120047	900	0	0	0	0	0	0	0	0	296	0	1	0	0	0	120020	119514	109468	25	60103	40106	10000	10000	30100	10000	10000	1078925	5736188	6133818	120026	120050	120035	113137	0	3	113636	50100	30200	10000	10000	60200	20000	10000	120050	120035	1	1	50201	100	99	100	40100	10000	10000	1	100	10000	0	0	10000	0	0	0	10000	0	0	1	0	0	0	0	0	3210	1	135	1	1	119660	40002	9	6	5	10000	40100	120051	120048	120048	120051	120051
50204	120050	899	0	0	0	0	0	0	0	0	205	0	0	0	0	0	120035	119493	109461	25	60103	40100	10001	10000	30100	10000	10000	1078862	5736188	6133818	120011	120035	120050	113218	0	3	113658	50100	30200	10000	10000	60842	20000	10000	120035	120047	1	1	50202	100	99	100	40100	10000	10000	0	100	10000	0	0	10000	0	0	0	10000	1	0	0	0	0	0	0	0	3210	1	101	0	1	119657	40036	9	0	8	10000	40100	120036	120036	120051	120048	120051
50204	120050	954	0	0	1	2	1	1	0	0	148	0	0	0	0	1	120045	119519	109458	25	60106	40104	10002	10000	30100	10000	10000	1079062	5736524	6133458	120017	120060	120062	113241	0	3	113680	50100	30200	10000	10000	60200	20000	10000	120057	120058	1	1	50201	100	99	100	40100	10000	10000	0	100	10001	1	0	10002	2	0	16	10000	1	1	1	1	0	0	0	0	3210	1	107	1	1	119664	40004	0	10	12	10000	40100	120061	120064	120064	120049	120056
50204	120035	964	0	0	0	0	0	1	0	0	1	0	0	0	1	0	120041	119515	109533	25	60106	40104	10002	10000	30111	10010	10006	1077902	5736710	6133999	120026	120050	120053	113236	0	3	113667	50100	30200	10000	10000	60200	20000	10000	120130	120050	1	1	50201	100	99	100	40100	10000	10000	0	100	10000	0	1	10000	0	0	0	10000	0	0	1	0	0	0	0	0	3210	1	107	1	1	119646	40002	9	6	8	10000	40100	120051	120051	120051	120051	120051
50204	120050	899	0	0	0	0	0	0	0	0	1	0	0	0	0	0	120035	119519	109461	25	60103	40102	10001	10000	30100	10000	10000	1079200	5735455	6133818	120011	120050	120056	113144	0	3	113667	50100	30200	10000	10000	60200	20000	10000	120035	120047	1	1	50201	100	99	100	40100	10000	10000	1	100	10000	0	1	10000	0	0	0	10000	1	0	1	0	0	0	0	1	3221	0	16	0	0	119730	40004	10	0	12	10000	40100	120061	120061	120042	120061	120042
50204	120060	899	1	0	0	0	0	0	0	0	6	0	0	0	1	0	120039	119514	109514	25	60100	40102	10001	10000	30108	10008	10006	1079120	5736614	6136783	120030	120057	120057	113237	0	7	113732	50122	30228	10010	10010	60256	20020	10010	120054	120051	1	1	50201	100	99	100	40100	10000	10000	0	100	10000	0	1	10000	0	0	0	10000	1	0	1	0	0	1	1	1	3220	0	16	0	1	119734	40002	0	0	12	10000	40100	120052	120036	120055	120055	120055
50204	120054	899	0	0	0	0	0	0	0	0	0	0	0	0	1	0	120020	119493	109467	25	60100	40102	10000	10000	30100	10000	10000	1079035	5736380	6136317	120027	120175	120047	113161	0	3	113668	50100	30200	10000	10000	60200	20000	10053	120097	120051	1	1	50201	100	99	100	40100	10000	10000	1	100	10000	0	1	10000	1	0	186	10000	1	0	1	0	0	0	0	0	3210	1	107	1	1	119661	40000	0	13	0	10000	40100	120055	120055	120052	120055	120041
50204	120054	899	0	0	0	0	1	1	1	1	178	88	0	0	1	0	120236	119493	109468	25	60103	40102	10001	10000	30100	10000	10000	1079062	5736380	6136317	120011	120041	120102	113150	0	3	113671	50100	30200	10000	10000	60200	20000	10000	120035	120051	1	1	50201	100	99	100	40100	10000	10000	0	100	10000	0	1	10000	0	0	0	10000	0	0	1	0	0	0	0	0	3210	3	107	1	1	119803	40056	13	0	9	10000	40100	120036	120052	120058	120055	120052
50204	120036	899	0	0	0	0	1	0	0	0	12	0	0	0	1	0	120050	119513	109467	25	60103	40102	10001	10000	30100	10000	10000	1079008	5736524	6136317	120030	120057	120107	113146	0	3	113672	50100	30200	10000	10000	60200	20000	10000	120051	120036	1	1	50201	100	99	100	40100	10000	10000	0	100	10000	0	0	10000	1	0	6	10000	1	0	1	0	0	0	0	0	3210	1	101	1	1	119661	40002	13	13	12	10000	40100	120052	120095	120063	120085	120048
50204	120049	899	0	0	0	0	0	0	0	0	6	0	0	0	1	0	120020	119509	109461	25	60103	40100	10001	10000	30100	10000	10000	1078999	5735455	6133818	120026	120054	120050	113141	0	3	113658	50100	30200	10000	10000	60200	20000	10000	120050	120047	1	1	50201	100	99	100	40100	10000	10000	0	100	10000	0	1	10000	0	0	0	10000	1	1	1	1	2	0	0	0	3210	1	101	1	1	119660	40014	0	6	5	10000	40100	120048	120036	120048	120036	120036

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 9.0054

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	09	0e	0f	1e	22	24	3f	4d	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	69	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	af	b5	l1d cache miss ld nonspec (bf)	branch cond mispred nonspec (c5)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
50025	120051	899	0	1	0	0	9	0	0	120020	119492	109449	25	60035	40021	10004	10000	30010	10000	10000	1079557	5736236	6133662	0	120030	0	120054	120035	113172	3	113693	50010	30020	10000	10000	60020	20000	10000	120035	120051	1	1	50021	10	9	10	40010	10000	10000	1	10	10000	1	10000	0	0	0	10000	1	1	0	0	3140	3	107	2	2	119669	40002	10	10	9	10000	40010	120036	120036	120055	120036	120055
50024	120051	899	0	1	0	0	0	0	0	120039	119492	109467	25	60010	40012	10000	10000	30010	10000	10000	1082126	5738444	6133715	0	120030	0	120035	120035	113169	3	113693	50010	30020	10000	10000	60020	20000	10000	120035	120051	1	1	50021	10	9	10	40010	10000	10000	0	10	10000	1	10000	0	0	24	10000	1	0	0	0	3140	2	107	3	3	119669	40000	10	0	0	10000	40010	120055	120036	120052	120052	120055
50024	120054	899	0	0	0	0	1	0	0	120039	119509	109467	25	60010	40012	10001	10000	30010	10000	10000	1079584	5735455	6133662	0	120011	0	120054	120035	113153	3	113693	50010	30020	10000	10000	60020	20000	10000	120054	120035	1	1	50021	10	9	10	40010	10000	10000	0	10	10000	1	10000	0	0	0	10000	1	1	0	0	3140	2	107	2	2	119669	40002	0	13	12	10000	40010	120055	120055	120055	120055	120055
50024	120054	899	0	0	0	0	1	1	0	120020	119512	109464	25	60013	40012	10001	10000	30010	10000	10000	1079584	5736380	6132757	1	120011	0	120035	120035	113153	3	113693	50010	30020	10064	10000	60020	20130	10000	120035	120052	1	1	50021	10	9	10	40010	10000	10000	0	10	10000	1	10000	0	0	0	10000	1	1	0	0	3140	2	107	2	2	119650	40000	10	0	9	10000	40010	120055	120052	120052	120055	120052
50024	120051	899	0	1	0	0	1	0	0	120020	119512	109467	25	60013	40010	10000	10000	30010	10000	10000	1079517	5736380	6133662	0	120027	0	120054	120054	113153	3	113693	50010	30020	10000	10000	60020	20000	10000	120054	120051	1	1	50021	10	9	10	40010	10000	10000	0	10	10000	1	10000	0	0	0	10000	1	1	0	0	3140	2	107	3	3	119666	40002	13	0	9	10000	40010	120055	120055	120055	120052	120036
50024	120054	899	0	0	0	0	1	1	0	120039	119492	109467	25	60013	40012	10001	10000	30010	10000	10000	1079584	5736380	6133662	0	120011	0	120054	120054	113153	3	113674	50010	30020	10000	10000	60020	20000	10000	120035	120051	1	1	50021	10	9	10	40010	10000	10000	0	10	10000	0	10000	0	0	0	10000	1	1	0	0	3140	2	107	3	2	119666	40002	13	10	12	10000	40010	120055	120055	120055	120055	120055
50024	120054	899	0	0	0	0	1	0	0	120039	119512	109467	25	60010	40012	10001	10000	30010	10000	10000	1079517	5736380	6133662	1	120030	0	120035	120035	113172	3	113674	50010	30020	10000	10000	60020	20000	10000	120054	120051	1	1	50021	10	9	10	40010	10000	10000	0	10	10000	0	10000	0	0	0	10000	0	1	0	0	3140	2	107	3	2	119807	40002	10	0	12	10000	40010	120036	120052	120052	120052	120055
50024	120035	899	0	0	0	0	1	1	0	120039	119509	109467	25	60013	40012	10001	10000	30010	10000	10000	1079557	5736236	6133815	0	120030	0	120099	120035	113169	3	113693	50010	30020	10000	10000	60020	20000	10000	120054	120035	1	1	50021	10	9	10	40010	10000	10000	0	10	10000	1	10000	0	0	0	10000	1	0	0	0	3140	2	107	3	3	119666	40000	13	13	0	10000	40010	120055	120055	120055	120036	120036
50024	120035	899	0	0	0	0	1	0	0	120039	119492	109467	25	60013	40010	10001	10000	30010	10000	10000	1079557	5736380	6133815	1	120114	3	120035	120058	113172	3	113690	50010	30020	10000	10000	60020	20000	10000	120035	120051	1	1	50021	10	9	10	40010	10000	10000	0	10	10000	1	10000	30	0	0	10000	1	1	0	0	3140	2	107	2	2	119666	40002	13	0	12	10000	40010	120055	120055	120055	120056	120052
50024	120035	899	0	0	0	0	1	1	0	120036	119509	109449	25	60013	40012	10001	10000	30010	10000	10000	1079584	5736380	6132757	1	120027	0	120061	120035	113169	3	113674	50010	30020	10000	10000	60020	20000	10000	120051	120035	1	1	50021	10	9	10	40010	10000	10000	0	10	10000	1	10000	0	0	0	10000	1	1	0	0	3140	2	107	2	2	119718	40002	10	10	0	10000	40010	120055	120055	120052	120052	120055

Test 3: Latency 1->3 roundtrip

Chain cycles: 3

Code:

  ldr d0, [x6, x7]
  fmov x0, d0
  eor x8, x8, x0
  eor x8, x8, x0
  add x7, x7, x8

Initialization

  mov x7, #4
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 9.0056

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk instruction (07)	mmu table walk data (08)	09	l2 tlb miss data (0b)	0e	0f	18	1e	1f	22	23	24	3a	3f	4d	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	af	b5	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cf	d0	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
50205	120053	899	1	0	1	1	1	1	1	0	1	0	0	0	0	1	120038	119727	109469	25	60106	40102	10001	10000	30100	10000	10000	1079053	5736332	6136419	1	120032	120041	120041	113137	22	113675	50100	30200	10000	10000	60200	20000	10000	120056	120053	1	1	50201	100	99	100	40100	10000	10000	0	100	10001	3	0	10002	3	1	1	10000	1	1	1	1	3	0	0	3210	0	3	107	2	2	119654	40004	9	0	8	10000	40100	120059	120057	120057	120042	120042
50204	120056	899	1	0	1	1	1	0	0	0	2	0	0	0	0	1	120041	119515	109474	25	60106	40104	10002	10000	30100	10000	10000	1079053	5735750	6136419	1	120017	120056	120056	113137	3	113630	50100	30200	10000	10000	60200	20214	10000	120056	120053	1	1	50201	100	99	100	40100	10000	10000	0	100	10001	3	1	10002	0	1	1	10000	0	1	0	1	1	0	0	3210	0	2	135	2	2	119660	40002	0	0	0	10000	40100	120057	120057	120057	120414	120042
50204	120056	899	1	1	0	0	0	1	1	0	1	0	0	0	0	0	120035	119509	109463	25	60100	40102	10002	10000	30671	10000	10000	1079097	5736476	6136572	1	120032	120041	120053	113148	3	113630	50100	30200	10000	10000	60200	20000	10000	120041	120053	1	1	50201	100	99	100	40100	10000	10000	0	100	10003	1	1	10001	5	1	1	10000	0	1	0	1	1	0	0	3210	0	2	107	2	2	119654	40056	6	6	8	10000	40100	120057	120042	120042	120059	120057
50204	120056	899	1	0	0	0	1	1	1	0	2	0	0	0	0	0	120041	119513	109469	25	60103	40102	10002	10000	30100	10000	10000	1079053	5736524	6136725	1	120029	120056	120041	113138	3	113630	50100	30200	10000	10000	60200	20000	10000	120053	120041	1	1	50201	100	99	100	40100	10000	10000	0	100	10003	3	0	10006	0	0	1	10000	0	1	0	1	3	0	0	3210	0	2	107	2	2	119660	40004	6	9	5	10000	40100	120054	120042	120057	120057	120042
50204	120056	899	1	0	1	1	1	0	0	0	2	0	1	0	0	0	120041	119515	109455	25	60106	40102	10002	10000	30100	10000	10000	1079097	5736332	6146850	1	120018	120053	120041	113151	3	113670	50100	30200	10000	10000	61492	20000	10000	120053	120053	1	1	50201	100	99	100	40100	10000	10000	0	100	10001	1	1	10001	0	0	13	10000	1	1	0	1	1	0	0	3327	0	2	107	2	3	119663	40004	9	9	8	10000	40100	120042	120042	120057	120057	120062
50204	120041	899	1	0	1	0	2	0	0	0	5	0	1	0	0	0	120031	119516	109455	25	60103	40102	10001	10000	30100	10000	10000	1079035	5746012	6133561	1	120032	120056	120060	113137	3	113673	50100	30200	10000	10000	60200	20000	10000	120053	120053	1	1	50201	100	99	100	40100	10000	10000	0	100	10002	2	0	10002	1	0	1	10000	0	1	0	1	1	0	0	3210	0	2	107	2	2	119661	40004	6	0	8	10000	40100	120042	120054	120057	120057	120042
50204	120056	899	1	0	1	1	0	0	0	3	1	0	1	0	0	0	120041	119515	109469	25	60103	40104	10002	10000	30100	10000	10000	1079026	5736476	6136419	1	120032	120060	120056	113137	3	113630	50100	30200	10000	10000	60200	20000	10000	120044	120418	1	1	50201	100	99	100	40100	10000	10000	0	100	10001	2	1	10002	0	2	1	10000	1	1	1	1	1	0	0	3210	0	2	135	2	2	119654	40002	9	6	8	10000	40100	120042	120054	120054	120060	120057
50204	120056	899	1	0	1	1	1	1	1	0	1	0	0	0	0	1	122268	120664	110179	659	60423	40321	10052	10050	33677	11365	11226	1136242	5792533	6192983	1	121888	120805	122327	113879	311	114971	56209	34451	11340	11347	68578	22768	11336	122394	122392	26	1	50201	100	99	100	40100	10000	10000	0	100	10002	1	1	10002	1	1	25	10000	1	1	1	1	3	0	0	3961	0	2	376	2	2	121592	40004	0	9	5	10000	40100	120057	120042	120042	120055	120612
50204	120056	1053	1	0	1	0	0	1	1	0	14	0	1	0	0	0	120041	119526	109900	1130	60587	40467	10044	10084	36527	12476	10000	1121977	5807519	6219504	1	120036	120060	120060	113155	3	113630	50100	30200	10000	10000	60200	20000	10000	120060	120439	1	1	50201	100	99	100	40100	10000	10000	0	100	10001	3	1	10001	2	0	1	10000	1	1	0	1	1	0	0	3210	0	2	107	2	2	119654	40002	0	10	9	10000	40100	120061	120046	120437	120061	120058
50204	120060	899	1	0	1	1	1	1	0	0	1	0	0	0	0	1	120042	119519	109455	25	60106	40102	10002	10000	30100	10000	10000	1079089	5735750	6133458	1	120033	120041	120060	113155	3	113677	50100	30200	10000	10000	60200	20000	10000	120041	120057	1	1	50201	100	99	100	40100	10000	10000	0	100	10002	1	1	10001	0	0	1	10000	0	1	1	1	0	0	0	3210	0	2	107	2	2	119664	40002	13	0	0	10000	40100	120042	120061	120042	120058	120058

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 9.0051

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	09	l2 tlb miss data (0b)	0e	0f	18	19	1e	22	23	3f	4d	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	ac	af	b5	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
50025	120057	899	1	1	1	1	1	1	0	0	1	1	0	120039	119492	109467	25	60010	40010	10001	10000	30010	10000	10000	1079584	5736380	6133662	0	120027	120054	120035	113153	3	113698	50010	30020	10000	10000	60020	20000	10000	120054	120051	1	1	50021	10	9	10	40010	10000	10000	1	10	10000	0	1	10000	0	0	10000	1	0	1	0	0	3140	4	107	2	2	119669	40002	13	10	0	10000	40010	120055	120036	120055	120052	120055
50024	120055	900	0	0	0	0	1	0	0	0	1	0	0	120039	119492	109467	25	60013	40010	10001	10000	30010	10000	10000	1079517	5736380	6133662	0	120011	120035	120054	113172	3	113690	50010	30020	10000	10000	60020	20000	10000	120035	120051	1	1	50021	10	9	10	40010	10000	10000	0	10	10000	0	1	10000	0	0	10000	0	0	1	0	0	3140	2	107	2	2	119650	40000	0	10	12	10000	40010	120055	120055	120055	120036	120036
50024	120035	899	0	0	0	0	1	0	0	0	132	0	0	120095	119509	109505	25	60013	40012	10001	10000	30010	10000	10000	1079584	5735455	6133662	1	120035	120054	120054	113153	3	113690	50010	30020	10000	10000	60020	20000	10000	120054	120051	1	1	50021	10	9	10	40010	10000	10000	0	10	10000	0	1	10000	0	0	10000	1	0	1	0	0	3140	1	107	2	2	119669	40000	13	10	12	10000	40010	120052	120055	120055	120055	120055
50024	120054	900	0	0	0	0	1	0	3	0	0	0	0	120039	119512	109467	25	60013	40010	10000	10000	30010	10000	10000	1079535	5736380	6133815	1	120030	120054	120054	113154	41	113690	50010	30020	10000	10064	60020	20000	10000	120052	120051	1	1	50021	10	9	10	40010	10000	10000	0	10	10000	0	1	10000	0	0	10000	0	0	1	0	2	3140	2	107	2	2	119666	40000	13	0	12	10000	40010	120039	120036	120055	120055	120055
50024	120054	899	0	0	0	0	1	1	0	0	0	0	0	120039	119681	109472	25	60010	40010	10001	10000	30010	10000	10000	1079517	5735455	6133662	1	120011	120077	120051	113172	3	113690	50010	30020	10000	10000	60020	20000	10000	120054	120035	1	1	50021	10	9	10	40010	10000	10000	0	10	10006	0	0	10000	0	0	10000	0	0	1	0	0	3140	1	107	1	1	119666	40002	0	10	12	10000	40010	120055	120036	120036	120055	120036
50024	120054	899	0	0	0	0	1	0	0	0	1	1	0	120039	119512	109467	25	60010	40012	10001	10000	30010	10063	10000	1079584	5736380	6132757	0	120011	120054	120035	113169	3	113674	50010	30020	10000	10000	60020	20000	10000	120054	120051	1	1	50021	10	9	10	40010	10000	10000	0	10	10000	0	0	10000	0	0	10000	1	0	0	0	0	3140	2	107	2	2	119669	40002	13	10	9	10000	40010	120055	120036	120052	120052	120036
50024	120054	899	0	0	0	0	1	0	0	0	1	0	0	120039	119512	109467	25	60013	40010	10000	10000	30010	10000	10000	1079584	5736380	6133662	0	120030	120054	120035	113172	3	113674	50010	30020	10000	10000	60020	20000	10000	120054	120051	1	1	50021	10	9	10	40010	10000	10000	0	10	10000	0	1	10000	0	0	10000	1	0	1	0	0	3140	2	107	2	2	119650	40000	13	0	9	10000	40010	120055	120036	120055	120036	120055
50024	120035	899	0	0	0	0	1	0	0	0	1	1	0	120039	119492	109467	25	60013	40010	10000	10000	30010	10000	10000	1079584	5736380	6133662	1	120030	120054	120054	113172	3	113693	50010	30020	10000	10000	60020	20000	10000	120054	120035	1	1	50021	10	9	10	40010	10000	10000	0	10	10000	0	0	10000	0	0	10000	1	0	1	0	0	3140	2	107	2	2	119666	40000	0	13	9	10000	40010	120055	120052	120052	120055	120055
50024	120054	899	0	0	0	0	1	1	0	0	4	1	0	120020	119492	109467	25	60010	40012	10001	10000	30010	10000	10000	1079557	5736380	6132757	1	120030	120035	120035	113172	3	113674	50010	30020	10000	10000	60020	20000	10000	120035	120051	1	1	50021	10	9	10	40010	10000	10000	0	10	10000	0	1	10000	0	0	10000	1	0	1	0	0	3140	3	107	2	3	119650	40002	10	10	12	10000	40010	120054	120052	120055	120036	120052
50024	120051	900	0	0	0	0	1	0	0	0	12	0	0	120039	119517	109467	25	60010	40012	10001	10000	30010	10000	10000	1079584	5735455	6133662	1	120030	120054	120051	113172	3	113693	50010	30020	10000	10000	60020	20000	10000	120054	120051	1	1	50021	10	9	10	40010	10000	10000	1	10	10000	0	0	10000	0	0	10000	1	0	0	0	0	3140	1	107	2	2	119666	40000	0	13	0	10000	40010	120036	120055	120055	120055	120036

Test 4: throughput

Count: 8

Code:

  ldr d0, [x6, x7]
  ldr d0, [x6, x7]
  ldr d0, [x6, x7]
  ldr d0, [x6, x7]
  ldr d0, [x6, x7]
  ldr d0, [x6, x7]
  ldr d0, [x6, x7]
  ldr d0, [x6, x7]

Initialization

  mov x7, 8

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.3340

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk instruction (07)	09	l2 tlb miss instruction (0a)	0e	0f	1e	22	23	3a	3f	43	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d cache miss ld (a3)	a5	ld unit uop (a6)	l1d cache writeback (a8)	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
80205	26724	200	1	1	1	1	1	0	1	0	0	26707	2	18	18	81	25	80100	100	80000	100	80015	500	1167263	1	26697	26722	26707	16650	6	16674	80114	200	80024	200	160048	26722	26722	1	1	80201	100	99	100	100	80000	80000	0	100	80000	39	0	80035	0	35	80035	6	1	35	39	1	1	1	5118	1	16	1	1	26719	6	6	2	80000	100	26708	26723	26708	26798	26732
80204	26722	200	1	0	1	0	0	41	1	0	1	26707	2	0	18	63	25	80100	100	80000	100	80014	500	1159814	0	26697	26722	26722	16650	6	16674	80114	200	80024	200	160048	26722	26707	1	1	80201	100	99	100	100	80000	80000	0	100	80000	39	0	80036	1	3	80035	0	1	35	39	1	1	1	5118	1	16	1	1	26704	6	6	2	80000	100	26723	26708	26723	26779	26723
80204	26722	200	1	0	1	1	0	41	1	0	1	26707	2	18	18	12	25	80100	100	80000	100	80014	500	1168369	1	26682	26722	26722	16650	6	16674	80114	200	80024	200	160048	26722	26707	1	1	80201	100	99	100	100	80000	80000	0	100	80000	39	28	80035	51	35	80035	6	1	36	39	1	1	1	5118	1	16	1	1	26724	6	6	2	80000	100	26723	26723	26723	26723	26887
80204	26848	200	1	0	1	0	0	41	1	0	1	26707	2	18	0	73	25	80100	100	80000	100	80014	500	1170622	0	26697	26722	26722	16635	6	16674	80115	200	80024	200	160048	26722	26707	1	1	80201	100	99	100	100	80000	80000	0	100	80000	0	0	80035	1	38	80000	0	1	0	39	1	1	1	5118	2	16	1	1	26719	0	6	0	80000	100	26723	26723	26723	26785	26718
80204	26722	200	1	0	1	0	0	41	1	0	0	26707	2	18	18	13	25	80100	100	80000	100	80015	500	1170050	1	26682	26722	26722	16655	6	16674	80114	200	80024	200	160048	26722	26722	1	1	80201	100	99	100	100	80000	80000	0	100	80000	39	0	80035	0	38	80035	6	1	35	0	1	1	1	5118	1	16	1	1	26719	6	6	0	80000	100	26723	26723	26723	26880	26730
80204	26727	201	1	0	1	0	0	41	1	0	1	26707	2	18	18	43	25	80100	100	80000	100	80015	500	1167875	0	26697	26707	26722	16650	6	16674	80114	200	80024	200	160048	26722	26722	1	1	80201	100	99	100	100	80000	80000	0	100	80000	39	0	80035	0	35	80035	6	1	0	39	1	1	1	5118	1	16	1	1	26704	0	6	2	80000	100	26723	26723	26801	26771	26733
80204	26722	200	1	0	1	0	0	41	1	0	1	26692	0	18	18	78	25	80100	100	80000	100	80014	500	1166888	0	26697	26722	26722	16650	6	16674	80114	200	80024	200	160048	26722	26722	1	1	80201	100	99	100	100	80000	80000	0	100	80000	39	0	80035	1	35	80035	0	0	35	39	1	1	1	5118	1	16	1	1	26719	6	6	2	80000	100	26708	26723	26708	26842	26731
80204	26722	200	1	0	1	0	0	41	0	1	1	26707	2	18	18	75	25	80100	100	80000	100	80015	500	1167875	0	26697	26722	26722	16650	6	16674	80115	200	80024	200	160048	26722	26722	1	1	80201	100	99	100	100	80000	80000	0	100	80000	39	0	80000	1	35	80035	6	0	35	39	1	1	1	5118	1	16	1	1	26719	0	6	2	80000	100	26723	26724	26723	26812	26733
80204	26722	200	1	0	1	0	0	0	0	0	1	26707	2	18	18	14	25	80100	100	80000	100	80014	500	1167875	0	26697	26722	26722	16650	6	16674	80114	200	80024	200	160048	26722	26722	1	1	80201	100	99	100	100	80000	80000	0	100	80000	39	0	80035	1	38	80035	6	1	35	39	1	1	1	5118	1	16	1	1	26719	6	6	2	80000	100	26723	26723	26723	26789	26723
80204	26722	200	1	0	1	0	0	41	0	0	1	26707	2	0	0	75	25	80100	100	80000	100	80015	500	1166596	1	26697	26722	26722	16650	6	16674	80115	200	80024	200	160048	26722	26722	1	1	80201	100	99	100	100	80000	80000	0	100	80000	39	0	80035	1	0	80035	0	0	35	39	1	1	1	5118	1	16	1	1	26704	6	6	2	80000	100	26723	26708	26723	26808	27318

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.3341

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	09	l2 tlb miss data (0b)	0e	0f	1e	22	24	3a	3f	43	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	cf	d0	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
80025	26728	200	0	1	0	0	0	45	1	0	1	26716	2	12	0	19	25	80010	10	80000	10	80000	50	1167124	1	26683	26731	26708	16676	3	16688	80010	20	80000	20	160000	26727	26727	1	1	80021	10	9	10	10	80000	80000	0	10	80000	0	80000	0	38	80000	6	0	0	44	5020	0	4	16	5	3	26728	14	0	7	80000	10	26732	26709	26721	26732	26732
80024	26731	200	0	1	0	0	0	44	0	0	1	26716	2	1	12	19	25	80010	10	80000	10	80000	50	1167201	0	26706	26731	26731	16652	3	16711	80010	20	80000	20	160000	26728	26728	1	1	80021	10	9	10	10	80000	80000	0	10	80000	43	80000	0	38	80038	6	1	39	44	5020	0	5	16	3	5	26705	14	10	7	80000	10	26709	26728	26709	26728	26709
80024	26731	200	0	1	0	0	0	0	1	0	1	26693	2	0	12	19	25	80010	10	80000	10	80000	50	1166750	0	26683	26731	26732	16652	3	16688	80010	20	80000	20	160000	26731	26708	1	1	80021	10	9	10	10	80000	80000	0	10	80000	0	80000	1	42	80000	0	0	0	43	5020	0	5	16	5	7	26728	0	14	0	80000	10	26732	26732	26709	26728	26709
80024	26708	200	0	1	0	0	0	44	0	0	1	26716	2	1	0	19	25	80010	10	80000	10	80000	50	1167124	0	26706	26731	26727	16652	3	16688	80010	20	80000	20	160000	26708	26727	1	1	80021	10	9	10	10	80000	80000	1	10	80000	0	80038	0	38	80000	6	1	39	44	5020	0	4	16	5	5	26705	14	14	4	80000	10	26732	26709	26728	26732	26728
80024	26731	200	0	1	0	0	0	45	1	0	1	26693	2	1	1	16	25	80010	10	80000	10	80000	50	1167124	0	26715	26708	26731	16672	3	16688	80010	20	80000	20	160384	26894	26730	1	1	80021	10	9	10	10	80000	80000	0	10	80000	43	80038	0	38	80038	6	1	39	0	5020	0	6	16	5	5	26728	0	14	7	80000	10	26732	26732	26709	26728	26732
80024	26731	201	0	1	0	0	0	44	1	0	0	26712	2	1	1	0	25	80010	10	80000	10	80000	50	1168843	0	26683	26731	26708	16652	3	16708	80010	20	80000	20	160000	26731	26727	1	1	80021	10	9	10	10	80000	80000	0	10	80000	43	80039	0	0	80038	0	1	0	44	5020	0	5	16	3	5	26705	14	0	7	80000	10	26732	26732	26732	26709	26709
80024	26708	200	0	1	0	0	0	0	0	0	1	26716	2	1	0	0	25	80010	10	80000	10	80000	50	1166750	0	26702	26731	26731	16676	3	16708	80010	20	80000	20	160000	26731	26708	1	1	80021	10	9	10	10	80000	80000	0	10	80000	0	80039	0	38	80038	0	1	39	43	5020	0	5	16	7	6	26724	14	10	4	80000	10	26729	26729	26729	26709	26728
80024	26731	200	0	1	0	1	0	0	0	0	1	26716	2	12	0	19	25	80010	10	80000	10	80000	50	1167201	0	26683	26708	26731	16652	3	16711	80010	20	80000	20	160000	26731	26708	1	1	80021	10	9	10	10	80000	80000	0	10	80000	43	80039	0	41	80000	6	0	0	44	5020	0	5	16	7	4	26705	14	14	7	80000	10	26732	26732	26732	26732	26732
80024	26731	200	0	1	0	0	1	0	0	0	0	26693	2	1	1	19	25	80010	10	80000	10	80000	50	1166750	1	26683	26708	26731	16676	3	16711	80010	20	80000	20	160000	26731	26708	1	1	80021	10	9	10	10	80000	80000	0	10	80000	0	80039	0	0	80038	0	0	38	43	5020	0	5	16	5	4	26705	0	0	7	80000	10	26709	26732	26732	26732	26732
80024	26708	200	0	1	0	1	0	44	1	0	1	26716	2	1	0	0	25	80010	10	80000	10	80000	50	1167124	0	26710	26731	26731	16672	3	16708	80010	20	80000	20	160000	26708	26727	1	1	80021	10	9	10	10	80000	80000	0	10	80000	44	80038	0	38	80038	6	1	39	43	5020	0	5	16	5	3	26728	0	10	7	80000	10	26732	26709	26728	26732	26728

LDR (register, D)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->2 roundtrip

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: Latency 1->3 roundtrip

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 4: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations