Firestorm: LDR (register, Q) measurements

Code:

  ldr q0, [x6, x7]

Initialization

  mov x7, #4
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 1.000

SIMD/FP unit issues: 0.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	09	l2 tlb miss data (0b)	0e	0f	1e	22	24	3a	3f	43	46	49	4f	51	schedule uop (52)	schedule ldst uop (55)	dispatch ldst uop (58)	simd uops in schedulers (5a)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map ldst uop (7d)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst simd load (98)	inst ldst (9b)	9d	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	ea	eb	ec	? ldst retires (ed)	f5	f6	f7	f8	fd
1005	398	3	1	1	0	0	0	1	65	1	0	1	384	0	18	0	15	25	1000	1000	1000	14674	0	374	381	399	221	3	257	1000	1000	2000	381	398	1	1	1001	1000	1000	1	1019	19	42	1057	1	0	0	69	1037	6	0	19	42	19	2	73	1	16	1	1	395	9	9	0	1000	383	399	400	399	400
1004	399	2	1	1	1	1	0	1	65	1	0	2	383	2	0	18	16	25	1000	1000	1000	15375	0	377	399	398	221	3	239	1000	1000	2000	399	381	1	1	1001	1000	1000	0	1019	20	42	1058	1	0	1	59	1038	6	1	57	42	19	1	73	1	16	1	1	396	9	9	2	1000	382	382	399	383	382
1004	399	2	1	1	1	1	0	0	65	0	0	2	384	2	0	0	16	25	1000	1000	1000	14399	0	373	398	398	221	3	257	1000	1000	2000	398	399	1	1	1001	1000	1000	0	1020	19	41	1019	0	1	0	59	1038	6	0	19	42	19	1	73	1	16	1	1	378	9	0	0	1000	400	400	400	400	399
1004	381	3	1	0	1	1	0	1	65	1	0	2	384	2	18	18	16	25	1000	1000	1000	15375	0	374	399	399	221	3	256	1000	1000	2000	399	399	1	1	1001	1000	1000	0	1019	19	42	1057	0	0	0	21	1038	0	0	57	38	19	1	73	1	16	1	1	396	0	0	2	1000	400	399	400	400	400
1004	381	3	1	0	0	1	0	1	65	0	0	2	366	2	18	0	16	25	1000	1000	1000	15318	0	374	381	399	204	3	240	1000	1000	2000	398	399	1	1	1001	1000	1000	0	1020	20	0	1019	2	0	1	59	1038	6	0	57	42	19	2	73	1	16	1	1	396	9	9	0	1000	400	399	399	383	382
1004	402	3	1	0	1	1	0	0	65	1	0	3	384	2	18	18	16	25	1000	1000	1000	15319	0	373	399	398	221	3	239	1000	1000	2000	398	381	1	1	1001	1000	1000	0	1020	19	42	1057	1	0	1	65	1039	0	0	57	42	19	1	73	1	16	1	1	379	0	9	2	1000	400	401	400	383	400
1004	398	3	1	0	1	1	1	0	65	0	0	0	366	2	0	18	15	25	1000	1000	1000	15314	0	356	398	399	221	3	257	1000	1000	2000	399	398	1	1	1001	1000	1000	0	1020	21	0	1019	1	0	0	27	1038	6	1	57	38	19	1	73	1	16	1	1	396	9	9	2	1000	399	399	400	382	399
1004	398	2	1	1	0	1	0	0	21	1	0	0	384	0	18	0	0	25	1000	1000	1000	15362	0	373	399	382	204	3	239	1000	1000	2000	398	381	1	1	1001	1000	1000	0	1020	19	42	1058	1	0	0	60	1000	6	1	57	42	19	1	73	1	16	1	1	396	9	4	0	1000	382	382	400	383	400
1004	381	3	1	1	0	0	0	0	66	0	0	2	383	2	0	0	0	25	1000	1000	1000	14399	0	357	399	398	221	3	257	1000	1000	2000	382	399	1	1	1001	1000	1000	0	1020	19	41	1019	1	0	2	59	1038	0	0	57	0	19	1	73	1	16	1	1	395	9	0	2	1000	383	382	400	400	382
1004	381	3	1	1	1	1	0	0	65	0	0	1	384	2	0	18	15	25	1000	1000	1000	15334	0	357	399	398	204	3	257	1000	1000	2000	398	399	1	1	1001	1000	1000	0	1020	20	0	1056	1	0	0	58	1038	6	1	57	41	19	0	73	1	16	1	1	396	9	9	2	1000	382	382	400	382	382

Test 2: Latency 1->2 roundtrip

Chain cycles: 3

Code:

  ldr q0, [x6, x7]
  fmov x0, d0
  eor x8, x8, x0
  eor x8, x8, x0
  add x6, x6, x8

Initialization

  mov x7, #4
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 9.0050

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	09	l2 tlb miss data (0b)	0e	0f	18	19	1e	22	23	24	3f	4d	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	int prf full (71)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	ac	af	b5	l1d cache miss ld nonspec (bf)	branch cond mispred nonspec (c5)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
50205	120047	899	0	0	0	0	0	0	1	0	0	0	120032	119509	109463	25	60103	40102	10000	10000	30100	10000	10000	1078862	5735455	6134461	1	120026	120050	120050	113141	0	3	113667	50100	30200	10000	10000	60200	20000	10000	120050	120035	1	1	50201	100	99	100	40100	10000	10000	1	100	10000	1	10000	0	0	10000	1	1	0	3210	1	107	1	3	119777	40002	9	6	8	10000	40100	120036	120051	120051	120048	120036
50204	120050	899	0	0	0	0	0	0	0	0	0	0	120035	119493	109461	25	60103	40100	10001	10000	30100	10000	10000	1078999	5735455	6134461	0	120023	120047	120050	113145	0	3	113796	50100	30200	10000	10000	60200	20000	10000	120042	120047	1	1	50201	100	99	100	40100	10000	10000	1	100	10000	1	10000	0	0	10000	0	1	0	3210	2	107	2	3	119657	40002	6	6	8	10000	40100	120048	120051	120048	120051	120051
50204	120050	899	0	0	0	0	0	0	1	1	0	0	120020	119493	109449	25	60100	40102	10001	10000	30100	10000	10000	1078999	5736044	6133818	1	120026	120035	120050	113143	0	3	113636	50100	30200	10000	10000	60200	20000	10000	120050	120035	1	1	50201	100	99	100	40100	10000	10000	0	100	10000	0	10000	0	0	10000	1	1	0	3210	2	107	2	1	119659	40002	9	6	8	10000	40100	120166	120055	120048	120036	120048
50204	120047	899	0	0	0	0	0	0	0	0	0	0	120026	119493	109461	25	60100	40102	10000	10000	30100	10000	10000	1078999	5735455	6134461	1	120026	120050	120047	113145	0	3	113667	50100	30200	10000	10000	60200	20000	10000	120050	120047	1	1	50201	100	99	100	40100	10000	10000	0	100	10000	0	10000	0	0	10000	1	1	0	3210	2	107	2	2	119646	40002	9	9	8	10000	40100	120051	120051	120051	120036	120036
50204	120050	899	0	0	0	0	0	0	1	0	0	0	120035	119509	109463	25	60103	40102	10001	10000	30100	10000	10000	1078999	5735455	6133818	1	120026	120050	120050	113143	0	3	113667	50100	30200	10000	10000	60200	20000	10000	120050	120047	1	1	50201	100	99	100	40100	10000	10000	0	100	10000	0	10000	0	3	10000	0	1	0	3210	2	107	2	2	119657	40002	0	6	8	10000	40100	120104	120081	120050	120048	120051
50204	120035	899	0	0	0	0	0	0	0	0	0	0	120035	119493	109463	25	60100	40102	10000	10000	30100	10000	10000	1078862	5735455	6134461	0	120026	120050	120047	113141	0	3	113667	50100	30200	10000	10000	60200	20000	10000	120035	120047	1	1	50201	100	99	100	40100	10000	10000	0	100	10000	1	10000	0	0	10000	1	0	0	3210	3	107	2	3	119657	40002	9	0	0	10000	40100	120048	120048	120051	120048	120051
50204	120050	899	0	0	0	0	0	0	6	1	0	0	120035	119493	109463	25	60103	40102	10001	10000	30100	10000	10000	1078862	5735599	6133869	1	120026	120035	120035	113141	0	3	113667	50100	30200	10000	10000	60200	20000	10000	120047	120035	1	1	50201	100	99	100	40100	10000	10000	0	100	10000	1	10000	0	0	10000	1	1	0	3210	2	101	3	2	119646	40000	9	6	8	10000	40100	120051	120036	120051	120051	120036
50204	120050	899	0	0	0	0	0	0	1	1	0	0	120035	119493	109463	25	60100	40100	10001	10000	30100	10000	10000	1078999	5736188	6136166	0	120026	120050	120050	113145	0	3	113667	50100	30200	10000	10000	60200	20000	10000	120035	120047	1	1	50201	100	99	100	40100	10000	10000	0	100	10000	1	10000	0	0	10000	1	1	0	3210	3	107	2	3	119657	40002	0	6	0	10000	40100	120054	120048	120048	120051	120036
50204	120051	899	0	0	0	0	0	0	189	1	0	0	120035	119509	109466	25	60103	40102	10001	10000	30100	10000	10000	1078999	5736188	6134461	0	120011	120050	120050	113145	0	3	113667	50100	30200	10000	10000	60200	20000	10000	120047	120047	1	1	50201	100	99	100	40100	10000	10000	0	100	10000	1	10000	0	0	10000	1	1	0	3210	3	107	3	2	119646	40000	9	0	8	10000	40100	120036	120056	120051	120036	120051
50204	120035	899	0	0	0	0	0	0	6	0	0	0	120020	119509	109463	25	60103	40102	10001	10000	30100	10000	10000	1079200	5735455	6133818	1	120026	120122	120047	113145	0	3	113667	50100	30200	10000	10000	60200	20000	10000	120047	120035	1	1	50201	100	99	100	40100	10000	10000	1	100	10000	0	10000	0	0	10000	1	1	0	3210	3	101	3	2	119646	40002	0	9	8	10000	40100	120051	120051	120051	120036	120051

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 9.0053

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	09	l2 tlb miss data (0b)	0e	0f	19	1e	22	23	3a	3f	4d	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	61	69	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	af	b5	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	branch cond mispred nonspec (c5)	cf	d0	d2	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
50025	120053	899	1	1	1	1	0	0	0	2	1	0	1	120026	119511	109474	25	60016	40014	10002	10000	30010	10000	10000	1079575	5735750	6133216	0	0	120029	0	120041	120053	113171	3	113692	50010	30020	10000	10000	60020	20000	10000	120053	120053	1	1	50021	10	9	10	40010	10000	10000	0	10	10002	2	1	10002	0	2	1	10000	1	1	1	1	1	0	3140	0	0	2	107	2	4	119668	40004	6	6	5	10000	40010	120054	120054	120054	120103	120042
50024	120053	899	1	1	0	1	0	0	0	2	1	0	1	120038	119605	109488	244	60013	40014	10002	10000	30158	10000	10000	1079584	5736332	6133764	1	5	120029	0	120053	120053	113159	3	113692	50010	30020	10000	10000	60020	20000	10000	120053	120053	1	1	50021	10	9	10	40010	10000	10000	0	10	10001	1	1	10002	4	1	1	10000	1	1	0	1	2	0	3140	0	0	4	107	2	5	119668	40004	0	0	0	10000	40010	120054	120054	120054	120091	120054
50024	120041	899	1	1	1	2	0	0	0	2	0	0	1	120038	119572	109466	25	60016	40014	10002	10000	30010	10000	10000	1079575	5736332	6133764	0	0	120029	0	120041	120041	113171	3	113692	50010	30020	10000	10000	60020	20000	10000	120053	120053	1	1	50021	10	9	10	40010	10000	10000	0	10	10001	3	1	10003	0	1	1	10000	1	1	1	1	1	0	3140	0	0	3	107	2	2	119656	40004	6	6	5	10000	40010	120043	120054	120171	120059	120054
50024	120053	899	1	0	1	1	0	0	0	1	0	0	1	120038	119547	109469	25	60016	40014	10002	10000	30010	10000	10000	1079463	5736332	6133764	0	0	120017	0	120053	120053	113171	3	113692	50010	30020	10000	10000	60020	20000	10000	120053	120041	1	1	50021	10	9	10	40010	10000	10000	0	10	10002	2	0	10003	0	1	4	10000	1	1	1	1	1	0	3140	0	0	2	107	3	3	119668	40004	6	6	5	10000	40010	120054	120054	120054	120133	120054
50024	120053	899	1	1	1	1	0	0	0	2	1	0	1	120038	119499	109513	25	60016	40014	10001	10002	30010	10000	10000	1079463	5736332	6133764	0	0	120029	0	120057	120053	113171	3	113692	50010	30020	10000	10000	60020	20000	10000	120041	120053	1	1	50021	10	9	10	40010	10000	10000	0	10	10002	2	1	10002	1	2	1	10000	1	1	1	1	1	0	3140	0	0	2	107	2	4	119841	40004	6	6	5	10000	40010	120054	120054	120054	120118	120054
50024	120041	899	1	1	1	0	0	0	0	2	1	0	1	120043	119511	109467	25	60013	40014	10002	10000	30010	10000	10000	1079575	5736332	6133764	0	0	120029	0	120053	120053	113171	3	113680	50010	30020	10000	10000	60020	20000	10000	120041	120053	1	1	50021	10	9	10	40010	10000	10000	0	10	10002	2	0	10002	1	1	1	10000	1	1	1	1	0	0	3140	0	0	3	107	2	4	119668	40004	6	6	0	10000	40010	120042	120054	120160	120125	120054
50024	120041	899	1	1	1	0	0	0	0	2	1	0	1	120038	119511	109468	25	60016	40014	10002	10000	30010	10000	10000	1079575	5736332	6133917	0	0	120029	0	120053	120053	113171	3	113692	50010	30020	10000	10000	60020	20000	10000	120102	120053	2	1	50021	10	9	10	40010	10000	10000	0	10	10001	2	1	10003	0	0	1	10000	1	1	1	1	2	0	3140	0	0	3	107	4	2	119668	40002	6	0	5	10000	40010	120042	120042	120054	120106	120054
50024	120053	900	1	1	1	0	0	0	0	1	1	0	1	120066	119511	109525	25	60016	40014	10002	10000	30010	10000	10000	1079575	5736332	6133764	0	0	120029	0	120053	120053	113171	3	113692	50010	30020	10000	10000	60398	20000	10000	120053	120053	1	1	50021	10	9	10	40010	10000	10000	0	10	10002	2	1	10001	0	1	1	10000	1	1	1	1	1	0	3140	0	0	4	107	4	4	119668	40004	6	0	5	10000	40010	120054	120054	120054	120054	120057
50024	120053	899	1	1	1	1	0	0	0	2	1	0	1	120038	119511	109510	25	60016	40014	10002	10000	30010	10000	10000	1079463	5736332	6133764	0	0	120029	0	120053	120053	113171	3	113692	50010	30020	10000	10000	60020	20000	10000	120053	120058	1	1	50021	10	9	10	40010	10000	10000	0	10	10002	2	1	10002	1	0	1	10000	0	1	1	1	1	0	3140	0	0	2	107	5	2	119668	40004	6	6	5	10000	40010	120054	120054	120054	120119	120054
50024	120053	900	1	0	1	1	0	0	0	11	0	0	1	120026	119511	109493	25	60016	40014	10002	10000	30010	10000	10000	1079575	5735750	6133764	0	0	120029	0	120053	120053	113171	22	113680	50010	30020	10000	10000	60020	20000	10000	120059	120053	1	1	50021	10	9	10	40010	10000	10000	0	10	10003	2	1	10002	0	1	4	10000	1	1	1	1	1	0	3140	0	0	4	107	5	2	119668	40004	6	6	0	10000	40010	120054	120587	120054	120079	120054

Test 3: Latency 1->3 roundtrip

Chain cycles: 3

Code:

  ldr q0, [x6, x7]
  fmov x0, d0
  eor x8, x8, x0
  eor x8, x8, x0
  add x7, x7, x8

Initialization

  mov x7, #4
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 9.0051

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk instruction (07)	mmu table walk data (08)	09	0e	0f	18	19	1e	1f	22	23	24	3a	3f	4d	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	69	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	ac	af	b5	l1d cache miss ld nonspec (bf)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
50205	120051	899	0	0	1	0	1	0	0	1	0	1	0	0	0	120036	119510	109464	25	60100	40102	10001	10000	30100	10000	10000	1079008	5736236	6134461	0	120029	0	120051	120051	113146	3	113668	50100	30200	10000	10000	60200	20000	10000	120055	120079	1	1	50201	100	99	100	40100	10000	10000	0	100	10000	0	1	10000	0	3	10000	1	1	0	3210	5	107	1	1	119658	40000	10	10	12	10000	40100	120052	120052	120052	120055	120052
50204	120051	899	0	0	0	0	0	0	0	1	0	1	0	0	0	120020	119493	109467	25	60103	40102	10000	10000	30100	10000	10000	1079035	5736380	6136317	0	120027	0	120035	120051	113141	3	113658	50100	30200	10000	10000	60200	20000	10000	120077	120051	1	1	50201	100	99	100	40100	10000	10000	0	100	10000	0	1	10000	0	0	10000	0	1	0	3210	1	107	1	1	119591	40000	13	10	0	10000	40100	120036	120052	120052	120052	120052
50204	120036	899	0	0	0	0	0	0	0	1	0	0	0	0	0	120020	119513	109449	25	60103	40100	10001	10000	30100	10000	10000	1079008	5736236	6134461	0	120011	0	120051	120035	113146	3	113668	50100	30200	10000	10000	60200	20000	10000	120073	120053	1	1	50201	100	99	100	40100	10000	10000	0	100	10000	0	1	10000	0	0	10000	1	1	0	3210	1	101	1	1	119646	40002	0	10	9	10000	40100	120052	120052	120052	120052	120052
50204	120054	899	0	0	0	0	0	0	0	1	0	1	0	0	0	120036	119510	109449	25	60103	40100	10001	10000	30100	10000	10000	1079008	5736380	6134461	1	120011	0	120051	120035	113146	3	113668	50100	30200	10000	10000	60200	20000	10000	120061	120051	1	1	50201	100	99	100	40100	10000	10000	0	100	10000	0	1	10000	0	0	10000	0	1	1	3210	2	107	1	1	119658	40002	10	10	0	10000	40100	120036	120055	120036	120055	120052
50204	120051	899	0	0	0	0	0	0	0	0	0	1	0	0	0	120036	119510	109464	25	60103	40102	10000	10000	30100	10000	10000	1079008	5736380	6136317	0	120027	0	120054	120051	113141	3	113668	50100	30200	10000	10000	60200	20000	10000	120055	120051	1	1	50201	100	99	100	40100	10000	10000	0	100	10000	0	1	10000	0	0	10000	0	0	0	3210	1	107	2	1	119646	40002	10	0	9	10000	40100	120563	120052	120052	120036	120052
50204	120051	899	0	0	0	0	1	0	0	0	0	1	0	0	0	120036	119513	109464	25	60100	40102	10001	10000	30100	10000	10000	1078862	5736236	6136317	0	120027	0	120035	120051	113146	3	113668	50100	30200	10000	10000	60200	20000	10000	120072	120055	1	1	50201	100	99	100	40100	10000	10000	0	100	10000	0	1	10000	1	54	10000	0	0	0	3210	1	101	1	1	119658	40024	13	10	0	10000	40100	120052	120052	120052	120052	120052
50204	120035	899	0	0	0	0	1	0	0	1	0	1	0	0	0	120036	119510	109464	25	60103	40102	10001	10000	30100	10000	10000	1079035	5735455	6136470	1	120030	0	120054	120035	113141	3	113668	50100	30200	10000	10000	60200	20000	10000	120083	120051	1	1	50201	100	99	100	40100	10000	10000	0	100	10000	0	1	10000	0	0	10000	1	1	0	3210	2	101	1	1	119646	40002	13	13	12	10000	40100	120036	120052	120052	120052	122262
50204	122289	915	0	1	0	0	0	17	13	3181	2112	0	0	0	0	122451	120538	110322	739	60449	40245	10049	10052	33666	11368	11181	1137841	5799015	6197198	0	120027	0	120054	120052	113141	3	113671	50100	32143	10737	10490	60200	20000	10000	120070	120056	15	1	50201	100	99	100	40100	10000	10000	0	100	10046	4	0	10000	0	0	10008	1	1	0	3210	1	117	1	1	119646	40002	13	10	9	10000	40100	120041	120036	120036	120052	120036
50204	120051	931	0	1	0	1	1	30	34	4225	2288	0	0	8	0	120020	119510	109449	25	60103	40100	10001	10000	30100	10000	10000	1079008	5735455	6136317	1	120027	0	120035	120051	113149	3	113668	50100	30200	10000	10000	60200	20000	10000	120042	120051	1	1	50201	100	99	100	40100	10000	10000	0	100	10000	0	1	10000	1	0	10000	1	1	0	3210	1	116	1	1	119661	40002	13	10	0	10000	40100	120052	120052	120036	120036	120036
50204	120035	899	0	0	0	1	1	0	0	0	0	0	1	0	0	120020	119513	109464	25	60103	40102	10001	10000	30100	10000	10000	1079008	5736236	6136317	1	120011	0	120051	120051	113146	3	113671	50100	30200	10000	10000	60200	20000	10000	120063	120051	1	1	50201	100	99	100	40100	10000	10000	0	100	10000	0	1	10000	0	3	10000	0	1	0	3210	1	173	1	3	119728	40000	10	10	0	10000	40100	120052	120052	120052	120039	120036

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 9.0047

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	09	l2 tlb miss data (0b)	0f	18	19	1e	1f	22	23	3f	4d	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	69	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	b5	l1d cache miss ld nonspec (bf)	c2	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	d9	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
50025	120049	899	0	0	0	0	0	0	1	0	1	0	120035	119505	109461	25	60013	40012	10001	10000	30010	10000	10000	1079517	5736188	6133499	1	120023	0	120050	120097	113153	3	113689	50010	30020	10000	10000	60020	20000	10000	120050	120047	1	1	50021	10	9	10	40010	10000	10000	0	10	10000	0	1	10000	0	0	0	0	10000	1	1	0	0	0	3140	4	140	1	5	5	119662	40002	0	6	8	10000	40010	120036	120051	120051	120036	120051
50024	120050	899	0	0	0	0	0	0	1	0	0	0	120032	119508	109463	46	60013	40012	10001	10000	30010	10060	10000	1079548	5736044	6133652	0	120011	0	120050	120050	113168	3	113689	50010	30020	10000	10000	60020	20000	10000	120035	120050	1	1	50021	10	9	10	40010	10000	10000	0	10	10000	0	1	10000	0	0	0	0	10000	1	1	0	0	0	3140	5	107	0	4	4	119662	40000	0	6	8	10000	40010	120036	120051	120051	120048	120051
50024	120050	899	0	0	0	0	0	0	1	0	0	0	120035	119492	109463	25	60013	40023	10000	10000	30010	10000	10000	1079548	5735455	6133499	0	120026	0	120035	120047	113153	3	113689	50010	30020	10000	10000	60020	20000	10000	120050	120050	1	1	50021	10	9	10	40010	10000	10000	1	10	10000	0	1	10000	0	0	0	0	10000	0	1	0	0	0	3140	4	107	0	5	5	119662	40002	9	0	8	10000	40010	120036	120036	120056	120051	120036
50024	120047	899	0	0	0	0	0	0	1	0	1	0	120020	119511	109463	25	60013	40012	10001	10000	30010	10000	10000	1079548	5735455	6132757	0	120023	0	120050	120050	113168	3	113689	50010	30020	10000	10000	60020	20212	10160	121033	120035	1	1	50021	10	9	10	40010	10000	10000	0	10	10000	0	0	10000	0	0	0	0	10000	0	1	0	0	0	3140	5	107	0	4	2	119665	40000	0	9	8	10000	40010	120051	120048	120051	120051	120048
50024	120047	899	0	0	0	0	0	0	6	0	0	0	120035	119513	109449	25	60010	40010	10000	10000	30010	10000	10000	1079548	5736188	6133652	0	120011	0	120035	120050	113168	3	113689	50010	30020	10000	10000	60020	20000	10000	120050	120047	1	1	50021	10	9	10	40010	10000	10000	0	10	10000	0	1	10000	0	0	0	0	10000	1	1	0	0	0	3140	4	107	1	4	5	119650	40002	9	0	8	10000	40010	120051	120051	120051	120048	120051
50024	120047	899	0	0	0	1	0	0	0	0	1	0	120035	119508	109463	25	60013	40012	10001	10000	30010	10060	10000	1079548	5736044	6132757	0	120026	0	120050	120035	113168	3	113689	50010	30020	10000	10000	60020	20000	10000	120035	120035	1	1	50021	10	9	10	40010	10000	10000	0	10	10000	0	0	10000	0	0	0	0	10000	1	1	0	0	0	3140	3	107	1	6	5	119665	40002	9	6	8	10000	40010	120036	120051	120048	120036	120051
50024	120050	899	0	0	0	0	0	0	0	0	0	0	120035	119508	109449	25	60010	40012	10000	10000	30010	10000	10000	1079548	5736188	6133499	0	120026	0	120047	120035	113153	3	113689	50010	30020	10000	10000	60020	20000	10000	120050	120047	1	1	50021	10	9	10	40010	10000	10000	0	10	10000	0	1	10000	0	0	0	0	10000	1	1	0	0	0	3140	5	107	0	2	3	119662	40002	9	6	8	10000	40010	120036	120036	120051	120036	120051
50024	120050	899	0	0	0	0	0	0	1	0	1	0	120020	119508	109506	25	60013	40012	10001	10000	30010	10000	10000	1079548	5736044	6134569	0	120026	0	120035	120047	113168	3	113689	50010	30020	10000	10000	60020	20000	10000	120050	120035	1	1	50021	10	9	10	40010	10000	10000	0	10	10000	0	0	10000	0	0	0	3	10000	1	1	0	0	0	3140	4	107	1	5	5	119665	40010	6	6	8	10000	40010	120036	120048	120048	120051	120051
50024	120047	899	0	0	0	0	0	0	1	0	0	0	120020	119492	109463	25	60013	40012	10001	10000	30010	10000	10000	1079523	5736044	6133499	1	120026	0	120035	120035	113168	3	113674	50010	30020	10000	10000	60020	20000	10000	120050	120047	1	1	50021	10	9	10	40010	10000	10000	0	10	10000	0	0	10000	0	0	0	0	10000	1	1	0	0	0	3140	3	107	1	5	5	119665	40000	6	9	0	10000	40010	120051	120051	120051	120036	120051
50024	120050	899	0	0	0	0	0	0	1	0	1	0	120035	119508	109463	25	60010	40010	10001	10000	30010	10000	10000	1079517	5736188	6133499	0	120011	0	120050	120047	113168	3	113689	50010	30020	10000	10000	60020	20000	10000	120035	120047	1	1	50021	10	9	10	40010	10000	10000	0	10	10000	0	0	10000	0	0	0	0	10000	0	1	0	0	0	3140	4	107	0	5	5	119650	40002	0	0	8	10000	40010	120051	120051	120051	120051	120036

Test 4: throughput

Count: 8

Code:

  ldr q0, [x6, x7]
  ldr q0, [x6, x7]
  ldr q0, [x6, x7]
  ldr q0, [x6, x7]
  ldr q0, [x6, x7]
  ldr q0, [x6, x7]
  ldr q0, [x6, x7]
  ldr q0, [x6, x7]

Initialization

  mov x7, 8

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.3342

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	09	l2 tlb miss data (0b)	0e	0f	18	1e	1f	22	24	3a	3f	43	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	a5	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
80205	26732	201	1	0	0	0	0	0	0	21	0	1	0	2	26699	0	18	0	0	25	80100	100	80000	100	80016	500	1166160	0	26689	26714	26732	16664	6	16688	80114	202	80024	200	160048	26720	26718	1	1	80201	100	99	100	100	80000	80000	0	100	80020	19	42	0	80057	0	0	1	21	80000	6	1	19	42	19	1	1	1	1	5118	0	16	0	0	26729	0	9	9	2	80000	100	26733	26715	26715	26733	26733
80204	26732	200	1	1	0	2	0	0	0	65	0	0	0	3	26717	0	18	18	15	25	80100	100	80000	100	80016	511	1169902	0	26707	26748	26732	16660	6	16666	80115	200	80024	200	160048	26884	26880	1	1	80201	100	99	100	100	80000	80000	0	100	80020	20	42	0	80057	1	0	3	21	80038	6	1	57	42	19	0	1	1	1	5118	0	16	0	0	26711	0	9	9	2	80000	100	26715	26733	26715	26733	26888
80204	26715	200	1	1	0	1	0	1	0	86	0	1	0	2	26724	2	18	0	1	25	80100	100	80000	100	80015	500	1167767	0	26690	26736	26736	16667	6	16684	80113	200	80024	200	160048	26836	26743	1	1	80201	100	99	100	100	80000	80000	0	100	80018	19	0	0	80018	0	0	0	59	80038	6	1	57	42	19	0	1	1	1	5118	0	16	0	0	26736	0	9	0	2	80000	100	26715	26733	26733	26715	26733
80204	26732	200	1	1	0	1	0	0	0	66	0	1	0	3	26717	2	0	0	19	25	80100	100	80000	100	80015	500	1169563	0	26689	26732	26733	16660	6	16666	80116	200	80024	200	160048	26724	26869	1	1	80201	100	99	100	100	80000	80000	0	100	80020	21	0	0	80057	1	1	0	62	80037	0	1	57	0	19	2	1	1	1	5118	0	16	0	0	26729	0	0	0	2	80000	100	26733	26715	26733	26733	26733
80204	26732	200	1	0	0	1	0	0	4	21	0	0	0	4	26699	2	18	18	15	25	80100	100	80000	100	80016	500	1167215	0	26707	26714	26732	16643	6	16667	80116	200	80024	200	160048	26739	26838	1	1	80201	100	99	100	100	80000	80000	0	100	80019	19	42	0	80019	0	1	0	21	80038	6	0	56	39	19	0	1	1	1	5118	0	16	0	0	26711	0	9	9	2	80000	100	26734	26734	26733	26733	26733
80204	26732	200	1	0	0	0	0	0	0	65	0	1	0	2	26699	0	18	18	16	25	80100	100	80000	100	80016	500	1166590	0	26689	26732	26732	16660	6	16684	80115	200	80024	200	160048	26740	26851	1	1	80201	100	99	100	100	80000	80000	0	100	80020	20	0	0	80019	0	0	1	63	80038	6	1	19	42	19	1	1	1	1	5118	0	16	0	0	26729	0	9	9	2	80000	100	26715	26733	26733	26733	26733
80204	26732	200	1	0	1	1	0	0	0	21	0	1	0	0	26718	0	0	18	16	25	80100	100	80000	100	80017	500	1169757	0	26689	26715	26732	16660	6	16666	80116	200	80024	202	160048	26714	26714	1	1	80201	100	99	100	100	80000	80000	0	100	80020	19	42	0	80057	0	0	0	60	80038	6	1	57	0	19	1	1	1	1	5118	0	16	0	0	26730	0	9	0	2	80000	100	26734	26715	26733	26733	26719
80204	26733	204	1	1	1	0	0	0	0	65	0	0	0	3	26717	2	18	18	14	25	80100	100	80000	100	80014	500	1166590	0	26689	26732	26733	16660	6	16684	80114	200	80024	200	160048	26737	26831	1	1	80201	100	99	100	100	80000	80000	0	100	80020	20	42	0	80057	0	0	0	59	80038	6	1	57	42	19	0	1	1	1	5118	0	16	0	0	26729	0	9	9	2	80000	100	26729	26733	26715	26734	26715
80204	26732	200	1	0	0	1	0	0	0	104	0	0	0	0	26717	2	0	18	3	25	80100	100	80000	100	80379	500	1168294	0	26707	26732	26714	16660	6	16689	80112	204	80024	200	160048	26736	26818	1	1	80201	100	99	100	100	80000	80000	0	100	80542	20	42	0	80057	0	0	0	59	80038	0	1	57	42	19	0	1	1	1	5117	0	16	0	0	26729	0	9	9	2	80000	100	26715	26734	26734	26734	26733
80204	26733	200	1	1	0	1	1	1	0	21	0	0	0	2	26699	2	18	0	17	25	80100	100	80000	100	80015	500	1167561	1	26708	26732	26714	16642	6	16666	80116	200	80024	200	160048	26723	26813	1	1	80201	100	99	100	100	80000	80000	1	100	80019	20	42	0	80057	1	0	0	59	80038	6	0	57	42	19	0	1	1	1	5118	0	16	0	0	26711	0	9	9	2	80000	100	26733	26715	26733	26733	26734

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.3342

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk instruction (07)	mmu table walk data (08)	09	l2 tlb miss data (0b)	0e	0f	1e	22	23	24	3a	3f	43	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	92	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	a5	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	cd	cf	d5	map dispatch bubble (d6)	db	dd	fetch restart (de)	df	e0	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
80025	26728	200	0	0	0	1	0	0	1	66	0	0	0	2	26721	2	7	7	19	25	80010	10	80000	10	80000	50	1171812	0	26713	26736	26715	16681	3	16717	80010	20	80000	20	160000	26749	26746	1	1	80021	10	9	0	10	10	80000	80000	0	10	80020	19	43	0	80059	1	0	0	61	80040	6	1	59	0	19	1	0	5043	2	32	0	1	1	0	26734	13	13	5	80000	10	26737	26715	26715	26716	26738
80024	26737	200	1	0	1	0	1	0	0	66	1	0	0	2	26721	3	7	7	19	25	80010	10	80000	10	80000	50	1168286	1	26711	26736	26736	16660	3	16717	80010	20	80000	20	160000	26736	26736	1	1	80021	10	9	0	10	10	80000	80000	0	10	80019	20	0	0	80059	0	0	0	64	80000	6	1	19	43	19	0	0	5020	1	16	0	1	1	0	26733	13	13	5	80000	10	26737	26738	26739	26737	26715
80024	26736	200	1	0	1	1	1	0	0	67	1	0	0	3	26700	3	7	7	20	25	80010	10	80000	10	80000	50	1167219	1	26690	26714	26736	16681	3	16716	80010	20	80000	20	160000	26741	26737	1	1	80021	10	9	0	10	10	80000	80000	0	10	80021	20	43	0	80059	0	0	1	21	80040	6	1	58	0	19	1	0	5020	1	16	0	1	1	0	26733	13	13	0	80000	10	26738	26716	26738	26738	26737
80024	26736	200	1	0	0	1	1	0	0	67	1	0	0	3	26721	3	7	7	19	25	80010	10	80000	10	80000	50	1168286	1	26711	26736	26736	16682	3	16717	80010	20	80000	20	160000	26744	26737	1	1	80021	10	9	0	10	10	80000	80000	0	10	80019	20	0	0	80059	1	0	0	61	80040	6	1	59	45	19	0	0	5022	5	16	0	5	1	0	26734	0	13	5	80000	10	26737	26737	26737	26737	26738
80024	26737	200	1	0	1	1	1	0	0	67	1	0	0	3	26721	1	7	0	19	25	80010	10	80000	10	80000	50	1173975	1	26711	26737	26737	16662	3	16695	80010	20	80000	20	160000	26746	26736	1	1	80021	10	9	0	10	10	80000	80000	0	10	80019	19	43	0	80060	1	0	1	64	80039	6	1	58	45	19	1	0	5020	1	16	0	1	1	0	26712	0	13	5	80000	10	26715	26748	26737	26737	26737
80024	26736	200	1	0	1	0	1	0	0	21	0	0	0	3	26700	2	7	7	21	25	80010	10	80000	10	80000	50	1167791	0	26711	26714	26737	16682	3	16717	80010	20	80000	20	160000	26742	26737	1	1	80021	10	9	0	10	10	80000	80000	0	10	80021	20	43	0	80058	0	0	0	60	80040	0	1	58	43	19	0	0	5020	1	16	0	1	1	0	26712	13	13	5	80000	10	26737	26738	26739	26716	26738
80024	26737	200	1	1	1	1	1	0	0	67	1	0	0	3	26721	2	7	7	19	25	80010	10	80000	10	80000	50	1170622	0	26690	26736	26737	16681	3	16694	80010	20	80000	20	160000	26743	26736	1	1	80021	10	9	0	10	10	80000	80000	0	10	80021	19	43	0	80059	1	0	2	61	80041	6	0	60	45	19	0	0	5020	1	16	0	1	1	0	26733	13	13	5	80000	10	26738	26716	26738	26738	26738
80024	26736	200	1	0	1	0	1	0	0	21	1	0	0	3	26722	2	7	7	0	25	80010	10	80000	10	80000	50	1167219	0	26711	26737	26736	16681	3	16716	80010	20	80000	20	160000	26755	26737	1	1	80021	10	9	0	10	10	80000	80000	0	10	80020	19	43	0	80059	1	1	1	63	80040	0	1	59	43	19	1	0	5020	1	16	0	1	1	0	26733	13	13	5	80000	10	26737	26716	26738	26738	26715
80024	26736	201	1	0	1	1	1	0	0	69	1	0	0	2	26722	2	7	7	19	25	80010	10	80000	10	80000	50	1167106	0	26711	26737	26714	16681	3	16716	80010	20	80000	20	160000	26748	26736	1	1	80021	10	9	0	10	10	80000	80000	0	10	80021	21	43	0	80019	1	0	1	61	80040	6	1	58	43	19	1	0	5020	1	16	0	1	1	0	26733	13	13	5	80000	10	26737	26737	26737	26737	26737
80024	26737	200	1	0	1	1	1	0	0	67	1	0	0	3	26723	3	0	7	20	25	80010	10	80000	10	80000	50	1167219	0	26711	26737	26714	16659	3	16695	80010	20	80000	20	160000	26756	26736	1	1	80021	10	9	0	10	10	80000	80000	0	10	80020	19	43	0	80060	1	0	0	61	80040	0	1	58	44	19	1	0	5020	1	16	0	1	1	0	26734	13	0	5	80000	10	26738	26738	26715	26738	26737

LDR (register, Q)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->2 roundtrip

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: Latency 1->3 roundtrip

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 4: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations