Firestorm: LDR (register, S) measurements

Code:

  ldr s0, [x6, x7]

Initialization

  mov x7, #4
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 1.000

SIMD/FP unit issues: 0.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	09	l2 tlb miss data (0b)	0e	0f	1e	22	3a	3f	43	46	49	4f	51	schedule uop (52)	schedule ldst uop (55)	dispatch ldst uop (58)	simd uops in schedulers (5a)	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map ldst uop (7d)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst simd load (98)	inst ldst (9b)	9d	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	ea	eb	ec	? ldst retires (ed)	f5	f6	f7	f8	fd
1005	389	2	0	0	1	0	0	0	41	1	2	384	2	18	18	12	25	1000	1000	1000	14844	364	399	391	211	3	247	1000	1000	2000	389	392	1	1	1001	1000	1000	1	1000	0	39	1035	0	35	1035	6	1	35	39	73	1	16	1	1	386	6	6	2	1000	400	400	400	399	400
1004	399	2	1	0	0	1	0	0	65	1	3	384	2	18	18	16	25	1000	1000	1000	15362	373	398	398	221	3	257	1000	1000	2000	398	399	1	1	1001	1000	1000	0	1000	0	39	1035	0	35	1035	6	1	35	39	73	1	16	1	1	386	6	6	2	1000	399	400	400	399	400
1004	399	3	1	0	0	1	0	1	65	0	3	384	3	18	18	16	25	1000	1000	1000	15315	373	399	398	222	3	256	1000	1000	2000	398	399	1	1	1001	1000	1000	0	1000	0	39	1035	0	35	1035	6	1	35	39	73	1	16	1	1	388	6	6	2	1000	399	400	400	399	400
1004	399	3	1	0	0	0	0	0	65	0	3	383	1	18	18	11	25	1000	1000	1000	14838	364	389	389	212	3	247	1000	1000	2000	389	389	1	1	1001	1000	1000	0	1000	0	39	1035	0	35	1035	6	1	35	39	73	1	16	1	1	386	6	6	2	1000	400	400	400	399	400
1004	399	3	1	1	0	1	0	0	65	0	3	384	2	18	18	12	25	1000	1000	1000	14838	364	389	389	212	3	247	1000	1000	2000	389	391	1	1	1001	1000	1000	0	1000	0	39	1036	0	35	1035	6	1	35	39	73	1	16	1	1	386	6	6	2	1000	390	390	390	391	390
1004	391	2	0	0	0	0	0	0	41	0	1	374	2	18	18	12	25	1000	1000	1000	14838	364	389	389	212	3	247	1000	1000	2000	389	389	1	1	1001	1000	1000	0	1000	0	39	1035	0	35	1035	6	1	35	39	73	1	16	1	1	386	6	6	2	1000	390	390	390	390	390
1004	389	2	0	0	0	0	0	0	41	0	1	374	2	18	18	11	25	1000	1000	1000	14838	364	391	389	212	3	247	1000	1000	2000	389	389	1	1	1001	1000	1000	0	1000	0	39	1035	0	35	1035	6	1	35	39	73	1	16	1	1	386	6	6	2	1000	420	401	399	399	400
1004	399	3	1	1	0	0	0	0	66	1	3	384	2	18	18	12	25	1000	1000	1000	14838	364	389	389	212	3	247	1000	1000	2000	389	389	1	1	1001	1000	1000	0	1000	0	39	1035	0	35	1035	6	1	35	39	73	1	16	1	1	386	6	6	2	1000	400	400	400	400	399
1004	398	3	1	0	0	0	0	0	65	0	3	383	2	18	18	12	25	1000	1000	1000	14838	364	389	389	212	3	247	1000	1000	2000	389	389	1	1	1001	1000	1000	0	1000	0	39	1035	0	35	1035	6	1	35	39	73	1	16	1	1	386	6	6	4	1000	392	390	390	390	390
1004	389	3	0	0	0	0	0	0	41	0	1	374	2	18	18	12	25	1000	1000	1000	14838	364	390	394	217	3	252	1000	1000	2000	394	389	1	1	1001	1000	1000	1	1000	0	39	1035	0	40	1035	6	1	39	43	73	1	16	1	1	391	6	10	4	1000	400	399	400	400	399

Test 2: Latency 1->2 roundtrip

Chain cycles: 3

Code:

  ldr s0, [x6, x7]
  fmov x0, d0
  eor x8, x8, x0
  eor x8, x8, x0
  add x6, x6, x8

Initialization

  mov x7, #4
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 9.0051

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk instruction (07)	mmu table walk data (08)	09	l2 tlb miss instruction (0a)	l2 tlb miss data (0b)	0e	0f	18	19	1e	1f	22	23	24	3a	3f	4d	4f	50	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	int prf full (71)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	b5	l1d cache miss ld nonspec (bf)	c2	cd	cf	d0	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
50205	120051	899	0	0	0	0	0	0	0	0	0	1	0	0	0	0	0	120036	119513	109467	1	25	60103	40102	10001	10000	30100	10000	10000	1079035	5736380	6136317	0	120027	120054	120051	113141	0	3	113658	50100	30200	10000	10000	60200	20000	10000	120051	120051	1	1	50201	100	99	100	40100	10000	10000	0	100	10000	0	1	10000	0	0	0	0	10000	1	1	0	0	3210	0	1	107	1	1	119661	40002	13	10	12	10000	40100	120036	120036	120055	120103	120055
50204	120054	899	0	0	0	0	0	0	0	0	0	10	0	0	0	0	0	120020	119510	109464	0	25	60103	40102	10001	10000	30100	10000	10000	1079035	5736380	6136317	0	120011	120035	120054	113141	0	3	113658	50100	30200	10000	10000	60200	20000	10000	120054	120051	1	1	50201	100	99	100	40100	10000	10000	0	100	10000	0	1	10000	0	0	0	0	10000	1	0	0	0	3210	0	1	107	1	1	119646	40000	13	10	12	10000	40100	120052	120055	120052	120055	120052
50204	120054	899	0	0	0	0	0	0	0	0	0	6	0	1	0	0	0	120039	119510	109467	0	25	60103	40102	10001	10000	30100	10000	10000	1079035	5735455	6136470	0	120030	120054	120035	113146	0	3	113658	50100	30200	10000	10000	60200	20000	10000	120054	120051	1	1	50201	100	99	100	40100	10000	10000	0	100	10000	0	1	10000	0	7	0	0	10000	1	0	0	0	3210	0	2	101	1	1	119661	40002	13	0	12	10000	40100	120055	120036	120052	120036	120051
50204	120039	899	0	0	0	0	0	0	0	0	0	1	0	1	0	0	0	120039	119513	109467	0	25	60103	40102	10001	10000	30100	10000	10000	1079035	5736332	6136317	0	120027	120054	120054	113141	0	3	113671	50100	30200	10000	10000	60200	20000	10000	120054	120052	1	1	50201	100	99	100	40100	10000	10000	0	100	10001	0	1	10000	0	0	0	0	10000	1	1	0	0	3210	0	1	107	1	1	119661	40000	10	0	12	10000	40100	120055	120055	120036	120052	120053
50204	120054	899	0	0	0	0	0	0	0	0	0	6	0	0	0	0	0	120039	119513	109449	0	25	60158	40121	10002	10000	30100	10000	10000	1079116	5737004	6136317	0	120027	120054	120282	113141	0	3	113668	50100	30200	10000	10000	60200	20000	10000	120054	120035	1	1	50201	100	99	100	40100	10000	10000	0	100	10000	0	0	10000	0	0	0	0	10000	1	1	0	0	3210	0	1	107	1	1	119661	40002	0	0	0	10000	40100	120055	120036	120055	120055	120055
50204	120035	899	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	120020	119493	109467	0	25	60103	40102	10001	10000	30100	10000	10000	1078862	5735455	6134461	0	120030	120054	120051	113146	0	3	113671	50100	30200	10000	10063	60200	20126	10000	120054	120066	1	1	50201	100	99	100	40100	10000	10000	0	100	10000	0	1	10000	0	5	0	0	10000	1	0	0	0	3210	0	1	107	1	1	119664	40000	13	0	12	10000	40100	120052	120058	120055	120055	120052
50204	120054	930	0	0	0	0	0	0	0	0	0	1	0	0	0	0	0	120039	119493	109467	0	25	60103	40102	10001	10000	30100	10000	10000	1079035	5736236	6134461	0	120030	120035	120054	113146	0	3	113658	50100	30200	10000	10000	60200	20000	10000	120054	120035	1	1	50201	100	99	100	40100	10000	10000	0	100	10000	0	1	10000	0	5	0	0	10000	1	1	0	0	3210	0	1	107	1	1	119646	40002	0	13	0	10000	40100	120055	120036	120052	120052	120059
50204	120054	899	0	0	0	0	0	0	0	0	0	1	0	0	0	0	0	120036	119510	109467	0	25	60103	40100	10001	10000	30100	10000	10000	1079035	5736380	6134461	0	120030	120037	120053	113146	0	3	113671	50100	30200	10000	10000	60200	20000	10000	120051	120101	1	1	50201	100	99	100	40100	10000	10000	0	100	10000	0	1	10000	0	5	0	3	10000	1	1	0	0	3210	0	1	101	2	1	119647	40002	0	13	9	10000	40100	120036	120055	120036	120058	120052
50204	120054	899	0	0	0	0	0	1	0	0	0	1	0	1	0	0	0	120039	119513	109449	0	25	60103	40102	10001	10000	30100	10000	10000	1079008	5735455	6136317	0	120030	120035	120035	113141	0	3	113658	50100	30200	10000	10000	60200	20000	10000	120054	120051	1	1	50201	100	99	100	40100	10000	10000	0	100	10000	0	0	10000	0	4	0	0	10000	0	1	0	0	3210	0	1	107	1	1	119661	40002	0	0	0	10000	40100	120052	120055	120052	120036	120052
50204	120035	899	0	0	0	0	0	0	0	0	0	1	0	0	0	0	0	120039	119513	109467	0	135	60103	40102	10001	10000	30100	10000	10000	1079035	5736236	6136317	0	120030	120054	120055	113146	0	3	114083	56400	33456	11339	11292	68275	22678	11294	122495	122417	28	1	50201	100	99	100	40100	10000	10000	0	100	10036	0	0	10035	1	6	2	92073	10039	1	1	0	0	3941	0	2	314	1	1	119658	40010	13	13	12	10000	40100	121172	121491	121263	120887	122288

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 9.0058

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk instruction (07)	mmu table walk data (08)	09	l2 tlb miss instruction (0a)	l2 tlb miss data (0b)	0e	0f	18	19	1e	1f	22	23	3a	3f	4d	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	b5	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
50025	120057	900	1	0	1	0	0	1	0	0	0	0	2	0	1	0	0	120026	119499	109470	25	60016	40012	10002	10000	30010	10000	10000	1079917	5735798	6134172	1	120017	120060	120060	113175	3	113680	50010	30020	10000	10000	60020	20000	10000	120057	120041	1	1	50021	10	9	10	40010	10000	10000	1	10	10002	1	1	10001	0	0	1	1	10000	1	1	0	1	1	3140	3	107	3	2	119672	40004	13	10	9	10000	40010	120061	120042	120058	120061	120042
50024	120060	899	1	0	1	0	0	1	0	1	0	0	2	0	0	0	0	120098	119518	109455	25	60016	40014	10003	10000	30010	10000	10000	1079922	5737484	6134280	1	120017	120060	120041	113159	3	113680	50010	30020	10000	10000	60020	20000	10000	120041	120041	1	1	50021	10	9	10	40010	10000	10000	0	10	10009	3	1	10002	0	0	0	4	10000	1	1	1	1	2	3140	2	107	2	2	119675	40004	0	0	12	10000	40010	120061	120061	120042	120042	120061
50024	120041	900	1	0	1	0	0	0	0	0	0	0	1	0	0	0	1	120045	119499	109473	25	60016	40012	10002	10000	30010	10000	10000	1079742	5736668	6134121	1	120036	120041	120060	113159	3	113699	50010	30020	10000	10000	60020	20000	10000	120041	120057	1	1	50021	10	9	10	40010	10000	10000	0	10	10002	2	1	10001	0	0	1	4	10000	1	1	0	1	1	3140	2	107	2	2	119656	40004	0	13	12	10000	40010	120042	120061	120061	120061	120042
50024	120060	899	1	0	1	0	0	0	1	1	0	0	7	0	0	0	1	120026	119518	109473	25	60013	40014	10001	10000	30010	10000	10000	1079674	5745201	6136864	1	120017	120060	120057	113175	3	113696	50494	30020	10000	10000	60020	20000	10000	120060	120041	1	1	50021	10	9	10	40010	10000	10000	0	10	10002	1	0	10002	0	0	1	1	10000	0	1	1	1	0	3140	1	107	2	2	119675	40004	0	0	12	10000	40010	120042	120061	120061	120061	120061
50024	120060	899	1	0	0	0	0	1	0	1	0	0	2	0	0	0	0	120045	119515	109473	25	60016	40014	10002	10000	30010	10000	10055	1079553	5736572	6133968	1	120039	120060	120060	113175	3	113680	50010	30020	10000	10000	60020	20000	10000	120061	120091	1	1	50021	10	9	10	40010	10000	10000	1	10	10002	1	1	10001	0	0	0	1	10000	1	1	1	1	0	3140	2	107	2	2	119656	40004	10	10	0	10000	40010	120061	120061	120061	120061	120061
50024	120110	900	1	0	1	0	0	0	0	0	0	0	1	0	1	0	0	120045	119499	109473	25	60016	40014	10004	10000	30010	10000	10000	1079683	5736524	6133968	1	120017	120060	120041	113178	3	113680	50010	30020	10000	10000	60020	20000	10000	120057	120057	1	1	50021	10	9	10	40010	10000	10000	0	10	10002	1	1	10001	0	0	1	1	10000	1	1	1	1	0	3140	3	107	2	2	119656	40004	13	10	0	10000	40010	120042	120061	120042	120042	120058
50024	120041	900	1	0	0	0	0	0	0	0	0	0	2	0	1	0	0	120026	119518	109473	25	60013	40012	10001	10000	30010	10000	10000	1079755	5736812	6133968	1	120036	120041	120060	113178	3	113702	50010	30020	10000	10000	60020	20000	10000	120060	120057	1	1	50021	10	9	10	40010	10000	10000	0	10	10001	1	1	10003	0	0	0	1	10000	1	1	1	1	0	3140	2	107	2	2	119656	40004	10	10	0	10000	40010	120042	120058	120061	120058	120061
50024	120118	899	1	0	1	0	0	1	0	0	0	0	2	0	0	0	0	120045	119518	109473	25	60016	40014	10002	10000	30010	10000	10000	1079679	5736860	6133968	1	120036	120060	120060	113159	3	113699	50010	30020	10000	10000	60020	20000	10000	120060	120057	1	1	50021	10	9	10	40010	10000	10000	0	10	10003	2	1	10002	0	0	1	79	10000	1	1	0	1	0	3140	2	107	2	2	119675	40004	10	0	9	10000	40010	120061	120061	120061	120058	120061
50024	120102	899	1	0	0	0	0	1	1	0	0	0	1	0	1	0	0	120045	119518	109473	25	60016	40014	10002	10000	30010	10000	10000	1088807	5736668	6134740	1	120036	120057	120041	113178	3	113747	50010	30020	10000	10000	60020	20000	10000	120060	120041	1	1	50021	10	9	10	40010	10000	10000	0	10	10001	1	1	10002	0	0	0	256	10000	0	1	1	1	0	3140	2	107	2	3	119672	40004	10	0	12	10000	40010	120061	120061	120058	120061	120042
50024	120057	899	1	0	0	0	0	1	0	0	0	0	1	0	1	0	0	120026	119499	109520	25	60013	40014	10002	10000	30010	10000	10000	1079674	5736524	6133216	1	120033	120060	120057	113178	3	113680	50010	30020	10000	10000	60020	20000	10000	120057	120057	1	1	50021	10	9	10	40010	10000	10000	0	10	10001	3	1	10002	0	0	1	64	10000	1	1	0	1	1	3140	2	107	2	2	119672	40004	13	0	12	10000	40010	120042	120042	120043	120042	120058

Test 3: Latency 1->3 roundtrip

Chain cycles: 3

Code:

  ldr s0, [x6, x7]
  fmov x0, d0
  eor x8, x8, x0
  eor x8, x8, x0
  add x7, x7, x8

Initialization

  mov x7, #4
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 9.0054

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk instruction (07)	mmu table walk data (08)	09	l2 tlb miss instruction (0a)	l2 tlb miss data (0b)	0e	0f	18	19	1e	1f	22	23	3a	3f	4d	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	b5	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
50205	120057	899	1	0	1	0	0	1	1	0	0	0	2	0	1	0	0	120045	119520	109473	25	60106	40102	10002	10000	30100	10000	10000	1079089	5735750	6136623	1	120036	120041	120060	113155	3	113630	50100	30200	10000	10000	60200	20000	10000	120060	120057	1	1	50201	100	99	100	40100	10000	10000	1	100	10002	1	1	10003	0	0	1	1	10000	1	1	1	1	0	3210	1	107	1	1	119646	40002	13	10	9	10000	40100	120058	120042	120061	120061	120061
50204	120041	900	0	0	0	0	0	0	0	0	0	0	1	0	1	0	0	120040	119740	109501	25	60103	40100	10001	10000	30100	10000	10000	1078862	5736380	6134461	1	120027	120054	120035	113146	3	113658	50100	30200	10000	10000	60200	20000	10000	120054	120051	1	1	50201	100	99	100	40100	10000	10000	0	100	10003	1	1	10001	0	0	1	7	10000	1	1	1	1	2	3210	1	107	1	1	119664	40002	13	0	12	10000	40100	120058	120061	120061	120042	120058
50204	120057	899	1	0	0	0	0	0	0	0	0	0	2	0	0	0	0	120045	119513	109467	25	60103	40100	10001	10000	30100	10000	10000	1079035	5736380	6136317	1	120036	120060	120060	113137	3	113630	50100	30200	10000	10000	60200	20000	10000	120060	120107	1	1	50201	100	99	100	40100	10000	10000	1	100	10000	0	1	10000	0	0	0	0	10000	1	0	1	0	0	3210	1	107	1	1	119658	40004	13	10	0	10000	40100	120058	120058	120061	120042	120061
50204	120041	899	1	0	1	1	0	1	0	0	0	0	1	0	0	0	1	120045	119493	109467	25	60100	40102	10001	10000	30100	10000	10000	1079035	5736380	6136317	1	120030	120054	120054	113141	3	113671	50100	30200	10000	10000	60200	20000	10000	120054	120051	1	1	50201	100	99	100	40100	10000	10000	0	100	10000	0	0	10000	0	0	0	0	10000	0	0	0	0	0	3210	1	101	1	1	119661	40000	10	10	0	10000	40100	120042	120042	120058	120058	120061
50204	120060	899	1	0	0	1	1	0	0	0	0	0	2	0	0	0	0	120045	119513	109467	25	60100	40102	10001	10000	30100	10000	10000	1079008	5735455	6134461	1	120030	120035	120051	113149	3	113677	50100	30200	10000	10000	60200	20000	10000	120057	120057	1	1	50201	100	99	100	40100	10000	10000	0	100	10000	0	1	10000	0	0	0	0	10000	1	0	0	0	0	3210	2	107	1	1	119646	40000	13	13	12	10000	40100	120061	120061	120061	120042	120061
50204	120060	900	1	0	0	1	0	1	0	0	0	0	2	0	0	0	0	120026	119513	109449	25	60100	40100	10001	10000	30100	10000	10000	1079035	5736380	6136317	1	120011	120054	120035	113149	3	113671	50100	30200	10000	10000	60200	20000	10000	120051	120035	1	1	50201	100	99	100	40100	10000	10000	0	100	10000	0	1	10001	0	0	0	0	10000	1	0	0	0	0	3210	1	107	1	1	119661	40002	0	13	9	10000	40100	120042	120061	120061	120042	120061
50204	120041	899	1	0	0	0	0	0	0	0	0	0	1	0	1	0	0	120045	119516	109473	25	60106	40102	10002	10000	30100	10000	10000	1079089	5736668	6136623	1	120033	120057	120057	113152	3	113674	50100	30200	10000	10000	60200	20000	10000	120060	120041	1	1	50201	100	99	100	40100	10000	10000	0	100	10001	2	1	10003	0	0	0	1	10000	0	1	1	1	0	3210	1	107	1	1	119654	40004	0	0	0	10000	40100	120058	120061	120042	120042	120061
50204	120041	899	1	0	1	1	0	0	0	0	0	0	2	0	0	0	0	120026	119513	109455	25	60103	40102	10002	10000	30100	10000	10000	1079467	5735942	6136623	1	120033	120060	120057	113137	3	113630	50100	30200	10000	10000	60200	20000	10000	120060	120057	1	1	50201	100	99	100	40100	10000	10000	0	100	10032	1	1	10034	1	8	3	89339	10034	1	1	0	1	0	3945	1	307	2	2	121579	40234	10	13	12	10000	40100	122638	122581	122502	122452	122518
50204	120041	899	1	0	0	0	0	1	0	0	0	0	3047	2112	1	0	0	123038	121101	110542	713	60543	40408	10056	10060	34532	11266	11526	1145447	5799822	6208728	1	122244	122876	123548	114183	3	113677	50100	30200	10054	10000	64742	20000	11733	123472	122699	33	1	50201	100	99	100	40100	10000	10000	1	100	10055	4	0	10048	0	0	0	134771	10050	1	1	1	1	0	3210	1	300	1	1	121775	40337	13	10	0	10000	40100	120062	120042	120061	120042	122142
50204	122744	954	1	0	2	2	0	0	0	0	26	28	3701	1760	0	0	0	120045	119513	109470	25	60106	40104	10002	10000	30100	10000	10000	1079089	5736860	6136623	1	120017	120041	120060	113155	3	113630	50100	30200	10000	10000	60200	20000	10000	120041	120041	1	1	50201	100	99	100	40100	10000	10000	0	100	10000	0	1	10000	0	1	0	0	10000	1	0	1	0	0	3210	1	101	1	1	119658	40000	13	10	0	10000	40100	120055	120036	120055	120055	120055

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 9.0047

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1i tlb fill (04)	mmu table walk data (08)	09	l2 tlb miss instruction (0a)	0e	0f	1e	1f	22	23	24	3f	4d	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	int prf full (71)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	ac	af	b5	l1d cache miss ld nonspec (bf)	c2	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	l1i tlb miss demand (d4)	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
50025	120051	899	0	0	0	0	0	0	10	88	1	0	0	120322	119536	109464	25	60013	40010	10001	10000	30010	10000	10000	1079557	5736236	6132757	0	120027	120051	120051	113169	0	3	113691	50010	30020	10000	10000	60020	20000	10000	120051	120051	1	1	50021	10	9	10	40010	10000	10000	0	10	10000	1	10000	2	0	10000	1	1	0	2	0	0	3140	0	5	107	5	4	119666	40011	10	0	9	10000	40010	120070	120149	120052	120052	120052
50024	120051	899	1	0	1	0	1	0	1	0	1	0	0	120036	119510	109513	25	60026	40012	10001	10000	30010	10000	10057	1079557	5735455	6133662	0	120027	120051	120051	113153	0	3	113690	50010	30020	10000	10000	60020	20000	10000	120035	120035	1	1	50021	10	9	10	40010	10000	10000	1	10	10000	1	10000	0	3	10000	1	0	0	0	0	0	3141	1	5	107	5	5	119666	40000	10	0	0	10000	40010	120073	120057	120036	120052	120052
50024	120051	899	1	0	1	0	0	0	1	0	0	0	0	120036	119509	109464	25	60013	40010	10001	10000	30010	10000	10000	1079557	5736236	6133662	0	120027	120051	120051	113169	0	3	113690	50010	30020	10000	10000	60020	20000	10000	120051	120051	1	1	50021	10	9	10	40010	10000	10000	0	10	10000	1	10000	0	0	10000	1	1	0	0	0	0	3141	1	4	107	6	5	119666	40002	10	10	9	10000	40010	120056	120052	120036	120052	120039
50024	120054	899	1	0	1	0	0	0	1	0	1	0	0	120036	119509	109464	25	60010	40012	10001	10000	30010	10000	10000	1079557	5736236	6133662	0	120027	120035	120051	113169	0	3	113690	50010	30020	10000	10000	60020	20000	10000	120051	120051	1	1	50021	10	9	10	40010	10000	10000	0	10	10000	1	10000	0	0	10000	1	1	0	0	0	0	3141	1	5	107	5	6	119666	40000	0	0	9	10000	40010	120073	120055	120036	120052	120052
50024	120051	899	1	0	1	0	0	0	0	0	1	0	0	120036	119509	109449	25	60013	40010	10000	10000	30010	10000	10055	1079557	5736236	6133662	0	120027	120051	120051	113171	0	3	113690	50010	30020	10000	10000	60020	20000	10000	120035	120054	2	1	50021	10	9	10	40010	10000	10000	0	10	10000	0	10000	0	0	10000	1	0	0	0	0	0	3141	1	5	107	5	5	119666	40002	10	10	9	10000	40010	120060	120053	120052	120052	120052
50024	120035	900	1	0	1	0	0	0	1	0	0	0	0	120036	119528	109464	25	60013	40012	10001	10000	30010	10000	10000	1079557	5736236	6132757	0	120027	120051	120051	113169	0	3	113674	50010	30020	10000	10000	60020	20000	10000	120051	120051	1	1	50021	10	9	10	40010	10000	10000	0	10	10000	1	10000	0	0	10000	1	1	0	0	0	0	3141	1	5	107	5	5	119666	40002	10	10	0	10000	40010	120068	120052	120052	120052	120052
50024	120051	899	1	0	1	0	0	0	0	0	1	0	0	120036	119509	109464	25	60013	40012	10001	10000	30010	10000	10000	1079557	5736236	6132757	0	120011	120035	120051	113169	0	3	113690	50010	30020	10000	10000	60020	20000	10000	120051	120051	1	1	50021	10	9	10	40010	10000	10000	0	10	10000	1	10000	0	0	10000	1	1	0	0	0	0	3140	0	5	107	5	6	119666	40002	10	10	0	10000	40010	120073	120053	120102	120052	120056
50024	120051	899	1	0	1	0	0	0	1	0	1	0	0	120036	119509	109464	25	60010	40012	10001	10000	30010	10061	10000	1079557	5736236	6132757	0	120030	120051	120051	113153	0	3	113690	50010	30020	10000	10000	60020	20000	10000	120051	120051	1	1	50021	10	9	10	40010	10000	10000	0	10	10000	1	10000	0	0	10000	0	1	0	1	0	0	3140	0	5	38	5	5	119666	40002	10	0	0	10000	40010	120067	120053	120052	120052	120036
50024	120035	899	1	0	1	0	0	0	6	0	1	0	0	120020	119509	109464	25	60013	40010	10000	10000	30010	10000	10000	1079557	5736236	6132757	0	120027	120051	120035	113153	0	3	113690	50010	30020	10000	10000	60020	20000	10000	120051	120052	1	1	50021	10	9	10	40010	10000	10000	0	10	10000	1	10000	0	0	10000	0	1	0	0	0	0	3141	1	5	107	6	5	119666	40002	10	10	9	10000	40010	120088	120060	120052	120052	120052
50024	120035	899	1	0	1	0	0	0	0	0	1	0	0	120037	119509	109464	46	60013	40012	10001	10000	30010	10000	10000	1081542	5738012	6134279	0	120027	120054	120051	113153	0	3	113674	50010	30020	10000	10000	60020	20108	10218	120051	120051	1	1	50021	10	9	10	40010	10000	10000	1	10	10010	1	10000	0	15	10006	1	1	0	0	0	0	3224	1	6	144	7	5	119752	40026	10	10	9	10000	40010	120052	120053	120052	120058	120053

Test 4: throughput

Count: 8

Code:

  ldr s0, [x6, x7]
  ldr s0, [x6, x7]
  ldr s0, [x6, x7]
  ldr s0, [x6, x7]
  ldr s0, [x6, x7]
  ldr s0, [x6, x7]
  ldr s0, [x6, x7]
  ldr s0, [x6, x7]

Initialization

  mov x7, 8

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.3341

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	0e	18	19	1e	22	3a	3f	43	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
80205	26733	200	0	0	0	0	1	3	26725	2	18	12	85	71	80100	100	80130	102	80016	500	1166596	1	26682	26722	26722	16650	6	16674	80115	200	80024	200	160048	26722	26722	1	1	80201	100	99	100	100	80000	80000	1	100	80000	0	39	80039	0	0	35	80039	6	1	35	39	1	1	1	5118	0	16	0	0	26731	6	0	0	80000	100	26728	26728	26728	26728	26728
80204	26722	200	0	0	0	41	0	0	26692	0	12	12	0	25	80100	100	80000	100	80014	500	1167303	1	26702	26727	26722	16635	6	16679	80115	200	80024	200	160048	26729	26722	1	1	80201	100	99	100	100	80000	80000	0	100	80000	0	39	80000	1	0	39	80035	6	0	35	43	1	1	1	5118	0	16	0	1	26723	10	0	2	80000	100	26708	26728	26728	26723	26728
80204	26722	200	0	0	0	12	1	2	26725	2	12	0	20	25	80100	100	80000	100	80015	500	1177116	1	26702	26728	26707	16655	6	16679	80114	200	80024	200	160048	26727	26722	1	1	80201	100	99	100	100	80000	80000	0	100	80000	0	39	80039	0	0	45	80039	6	0	0	0	1	1	1	5118	1	16	0	0	26727	6	10	4	80000	100	26735	26873	26739	26728	26725
80204	26727	200	1	1	1	54	1	0	26716	3	18	18	18	25	80100	100	80000	100	80014	500	1166596	1	26682	26727	26727	16654	6	16659	80115	200	80024	200	160048	26727	26722	1	1	80201	100	99	100	100	80000	80000	0	100	80000	0	39	80039	0	0	3	80000	0	1	35	39	2	2	2	5129	1	23	1	1	26724	10	10	4	80000	100	26723	26729	26709	26713	26723
80204	26708	200	0	0	0	41	0	2	26707	2	0	18	16	25	80100	100	80000	100	80021	500	1166714	1	26686	26727	26708	16648	10	16668	80121	200	80030	200	160060	26727	26727	1	1	80201	100	99	100	100	80000	80000	0	100	80000	0	39	80039	0	0	39	80039	0	0	35	43	2	2	2	5128	1	23	1	1	26724	8	6	2	80000	100	26709	26723	26709	26723	26728
80204	26708	199	0	0	0	57	1	2	26717	2	18	12	12	25	80100	100	80000	100	80200	500	1166108	1	26702	26727	26722	16645	9	16666	80119	200	80030	200	160060	26727	26722	1	1	80201	100	99	100	100	80000	80000	0	100	80000	0	39	80000	0	0	35	80000	6	1	39	43	2	2	2	5129	1	23	1	1	26719	0	10	4	80000	100	26728	26724	26723	26723	26723
80204	26727	200	0	0	0	45	0	0	26712	2	12	12	16	25	80100	100	80000	100	80019	500	1166108	1	26683	26728	26727	16625	10	16667	80120	200	80030	200	160060	26708	26708	1	1	80201	100	99	100	100	80000	80000	0	100	80000	0	0	80039	0	0	0	80039	6	1	0	43	2	2	2	5129	1	23	1	2	26759	10	0	2	80000	100	26709	26723	26728	26709	26709
80204	26727	200	0	0	0	0	1	0	26712	2	12	0	12	25	80100	100	80000	100	80021	500	1159479	1	26702	26727	26708	16640	9	16667	80119	200	80030	200	160060	26727	26728	1	1	80201	100	99	100	100	80000	80000	0	100	80000	0	39	80039	1	0	0	80035	6	1	35	39	2	2	2	5129	1	23	1	1	26804	0	10	0	80000	100	26728	26709	26709	26723	26729
80204	26728	200	0	0	0	41	0	2	26711	2	0	0	16	25	80100	100	80000	100	80021	500	1166108	1	26702	26728	26727	16640	10	16666	80120	200	80030	200	160060	26728	26722	1	1	80201	100	99	100	100	80000	80000	0	100	80000	0	39	80000	1	0	39	80000	6	1	36	39	2	2	2	5128	1	23	1	1	26837	10	0	4	80000	100	26728	26709	26728	26709	26709
80204	26708	200	0	0	0	45	1	1	26707	2	12	12	16	25	80100	100	80000	100	80022	500	1167398	1	26702	26727	26722	16645	9	16667	80121	200	80030	200	160060	26727	26722	1	1	80201	100	99	100	100	80000	80000	0	100	80000	0	39	80039	0	0	38	80039	0	1	35	0	2	2	2	5129	2	23	1	2	26819	10	6	4	80000	100	26728	26709	26728	26728	26728

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.3342

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	09	l2 tlb miss data (0b)	0e	0f	1e	22	3a	3f	43	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	67	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	branch cond mispred nonspec (c5)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
80025	26733	200	1	1	1	1	0	1	65	1	2	26768	3	18	18	16	25	80010	10	80000	10	80000	50	1165822	0	0	26708	26732	26732	16677	3	16712	80010	20	80000	20	160000	26732	26732	1	1	80021	10	9	10	10	80000	80000	1	10	80019	20	42	80057	1	1	1	59	80038	6	0	58	42	19	0	1	5020	26	16	25	25	26712	0	0	2	80000	10	26734	26734	26734	26734	26716
80024	26732	200	1	0	0	1	0	0	65	0	2	26717	0	0	0	2	25	80010	10	80000	10	80000	50	1167660	0	0	26707	26733	26732	16677	3	16712	80010	20	80000	20	160000	26715	26714	1	1	80021	10	9	10	10	80000	80000	0	10	80020	19	42	80058	0	0	0	59	80038	6	0	57	42	19	1	0	5020	26	16	25	24	26730	0	9	2	80000	10	26733	26733	26733	26733	26734
80024	26732	200	1	0	1	1	0	0	65	0	3	26723	2	18	18	15	25	80010	10	80000	10	80000	50	1167298	0	0	26707	26732	26732	16677	3	16712	80010	20	80000	20	160000	26732	26732	1	1	80021	10	9	10	10	80000	80000	0	10	80019	20	42	80019	0	0	0	59	80000	6	1	57	42	19	1	0	5020	15	16	25	20	26729	9	0	2	80000	10	26734	26734	26734	26734	26733
80024	26732	200	1	1	1	0	0	0	65	1	3	26718	3	0	18	15	25	80010	10	80000	10	80000	50	1167660	0	0	26707	26732	26732	16677	3	16712	80010	20	80000	20	160000	26732	26732	1	1	80021	10	9	10	10	80000	80000	0	10	80020	19	42	80057	1	0	0	59	80000	6	1	19	42	19	0	0	5020	26	16	17	24	26730	9	9	2	80000	10	26733	26733	26733	26734	26733
80024	26732	201	1	1	1	1	0	0	65	1	3	26718	0	18	0	16	25	80010	10	80000	10	80000	50	1167660	0	0	26707	26733	26732	16677	3	16712	80010	20	80000	20	160000	26732	26715	1	1	80021	10	9	10	10	80000	80000	0	10	80020	20	42	80057	2	0	1	59	80038	0	1	57	42	19	1	0	5020	15	16	25	15	26730	9	9	0	80000	10	26733	26733	26733	26733	26733
80024	26732	200	1	1	1	1	0	0	65	1	2	26719	2	18	0	16	25	80010	10	80000	10	80000	50	1165822	0	0	26708	26732	26732	16677	3	16712	80010	20	80000	20	160000	26732	26732	1	1	80021	10	9	10	10	80000	80000	0	10	80020	19	42	80019	1	0	1	21	80000	0	0	57	0	19	2	0	5020	26	16	19	25	26729	9	0	2	80000	10	26733	26716	26734	26733	26733
80024	26732	200	1	0	1	0	0	0	21	0	3	26717	2	18	18	16	25	80010	10	80000	10	80000	50	1167298	0	0	26707	26732	26714	16677	3	16712	80010	20	80000	20	160000	26732	26732	1	1	80021	10	9	10	10	80000	80000	1	10	80020	20	42	80057	1	0	1	21	80038	6	1	57	0	19	1	0	5020	22	16	25	25	26729	9	9	2	80000	10	26733	26715	26715	26733	26733
80024	26733	200	1	1	1	1	0	0	21	0	3	26801	2	18	18	16	25	80010	10	80000	10	80000	50	1170204	0	0	26708	26732	26733	16677	3	16712	80010	20	80000	20	160000	26732	26733	1	1	80021	10	9	10	10	80000	80000	0	10	80020	20	42	80057	1	0	1	59	80038	0	0	57	42	19	1	0	5020	25	16	25	25	26729	9	9	2	80000	10	26733	26733	26733	26715	26733
80024	26732	200	1	1	1	1	0	0	64	1	3	26717	0	18	18	16	25	80010	10	80000	10	80000	50	1170204	0	0	26707	26732	26733	16677	3	16712	80010	20	80000	20	160000	26732	26733	1	1	80021	10	9	10	10	80000	80000	0	10	80019	21	0	80057	1	1	3	59	80038	6	1	57	42	19	1	0	5020	25	16	21	24	26729	9	9	0	80000	10	26716	26733	26734	26733	26733
80024	26732	200	1	0	0	1	0	0	65	1	3	26701	2	18	18	0	25	80010	10	80000	10	80000	50	1170204	0	0	26689	26714	26715	16677	3	16695	80010	20	80000	20	160000	26715	26732	1	1	80021	10	9	10	10	80000	80000	0	10	80020	21	42	80057	0	0	0	59	80038	6	1	57	42	19	0	0	5020	22	16	25	25	26712	9	9	2	80000	10	26733	26733	26733	26733	26733

LDR (register, S)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->2 roundtrip

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: Latency 1->3 roundtrip

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 4: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations