Apple Microarchitecture Research by Dougall Johnson M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions M1/A14 E-core (Icestorm): Overview | Base Instructions | SIMD and FP Instructions
Code:
ldr d0, [x6, x7, lsl #3]
mov x7, #4 mov x8, 0
(no loop instructions)
Retires: 1.000
Issues: 1.000
Integer unit issues: 0.000
Load/store unit issues: 1.000
SIMD/FP unit issues: 0.000
| retire uop (01) | cycle (02) | 03 | l1d tlb fill (05) | mmu table walk data (08) | 09 | l2 tlb miss data (0b) | 0e | 0f | 1e | 22 | 23 | 3a | 3f | 43 | 46 | 49 | 4f | 51 | schedule uop (52) | schedule ldst uop (55) | dispatch ldst uop (58) | simd uops in schedulers (5a) | 60 | 69 | 6d | 6e | map stall dispatch (70) | map rewind (75) | map stall (76) | dispatch uop (78) | map ldst uop (7d) | map ldst uop inputs (80) | 82 | 83 | flush restart other nonspec (84) | 85 | inst all (8c) | 92 | inst simd load (98) | inst ldst (9b) | 9d | l1d tlb access (a0) | l1d cache miss ld (a3) | ld unit uop (a6) | l1d cache writeback (a8) | ac | af | b5 | b6 | bb | l1d cache miss ld nonspec (bf) | l1d tlb miss nonspec (c1) | cf | d5 | map dispatch bubble (d6) | dd | fetch restart (de) | e0 | ea | eb | ec | ? ldst retires (ed) | f5 | f6 | f7 | f8 | fd |
| 1005 | 404 | 3 | 0 | 0 | 0 | 0 | 1 | 1 | 67 | 1 | 0 | 2 | 389 | 3 | 7 | 10 | 21 | 25 | 1000 | 1000 | 1000 | 15572 | 1 | 379 | 404 | 404 | 226 | 3 | 262 | 1000 | 1000 | 2000 | 382 | 404 | 1 | 1 | 1001 | 0 | 1000 | 1000 | 0 | 1000 | 43 | 1042 | 0 | 42 | 1000 | 3 | 0 | 61 | 45 | 19 | 73 | 1 | 16 | 1 | 1 | 403 | 0 | 14 | 6 | 1000 | 404 | 382 | 382 | 405 | 382 |
| 1004 | 403 | 2 | 1 | 1 | 1 | 1 | 0 | 1 | 67 | 0 | 0 | 1 | 380 | 0 | 0 | 0 | 20 | 25 | 1000 | 1000 | 1000 | 15315 | 1 | 370 | 399 | 374 | 218 | 3 | 257 | 1000 | 1000 | 2000 | 399 | 395 | 1 | 1 | 1001 | 0 | 1000 | 1000 | 0 | 1000 | 43 | 1041 | 0 | 41 | 1000 | 3 | 1 | 42 | 44 | 0 | 73 | 1 | 16 | 1 | 1 | 403 | 14 | 0 | 6 | 1000 | 405 | 383 | 405 | 405 | 405 |
| 1004 | 404 | 3 | 1 | 0 | 1 | 0 | 0 | 0 | 67 | 0 | 0 | 1 | 359 | 0 | 1 | 1 | 0 | 25 | 1000 | 1000 | 1000 | 14060 | 1 | 349 | 399 | 399 | 218 | 3 | 257 | 1000 | 1000 | 2000 | 399 | 374 | 1 | 1 | 1001 | 0 | 1000 | 1000 | 0 | 1000 | 43 | 1041 | 0 | 0 | 1041 | 3 | 0 | 42 | 44 | 0 | 73 | 1 | 16 | 1 | 1 | 401 | 0 | 14 | 6 | 1000 | 405 | 405 | 382 | 405 | 382 |
| 1004 | 403 | 3 | 1 | 0 | 0 | 1 | 0 | 0 | 67 | 0 | 0 | 0 | 384 | 0 | 1 | 0 | 17 | 25 | 1000 | 1000 | 1000 | 15325 | 1 | 349 | 374 | 399 | 222 | 3 | 232 | 1000 | 1000 | 2000 | 399 | 374 | 1 | 1 | 1001 | 0 | 1000 | 1000 | 0 | 1000 | 44 | 1042 | 0 | 41 | 1041 | 0 | 0 | 42 | 44 | 0 | 73 | 1 | 16 | 1 | 1 | 401 | 14 | 14 | 6 | 1000 | 406 | 382 | 405 | 405 | 382 |
| 1004 | 403 | 3 | 1 | 1 | 1 | 0 | 0 | 0 | 66 | 1 | 0 | 1 | 384 | 2 | 1 | 12 | 20 | 25 | 1000 | 1000 | 1000 | 15322 | 1 | 370 | 399 | 399 | 197 | 3 | 257 | 1000 | 1000 | 2000 | 374 | 395 | 1 | 1 | 1001 | 0 | 1000 | 1000 | 0 | 1000 | 0 | 1041 | 0 | 41 | 1041 | 0 | 1 | 0 | 44 | 0 | 73 | 1 | 16 | 1 | 1 | 371 | 0 | 0 | 7 | 1000 | 375 | 400 | 400 | 400 | 400 |
| 1004 | 374 | 3 | 0 | 0 | 0 | 0 | 0 | 0 | 44 | 0 | 0 | 1 | 359 | 2 | 0 | 1 | 20 | 25 | 1000 | 1000 | 1000 | 15315 | 1 | 370 | 399 | 374 | 218 | 3 | 257 | 1000 | 1000 | 2000 | 374 | 399 | 1 | 1 | 1001 | 0 | 1000 | 1000 | 0 | 1000 | 43 | 1042 | 1 | 41 | 1041 | 3 | 1 | 0 | 44 | 0 | 73 | 1 | 16 | 1 | 1 | 401 | 0 | 0 | 6 | 1000 | 382 | 405 | 383 | 382 | 405 |
| 1004 | 404 | 2 | 1 | 0 | 1 | 1 | 0 | 0 | 21 | 0 | 0 | 1 | 384 | 2 | 0 | 0 | 17 | 25 | 1000 | 1000 | 1000 | 15037 | 1 | 374 | 399 | 402 | 222 | 3 | 257 | 1000 | 1000 | 2000 | 374 | 399 | 1 | 1 | 1001 | 0 | 1000 | 1000 | 0 | 1000 | 44 | 1041 | 0 | 44 | 1000 | 0 | 1 | 42 | 44 | 0 | 73 | 1 | 16 | 1 | 1 | 401 | 14 | 0 | 6 | 1000 | 382 | 404 | 405 | 387 | 405 |
| 1004 | 381 | 3 | 1 | 1 | 0 | 1 | 1 | 0 | 21 | 0 | 0 | 0 | 384 | 2 | 1 | 1 | 20 | 25 | 1000 | 1000 | 1000 | 15322 | 1 | 374 | 399 | 399 | 197 | 3 | 232 | 1000 | 1000 | 2000 | 399 | 374 | 1 | 1 | 1001 | 0 | 1000 | 1000 | 0 | 1000 | 43 | 1000 | 0 | 0 | 1000 | 0 | 0 | 41 | 0 | 0 | 73 | 1 | 16 | 1 | 1 | 401 | 14 | 14 | 6 | 1000 | 405 | 405 | 405 | 382 | 405 |
| 1004 | 405 | 3 | 1 | 1 | 1 | 1 | 0 | 0 | 21 | 0 | 0 | 1 | 389 | 0 | 7 | 7 | 20 | 25 | 1000 | 1000 | 1000 | 15572 | 1 | 379 | 381 | 381 | 204 | 3 | 262 | 1000 | 1000 | 2000 | 381 | 403 | 1 | 1 | 1001 | 0 | 1000 | 1000 | 0 | 1000 | 0 | 1041 | 0 | 41 | 1041 | 0 | 0 | 0 | 43 | 0 | 73 | 1 | 16 | 1 | 1 | 379 | 14 | 14 | 6 | 1000 | 383 | 405 | 405 | 405 | 405 |
| 1004 | 404 | 3 | 1 | 1 | 1 | 1 | 0 | 0 | 66 | 0 | 1 | 1 | 385 | 0 | 12 | 12 | 20 | 25 | 1000 | 1000 | 1000 | 15037 | 1 | 349 | 399 | 399 | 197 | 3 | 257 | 1000 | 1000 | 2000 | 399 | 395 | 1 | 1 | 1001 | 0 | 1000 | 1000 | 0 | 1000 | 43 | 1041 | 0 | 41 | 1041 | 3 | 1 | 42 | 0 | 0 | 73 | 1 | 16 | 1 | 1 | 401 | 14 | 14 | 6 | 1000 | 405 | 404 | 383 | 426 | 405 |
Chain cycles: 3
Code:
ldr d0, [x6, x7, lsl #3] fmov x0, d0 eor x8, x8, x0 eor x8, x8, x0 add x6, x6, x8
mov x7, #4 mov x8, 0
(fused SUBS/B.cc loop)
Result (median cycles for code, minus 3 chain cycles): 9.0055
| retire uop (01) | cycle (02) | 03 | mmu table walk data (08) | 09 | 0e | 0f | 18 | 1e | 1f | 22 | 23 | 3f | 4d | 4f | 51 | schedule uop (52) | schedule int uop (53) | schedule simd uop (54) | schedule ldst uop (55) | dispatch int uop (56) | dispatch simd uop (57) | dispatch ldst uop (58) | int uops in schedulers (59) | simd uops in schedulers (5a) | ldst uops in schedulers (5b) | 60 | 69 | 6b | 6d | 6e | map stall dispatch (70) | map rewind (75) | map stall (76) | dispatch uop (78) | map int uop (7c) | map ldst uop (7d) | map simd uop (7e) | map int uop inputs (7f) | map ldst uop inputs (80) | map simd uop inputs (81) | 82 | 83 | flush restart other nonspec (84) | 85 | inst all (8c) | inst branch (8d) | inst branch taken (90) | inst branch cond (94) | inst int alu (97) | inst simd load (98) | inst ldst (9b) | 9d | 9f | l1d tlb access (a0) | l1d cache miss ld (a3) | ld unit uop (a6) | st unit uop (a7) | l1d cache writeback (a8) | ac | af | b5 | l1d cache miss ld nonspec (bf) | c2 | branch mispred nonspec (cb) | cf | d0 | d5 | map dispatch bubble (d6) | dd | fetch restart (de) | e0 | ? int output thing (e9) | ea | eb | ec | ? ldst retires (ed) | ? int retires (ef) | f5 | f6 | f7 | f8 | fd |
| 50205 | 120052 | 899 | 0 | 1 | 1 | 0 | 0 | 6 | 0 | 1 | 0 | 120040 | 119493 | 109465 | 25 | 60103 | 40102 | 10000 | 10000 | 30100 | 10000 | 10000 | 1078862 | 5736428 | 6134461 | 1 | 120011 | 0 | 120055 | 120055 | 113150 | 3 | 113672 | 50100 | 30200 | 10000 | 10000 | 60200 | 20000 | 10000 | 120035 | 120052 | 1 | 1 | 50201 | 100 | 99 | 100 | 40100 | 10000 | 10000 | 0 | 100 | 10000 | 1 | 10000 | 0 | 0 | 0 | 10000 | 1 | 1 | 0 | 0 | 3210 | 0 | 1 | 107 | 1 | 1 | 119662 | 40002 | 14 | 11 | 13 | 10000 | 40100 | 120056 | 120056 | 120056 | 120053 | 120056 |
| 50204 | 120055 | 899 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 120020 | 119493 | 109468 | 25 | 60103 | 40100 | 10004 | 10000 | 30100 | 10000 | 10000 | 1079044 | 5735455 | 6136521 | 1 | 120031 | 0 | 120035 | 120052 | 113150 | 3 | 113658 | 50100 | 30200 | 10000 | 10000 | 60200 | 20000 | 10000 | 120055 | 120052 | 1 | 1 | 50201 | 100 | 99 | 100 | 40100 | 10000 | 10000 | 0 | 100 | 10000 | 1 | 10000 | 0 | 0 | 0 | 10000 | 1 | 1 | 0 | 0 | 3240 | 0 | 1 | 107 | 1 | 1 | 119662 | 40000 | 14 | 0 | 13 | 10000 | 40100 | 120056 | 120056 | 120053 | 120056 | 120056 |
| 50204 | 120052 | 899 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 0 | 120020 | 119514 | 109449 | 25 | 60100 | 40102 | 10000 | 10000 | 30100 | 10000 | 10000 | 1079017 | 5736428 | 6134461 | 1 | 120028 | 0 | 120035 | 120055 | 113141 | 3 | 113669 | 50100 | 30200 | 10000 | 10000 | 60200 | 20000 | 10000 | 120055 | 120052 | 1 | 1 | 50201 | 100 | 99 | 100 | 40100 | 10000 | 10000 | 0 | 100 | 10000 | 1 | 10000 | 0 | 0 | 0 | 10000 | 1 | 1 | 0 | 0 | 3210 | 0 | 1 | 101 | 1 | 1 | 119659 | 40002 | 0 | 14 | 13 | 10000 | 40100 | 120056 | 120070 | 120056 | 120056 | 120056 |
| 50204 | 120055 | 899 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 120040 | 119511 | 109465 | 25 | 60103 | 40102 | 10000 | 10001 | 30100 | 10000 | 10000 | 1079017 | 5736284 | 6136368 | 1 | 120031 | 0 | 120055 | 120035 | 113150 | 3 | 113669 | 50100 | 30200 | 10000 | 10000 | 60200 | 20000 | 10000 | 120055 | 120052 | 1 | 1 | 50201 | 100 | 99 | 100 | 40100 | 10000 | 10000 | 0 | 100 | 10000 | 1 | 10000 | 0 | 0 | 0 | 10000 | 1 | 1 | 0 | 0 | 3210 | 0 | 1 | 101 | 1 | 1 | 119651 | 40002 | 0 | 14 | 13 | 10000 | 40100 | 120056 | 120056 | 120036 | 120056 | 120056 |
| 50204 | 120035 | 899 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 0 | 120040 | 119493 | 109468 | 25 | 60103 | 40102 | 10001 | 10000 | 30100 | 10000 | 10000 | 1078862 | 5736284 | 6134461 | 1 | 120031 | 0 | 120055 | 120052 | 113150 | 3 | 113672 | 50100 | 30200 | 10000 | 10000 | 60200 | 20000 | 10000 | 120035 | 120052 | 1 | 1 | 50201 | 100 | 99 | 100 | 40100 | 10000 | 10000 | 0 | 100 | 10000 | 0 | 10000 | 0 | 0 | 7 | 10000 | 1 | 1 | 0 | 0 | 3210 | 0 | 2 | 107 | 1 | 1 | 119646 | 40002 | 14 | 11 | 10 | 10000 | 40100 | 120056 | 120056 | 120053 | 120053 | 120056 |
| 50204 | 120035 | 899 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 0 | 120020 | 119514 | 109468 | 25 | 60103 | 40102 | 10001 | 10000 | 30100 | 10000 | 10000 | 1078862 | 5735455 | 6136521 | 1 | 120011 | 0 | 120055 | 120035 | 113150 | 3 | 113672 | 50100 | 30200 | 10000 | 10000 | 60200 | 20000 | 10000 | 120055 | 120052 | 1 | 1 | 50201 | 100 | 99 | 100 | 40100 | 10000 | 10000 | 0 | 100 | 10000 | 1 | 10000 | 0 | 0 | 0 | 10000 | 0 | 1 | 0 | 0 | 3210 | 0 | 1 | 101 | 1 | 1 | 119662 | 40000 | 14 | 14 | 13 | 10000 | 40100 | 120036 | 120036 | 120056 | 120056 | 120056 |
| 50204 | 120052 | 899 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 0 | 120020 | 119514 | 109468 | 25 | 60103 | 40102 | 10001 | 10000 | 30100 | 10000 | 10000 | 1079044 | 5736284 | 6136521 | 1 | 120031 | 0 | 120055 | 120035 | 113155 | 3 | 113669 | 50100 | 30200 | 10000 | 10000 | 60200 | 20000 | 10000 | 120055 | 120035 | 1 | 1 | 50201 | 100 | 99 | 100 | 40100 | 10000 | 10000 | 0 | 100 | 10000 | 1 | 10000 | 0 | 0 | 0 | 10000 | 1 | 1 | 0 | 0 | 3327 | 0 | 1 | 107 | 1 | 1 | 119659 | 40002 | 0 | 14 | 0 | 10000 | 40100 | 120056 | 120056 | 120056 | 120056 | 120036 |
| 50204 | 120035 | 899 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 0 | 120040 | 119511 | 109473 | 25 | 60106 | 40100 | 10001 | 10000 | 30100 | 10000 | 10000 | 1078862 | 5736428 | 6136368 | 1 | 120031 | 0 | 120055 | 120035 | 113147 | 3 | 113658 | 50100 | 30200 | 10000 | 10000 | 60200 | 20000 | 10000 | 120055 | 120052 | 1 | 1 | 50201 | 100 | 99 | 100 | 40100 | 10000 | 10000 | 0 | 100 | 10000 | 1 | 10000 | 0 | 0 | 0 | 10000 | 1 | 1 | 0 | 0 | 3210 | 0 | 1 | 107 | 1 | 1 | 119649 | 40000 | 14 | 11 | 10 | 10000 | 40100 | 120056 | 120056 | 120039 | 120036 | 120086 |
| 50204 | 120035 | 899 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 120020 | 119493 | 109449 | 25 | 60103 | 40102 | 10001 | 10000 | 30100 | 10000 | 10000 | 1079044 | 5736428 | 6136521 | 1 | 120031 | 0 | 120055 | 120055 | 113150 | 3 | 113675 | 50100 | 30200 | 10000 | 10000 | 60200 | 20000 | 10000 | 120052 | 120035 | 1 | 1 | 50201 | 100 | 99 | 100 | 40100 | 10000 | 10000 | 0 | 100 | 10000 | 1 | 10000 | 0 | 0 | 0 | 10000 | 1 | 0 | 0 | 0 | 3210 | 0 | 1 | 107 | 1 | 1 | 119662 | 40002 | 0 | 11 | 13 | 10000 | 40100 | 120036 | 120056 | 120053 | 120036 | 120056 |
| 50204 | 120035 | 899 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 120020 | 119514 | 109468 | 25 | 60100 | 40102 | 10001 | 10000 | 30100 | 10000 | 10000 | 1079044 | 5736428 | 6136368 | 1 | 120028 | 0 | 120055 | 120055 | 113150 | 3 | 113669 | 50100 | 30200 | 10000 | 10000 | 60200 | 20000 | 10000 | 120035 | 120100 | 1 | 1 | 50201 | 100 | 99 | 100 | 40100 | 10000 | 10000 | 1 | 100 | 10000 | 1 | 10000 | 0 | 0 | 0 | 10000 | 1 | 1 | 0 | 0 | 3210 | 0 | 1 | 107 | 1 | 1 | 119646 | 40000 | 14 | 11 | 13 | 10000 | 40100 | 120056 | 120036 | 120053 | 120056 | 120056 |
Result (median cycles for code, minus 3 chain cycles): 9.0055
| retire uop (01) | cycle (02) | 03 | l1d tlb fill (05) | mmu table walk data (08) | l2 tlb miss data (0b) | 0e | 0f | 1e | 22 | 23 | 3f | 4d | 4f | 51 | schedule uop (52) | schedule int uop (53) | schedule simd uop (54) | schedule ldst uop (55) | dispatch int uop (56) | dispatch simd uop (57) | dispatch ldst uop (58) | int uops in schedulers (59) | simd uops in schedulers (5a) | ldst uops in schedulers (5b) | 60 | 69 | 6d | 6e | map stall dispatch (70) | int prf full (71) | map rewind (75) | map stall (76) | dispatch uop (78) | map int uop (7c) | map ldst uop (7d) | map simd uop (7e) | map int uop inputs (7f) | map ldst uop inputs (80) | map simd uop inputs (81) | 82 | 83 | flush restart other nonspec (84) | 85 | inst all (8c) | inst branch (8d) | inst branch taken (90) | inst branch cond (94) | inst int alu (97) | inst simd load (98) | inst ldst (9b) | 9d | 9f | l1d tlb access (a0) | l1d tlb miss (a1) | l1d cache miss ld (a3) | ld unit uop (a6) | l1d cache writeback (a8) | ac | af | b5 | bb | l1d cache miss ld nonspec (bf) | l1d tlb miss nonspec (c1) | c2 | branch mispred nonspec (cb) | cf | d5 | map dispatch bubble (d6) | dd | fetch restart (de) | e0 | ? int output thing (e9) | ea | eb | ec | ? ldst retires (ed) | ? int retires (ef) | f5 | f6 | f7 | f8 | fd |
| 50025 | 120058 | 900 | 0 | 0 | 0 | 1 | 1 | 1 | 1 | 0 | 120020 | 119513 | 109465 | 25 | 60013 | 40012 | 10001 | 10000 | 30010 | 10000 | 10000 | 1079566 | 5736428 | 6132757 | 0 | 120028 | 120035 | 120052 | 113170 | 0 | 3 | 113674 | 50010 | 30020 | 10000 | 10000 | 60020 | 20000 | 10000 | 120035 | 120093 | 1 | 1 | 50021 | 10 | 9 | 10 | 40010 | 10000 | 10000 | 0 | 10 | 10000 | 0 | 1 | 10000 | 0 | 0 | 10000 | 1 | 0 | 1 | 0 | 0 | 0 | 3140 | 2 | 107 | 3 | 3 | 119670 | 40002 | 14 | 11 | 13 | 10000 | 40010 | 120036 | 120036 | 120056 | 120056 | 120056 |
| 50025 | 120035 | 899 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 120040 | 119492 | 109468 | 25 | 60013 | 40012 | 10001 | 10000 | 30010 | 10000 | 10000 | 1079566 | 5736428 | 6133866 | 0 | 120028 | 120052 | 120055 | 113173 | 0 | 3 | 113694 | 50010 | 30020 | 10000 | 10000 | 60020 | 20000 | 10000 | 120121 | 120055 | 1 | 1 | 50021 | 10 | 9 | 10 | 40010 | 10000 | 10000 | 1 | 10 | 10000 | 0 | 1 | 10000 | 2 | 0 | 10000 | 1 | 0 | 1 | 0 | 0 | 0 | 3140 | 2 | 107 | 3 | 4 | 119670 | 40000 | 11 | 11 | 13 | 10000 | 40010 | 120056 | 120036 | 120053 | 120056 | 120056 |
| 50024 | 120035 | 899 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 120040 | 119513 | 109449 | 25 | 60013 | 40012 | 10000 | 10000 | 30010 | 10000 | 10000 | 1079566 | 5736284 | 6132757 | 0 | 120031 | 120055 | 120035 | 113173 | 0 | 3 | 113691 | 50010 | 30020 | 10000 | 10000 | 60020 | 20000 | 10000 | 120055 | 120052 | 1 | 1 | 50022 | 10 | 9 | 10 | 40010 | 10000 | 10000 | 0 | 10 | 10000 | 0 | 0 | 10000 | 0 | 0 | 10000 | 1 | 0 | 1 | 0 | 0 | 0 | 3140 | 3 | 107 | 3 | 3 | 119670 | 40000 | 14 | 0 | 13 | 10000 | 40010 | 120089 | 120041 | 120036 | 120036 | 120036 |
| 50024 | 120064 | 899 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 120040 | 119510 | 109468 | 25 | 60013 | 40012 | 10000 | 10000 | 30010 | 10000 | 10000 | 1079517 | 5735455 | 6133713 | 0 | 120028 | 120055 | 120035 | 113173 | 0 | 3 | 113691 | 50010 | 30020 | 10000 | 10000 | 60020 | 20000 | 10000 | 120055 | 120052 | 1 | 1 | 50021 | 10 | 9 | 10 | 40010 | 10000 | 10000 | 0 | 10 | 10000 | 0 | 1 | 10000 | 0 | 0 | 10000 | 1 | 0 | 1 | 0 | 0 | 0 | 3140 | 3 | 107 | 3 | 2 | 119650 | 40002 | 0 | 0 | 13 | 10000 | 40010 | 120056 | 120036 | 120056 | 120069 | 120102 |
| 50024 | 120035 | 899 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 120040 | 119513 | 109468 | 25 | 60013 | 40010 | 10000 | 10000 | 30010 | 10000 | 10000 | 1079517 | 5735455 | 6133713 | 0 | 120028 | 120035 | 120052 | 113170 | 0 | 3 | 113691 | 50010 | 30020 | 10000 | 10000 | 60020 | 20000 | 10000 | 120035 | 120052 | 1 | 1 | 50021 | 10 | 9 | 10 | 40010 | 10000 | 10000 | 0 | 10 | 10000 | 0 | 1 | 10000 | 0 | 0 | 10000 | 0 | 0 | 1 | 0 | 0 | 0 | 3140 | 2 | 107 | 2 | 3 | 119667 | 40002 | 14 | 14 | 10 | 10000 | 40010 | 120056 | 120036 | 120056 | 120036 | 120036 |
| 50024 | 120055 | 899 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 120040 | 119513 | 109468 | 25 | 60013 | 40012 | 10001 | 10000 | 30010 | 10000 | 10000 | 1079593 | 5736428 | 6132757 | 0 | 120011 | 120052 | 120055 | 113173 | 0 | 3 | 113694 | 50010 | 30020 | 10000 | 10000 | 60020 | 20000 | 10000 | 120052 | 120052 | 1 | 1 | 50021 | 10 | 9 | 10 | 40010 | 10000 | 10000 | 0 | 10 | 10000 | 0 | 1 | 10000 | 0 | 0 | 10000 | 1 | 0 | 1 | 0 | 0 | 0 | 3140 | 4 | 107 | 3 | 3 | 119650 | 40002 | 14 | 14 | 13 | 10000 | 40010 | 120056 | 120056 | 120036 | 120053 | 120056 |
| 50024 | 120055 | 899 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 120025 | 119513 | 109468 | 25 | 60013 | 40010 | 10001 | 10000 | 30162 | 10000 | 10000 | 1079566 | 5736284 | 6132757 | 0 | 120011 | 120035 | 120052 | 113173 | 0 | 3 | 113674 | 50010 | 30020 | 10000 | 10000 | 60020 | 20000 | 10000 | 120055 | 120052 | 1 | 1 | 50021 | 10 | 9 | 10 | 40010 | 10000 | 10000 | 0 | 10 | 10000 | 0 | 0 | 10000 | 0 | 0 | 10000 | 0 | 0 | 0 | 0 | 0 | 0 | 3140 | 3 | 107 | 2 | 3 | 119670 | 40002 | 14 | 11 | 13 | 10000 | 40010 | 120056 | 120036 | 120056 | 120036 | 120036 |
| 50024 | 120055 | 899 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 120040 | 119510 | 109449 | 25 | 60010 | 40010 | 10001 | 10000 | 30010 | 10000 | 10000 | 1079593 | 5735455 | 6133713 | 0 | 120031 | 120055 | 120035 | 113153 | 0 | 3 | 113674 | 50010 | 30020 | 10000 | 10000 | 60020 | 20000 | 10000 | 120035 | 120052 | 1 | 1 | 50021 | 10 | 9 | 10 | 40010 | 10000 | 10000 | 0 | 10 | 10000 | 0 | 1 | 10000 | 1 | 0 | 10000 | 1 | 0 | 1 | 0 | 0 | 0 | 3197 | 3 | 107 | 1 | 4 | 119749 | 40000 | 14 | 0 | 10 | 10000 | 40010 | 120037 | 120054 | 120036 | 120144 | 120136 |
| 50024 | 120255 | 900 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 120041 | 119513 | 109468 | 25 | 60013 | 40010 | 10001 | 10000 | 30010 | 10000 | 10000 | 1079593 | 5735455 | 6133713 | 0 | 120031 | 120058 | 120055 | 113173 | 0 | 3 | 113694 | 50010 | 30020 | 10000 | 10000 | 60020 | 20000 | 10000 | 120058 | 120052 | 1 | 1 | 50021 | 10 | 9 | 10 | 40010 | 10000 | 10000 | 0 | 10 | 10000 | 0 | 1 | 10000 | 1 | 7253 | 10003 | 1 | 0 | 1 | 0 | 0 | 0 | 3140 | 3 | 107 | 4 | 3 | 119670 | 40002 | 14 | 14 | 10 | 10000 | 40010 | 120053 | 120054 | 120053 | 120053 | 120056 |
| 50024 | 120057 | 899 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 0 | 120040 | 119492 | 109469 | 25 | 60010 | 40012 | 10000 | 10000 | 30010 | 10000 | 10000 | 1079517 | 5735455 | 6133866 | 0 | 120092 | 120035 | 120055 | 113153 | 0 | 3 | 113679 | 50254 | 30020 | 10000 | 10000 | 60020 | 20000 | 10000 | 120055 | 120052 | 1 | 1 | 50021 | 10 | 9 | 10 | 40010 | 10000 | 10000 | 1 | 10 | 10000 | 0 | 1 | 10000 | 1 | 3 | 10000 | 1 | 0 | 1 | 0 | 0 | 0 | 3140 | 3 | 107 | 4 | 2 | 119670 | 40002 | 14 | 11 | 10 | 10000 | 40010 | 120056 | 120056 | 120053 | 120053 | 120041 |
Chain cycles: 3
Code:
ldr d0, [x6, x7, lsl #3] fmov x0, d0 eor x8, x8, x0 eor x8, x8, x0 add x7, x7, x8
mov x7, #4 mov x8, 0
(fused SUBS/B.cc loop)
Result (median cycles for code, minus 3 chain cycles): 9.0052
| retire uop (01) | cycle (02) | 03 | l1d tlb fill (05) | mmu table walk data (08) | 09 | l2 tlb miss data (0b) | 0e | 0f | 18 | 19 | 1e | 1f | 22 | 23 | 3f | 4d | 4f | 51 | schedule uop (52) | schedule int uop (53) | schedule simd uop (54) | schedule ldst uop (55) | dispatch int uop (56) | dispatch simd uop (57) | dispatch ldst uop (58) | int uops in schedulers (59) | simd uops in schedulers (5a) | ldst uops in schedulers (5b) | 60 | 69 | 6b | 6d | 6e | map stall dispatch (70) | map rewind (75) | map stall (76) | dispatch uop (78) | map int uop (7c) | map ldst uop (7d) | map simd uop (7e) | map int uop inputs (7f) | map ldst uop inputs (80) | map simd uop inputs (81) | 82 | 83 | flush restart other nonspec (84) | 85 | inst all (8c) | inst branch (8d) | inst branch taken (90) | inst branch cond (94) | inst int alu (97) | inst simd load (98) | inst ldst (9b) | 9d | 9f | l1d tlb access (a0) | l1d tlb miss (a1) | l1d cache miss ld (a3) | ld unit uop (a6) | l1d cache writeback (a8) | a9 | ac | af | b5 | l1d cache miss ld nonspec (bf) | c2 | branch cond mispred nonspec (c5) | cf | d5 | map dispatch bubble (d6) | dd | fetch restart (de) | e0 | ? int output thing (e9) | ea | eb | ec | ? ldst retires (ed) | ? int retires (ef) | f5 | f6 | f7 | f8 | fd |
| 50205 | 120058 | 899 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 0 | 1 | 0 | 1 | 0 | 120037 | 119511 | 109465 | 25 | 60103 | 40102 | 10000 | 10000 | 30100 | 10000 | 10000 | 1079017 | 5736284 | 6138743 | 1 | 120011 | 0 | 120052 | 120052 | 113147 | 3 | 113669 | 50100 | 30200 | 10000 | 10000 | 60200 | 20000 | 10000 | 120052 | 120052 | 1 | 1 | 50201 | 100 | 99 | 100 | 40100 | 10000 | 10000 | 0 | 100 | 10000 | 0 | 1 | 10000 | 0 | 0 | 0 | 10000 | 1 | 1 | 0 | 0 | 3210 | 1 | 107 | 1 | 1 | 119659 | 40002 | 11 | 11 | 10 | 10000 | 40100 | 120053 | 120053 | 120053 | 120053 | 120053 |
| 50204 | 120052 | 899 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 1 | 0 | 1 | 0 | 120020 | 119493 | 109449 | 25 | 60103 | 40102 | 10001 | 10000 | 30100 | 10000 | 10000 | 1078889 | 5736428 | 6148780 | 1 | 120028 | 0 | 120052 | 120052 | 113141 | 3 | 113669 | 50100 | 30200 | 10000 | 10000 | 60200 | 20000 | 10000 | 120052 | 120052 | 1 | 1 | 50201 | 100 | 99 | 100 | 40100 | 10000 | 10000 | 0 | 100 | 10000 | 0 | 1 | 10000 | 0 | 0 | 0 | 10000 | 0 | 0 | 0 | 0 | 3210 | 1 | 107 | 1 | 1 | 119659 | 40002 | 0 | 11 | 10 | 10000 | 40100 | 120053 | 120053 | 120053 | 120053 | 120053 |
| 50204 | 120052 | 899 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 6 | 0 | 1 | 0 | 120138 | 119493 | 109465 | 25 | 60103 | 40100 | 10001 | 10000 | 30100 | 10000 | 10000 | 1079017 | 5736284 | 6139374 | 0 | 120011 | 0 | 120035 | 120035 | 113147 | 3 | 113658 | 50100 | 30848 | 10000 | 10000 | 60200 | 20000 | 10000 | 120035 | 120052 | 1 | 1 | 50201 | 100 | 99 | 100 | 40100 | 10000 | 10000 | 0 | 100 | 10000 | 0 | 1 | 10000 | 0 | 0 | 3 | 10000 | 0 | 0 | 0 | 0 | 3210 | 1 | 107 | 1 | 1 | 119659 | 40002 | 11 | 11 | 0 | 10000 | 40100 | 120053 | 120056 | 120054 | 120056 | 120053 |
| 50204 | 120052 | 899 | 0 | 0 | 0 | 0 | 1 | 1 | 4 | 0 | 1 | 0 | 1 | 0 | 120037 | 119493 | 109465 | 25 | 60103 | 40102 | 10001 | 10000 | 30100 | 10000 | 10000 | 1079017 | 5736284 | 6137653 | 0 | 120028 | 0 | 120052 | 120052 | 113147 | 3 | 113669 | 50100 | 30200 | 10000 | 10000 | 60200 | 20000 | 10000 | 120052 | 120096 | 1 | 1 | 50201 | 100 | 99 | 100 | 40100 | 10000 | 10000 | 0 | 100 | 10000 | 0 | 1 | 10000 | 0 | 0 | 0 | 10000 | 1 | 0 | 0 | 0 | 3269 | 1 | 107 | 1 | 1 | 119646 | 40002 | 11 | 11 | 10 | 10000 | 40100 | 120053 | 120053 | 120036 | 120053 | 120054 |
| 50204 | 120052 | 899 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 1 | 0 | 1 | 0 | 120037 | 119511 | 109465 | 25 | 60103 | 40102 | 10000 | 10000 | 30100 | 10000 | 10000 | 1079017 | 5739740 | 6136337 | 0 | 120028 | 0 | 120052 | 120052 | 113141 | 3 | 113669 | 50100 | 30200 | 10000 | 10000 | 60580 | 20000 | 10000 | 120052 | 120052 | 1 | 1 | 50201 | 100 | 99 | 100 | 40100 | 10000 | 10000 | 0 | 100 | 10000 | 0 | 1 | 10000 | 0 | 0 | 0 | 10000 | 1 | 1 | 2 | 0 | 3210 | 1 | 101 | 1 | 1 | 119646 | 40002 | 11 | 11 | 10 | 10000 | 40100 | 120053 | 120053 | 120036 | 120053 | 120053 |
| 50204 | 120035 | 900 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 13 | 0 | 0 | 1 | 120037 | 119511 | 109465 | 25 | 60103 | 40102 | 10001 | 10000 | 30676 | 10000 | 10000 | 1079017 | 5736284 | 6137348 | 0 | 120028 | 0 | 120052 | 120052 | 113147 | 3 | 113670 | 50100 | 30200 | 10000 | 10000 | 60200 | 20000 | 10000 | 120035 | 120052 | 1 | 1 | 50201 | 100 | 99 | 100 | 40100 | 10000 | 10000 | 0 | 100 | 10000 | 2 | 1 | 10000 | 0 | 0 | 0 | 10000 | 1 | 1 | 0 | 0 | 3210 | 1 | 101 | 1 | 1 | 119659 | 40002 | 11 | 11 | 10 | 10000 | 40100 | 120053 | 120053 | 120053 | 120053 | 120053 |
| 50204 | 120052 | 899 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 120037 | 119511 | 109449 | 25 | 60103 | 40102 | 10001 | 10000 | 30100 | 10000 | 10000 | 1079017 | 5736284 | 6139113 | 0 | 120011 | 0 | 120052 | 120052 | 113147 | 3 | 113669 | 50100 | 30200 | 10000 | 10000 | 60200 | 20000 | 10000 | 120052 | 120052 | 1 | 1 | 50201 | 100 | 99 | 100 | 40100 | 10000 | 10000 | 0 | 100 | 10000 | 0 | 1 | 10000 | 1 | 0 | 0 | 10000 | 0 | 0 | 0 | 0 | 3210 | 1 | 101 | 1 | 1 | 119659 | 40000 | 11 | 11 | 10 | 10000 | 40100 | 120053 | 120053 | 120053 | 120053 | 120036 |
| 50204 | 120052 | 899 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 120037 | 119511 | 109465 | 25 | 60103 | 40102 | 10000 | 10000 | 30100 | 10000 | 10000 | 1078862 | 5736284 | 6138990 | 0 | 120028 | 0 | 120052 | 120052 | 113147 | 3 | 113669 | 50100 | 30200 | 10000 | 10000 | 60200 | 20000 | 10000 | 120035 | 120052 | 1 | 1 | 50201 | 100 | 99 | 100 | 40100 | 10000 | 10000 | 0 | 100 | 10000 | 0 | 1 | 10000 | 0 | 0 | 0 | 10000 | 1 | 0 | 0 | 0 | 3210 | 1 | 101 | 1 | 1 | 119659 | 40000 | 11 | 0 | 10 | 10000 | 40100 | 120036 | 120053 | 120053 | 120053 | 120053 |
| 50204 | 120052 | 899 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 1 | 292 | 0 | 0 | 1 | 120037 | 119494 | 109467 | 25 | 60142 | 40102 | 10000 | 10004 | 30100 | 10207 | 10000 | 1079017 | 5742385 | 6139964 | 0 | 120028 | 0 | 120035 | 120052 | 113147 | 3 | 113669 | 50100 | 30200 | 10000 | 10000 | 60200 | 20000 | 10000 | 120035 | 120055 | 1 | 1 | 50201 | 100 | 99 | 100 | 40100 | 10000 | 10000 | 0 | 100 | 10000 | 0 | 1 | 10000 | 0 | 0 | 0 | 10000 | 1 | 0 | 0 | 0 | 3210 | 1 | 101 | 1 | 1 | 119659 | 40002 | 11 | 11 | 10 | 10000 | 40100 | 120053 | 120053 | 120053 | 120038 | 120059 |
| 50204 | 120052 | 901 | 0 | 0 | 1 | 1 | 0 | 0 | 0 | 5 | 316 | 280 | 0 | 1 | 120037 | 119511 | 109467 | 25 | 60103 | 40102 | 10001 | 10000 | 30100 | 10000 | 10000 | 1079017 | 5736332 | 6137197 | 0 | 120028 | 0 | 120054 | 120052 | 113154 | 3 | 113669 | 50100 | 30200 | 10055 | 10000 | 60200 | 20000 | 10053 | 120036 | 120152 | 1 | 1 | 50201 | 100 | 99 | 100 | 40100 | 10000 | 10000 | 0 | 100 | 10042 | 0 | 1 | 10044 | 0 | 2 | 125678 | 10047 | 1 | 1 | 0 | 0 | 4185 | 1 | 107 | 1 | 1 | 120635 | 40239 | 11 | 11 | 0 | 10000 | 40100 | 123251 | 122560 | 123897 | 123681 | 123345 |
Result (median cycles for code, minus 3 chain cycles): 9.0055
| retire uop (01) | cycle (02) | 03 | mmu table walk data (08) | 09 | l2 tlb miss data (0b) | 0e | 0f | 18 | 19 | 1e | 1f | 22 | 23 | 3f | 4d | 4f | 51 | schedule uop (52) | schedule int uop (53) | schedule simd uop (54) | schedule ldst uop (55) | dispatch int uop (56) | dispatch simd uop (57) | dispatch ldst uop (58) | int uops in schedulers (59) | simd uops in schedulers (5a) | ldst uops in schedulers (5b) | 60 | 69 | 6d | 6e | map stall dispatch (70) | map rewind (75) | map stall (76) | dispatch uop (78) | map int uop (7c) | map ldst uop (7d) | map simd uop (7e) | map int uop inputs (7f) | map ldst uop inputs (80) | map simd uop inputs (81) | 82 | 83 | flush restart other nonspec (84) | 85 | inst all (8c) | inst branch (8d) | inst branch taken (90) | inst branch cond (94) | inst int alu (97) | inst simd load (98) | inst ldst (9b) | 9d | 9f | l1d tlb access (a0) | l1d cache miss ld (a3) | ld unit uop (a6) | l1d cache writeback (a8) | a9 | ac | af | b5 | l1d cache miss ld nonspec (bf) | branch cond mispred nonspec (c5) | cd | cf | d5 | map dispatch bubble (d6) | dd | fetch restart (de) | e0 | ? int output thing (e9) | ea | eb | ec | ? ldst retires (ed) | ? int retires (ef) | f5 | f6 | f7 | f8 | fd |
| 50025 | 120052 | 899 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 120037 | 119492 | 109468 | 25 | 60010 | 40010 | 10001 | 10000 | 30010 | 10000 | 10000 | 1079566 | 5736428 | 6132757 | 0 | 120034 | 120035 | 120055 | 113170 | 3 | 113691 | 50010 | 30020 | 10000 | 10000 | 60020 | 20000 | 10063 | 120052 | 120035 | 1 | 1 | 50021 | 10 | 9 | 10 | 40010 | 10000 | 10000 | 0 | 10 | 10000 | 0 | 10000 | 0 | 0 | 0 | 10000 | 1 | 0 | 0 | 0 | 3140 | 6 | 107 | 1 | 1 | 119650 | 40002 | 11 | 11 | 10 | 10000 | 40010 | 120083 | 120056 | 120056 | 120056 | 120053 |
| 50024 | 120055 | 899 | 0 | 1 | 0 | 1 | 1 | 0 | 0 | 37 | 0 | 0 | 0 | 120020 | 119513 | 109465 | 25 | 60013 | 40012 | 10001 | 10000 | 30010 | 10000 | 10000 | 1079517 | 5736428 | 6132757 | 0 | 120011 | 120055 | 120052 | 113173 | 3 | 113694 | 50010 | 30209 | 10000 | 10000 | 60020 | 20000 | 10000 | 120055 | 120052 | 1 | 1 | 50021 | 10 | 9 | 10 | 40010 | 10000 | 10000 | 0 | 10 | 10000 | 1 | 10000 | 0 | 0 | 0 | 10000 | 1 | 1 | 0 | 0 | 3140 | 1 | 107 | 1 | 1 | 119650 | 40002 | 0 | 0 | 0 | 10000 | 40010 | 120056 | 120056 | 120056 | 120036 | 120036 |
| 50024 | 120035 | 899 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 120037 | 119510 | 109465 | 25 | 60013 | 40010 | 10001 | 10000 | 30010 | 10000 | 10000 | 1079566 | 5736428 | 6133713 | 1 | 120011 | 120055 | 120035 | 113153 | 3 | 113694 | 50010 | 30020 | 10000 | 10000 | 60020 | 20000 | 10000 | 120052 | 120052 | 1 | 1 | 50021 | 10 | 9 | 10 | 40010 | 10000 | 10000 | 0 | 10 | 10000 | 1 | 10000 | 0 | 0 | 0 | 10000 | 1 | 0 | 0 | 0 | 3283 | 1 | 107 | 1 | 1 | 119667 | 40000 | 0 | 0 | 13 | 10000 | 40010 | 120056 | 120056 | 120056 | 120056 | 120056 |
| 50024 | 120035 | 899 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 120037 | 119492 | 109468 | 25 | 60013 | 40010 | 10000 | 10000 | 30010 | 10000 | 10000 | 1079517 | 5735455 | 6133713 | 0 | 120031 | 120055 | 120055 | 113153 | 3 | 113694 | 50010 | 30020 | 10000 | 10000 | 60020 | 20000 | 10000 | 120035 | 120052 | 1 | 1 | 50021 | 10 | 9 | 10 | 40010 | 10000 | 10000 | 0 | 10 | 10000 | 1 | 10000 | 0 | 0 | 3 | 10000 | 0 | 0 | 0 | 0 | 3140 | 1 | 107 | 1 | 1 | 119667 | 40002 | 14 | 14 | 0 | 10000 | 40010 | 120056 | 120056 | 120053 | 120036 | 120056 |
| 50024 | 120035 | 899 | 0 | 0 | 0 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 120020 | 119513 | 109468 | 25 | 60010 | 40012 | 10001 | 10000 | 30010 | 10062 | 10000 | 1079611 | 5736284 | 6132757 | 0 | 120031 | 120055 | 120055 | 113153 | 3 | 113674 | 50010 | 30020 | 10000 | 10000 | 60020 | 20000 | 10000 | 120055 | 120035 | 3 | 1 | 50021 | 10 | 9 | 10 | 40010 | 10000 | 10000 | 0 | 10 | 10000 | 0 | 10000 | 0 | 0 | 3 | 10000 | 1 | 0 | 0 | 0 | 3140 | 1 | 107 | 1 | 1 | 119670 | 40000 | 14 | 0 | 0 | 10000 | 40010 | 120036 | 120053 | 120053 | 120053 | 120056 |
| 50024 | 120052 | 899 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 120020 | 119492 | 109468 | 25 | 60013 | 40012 | 10000 | 10000 | 30010 | 10000 | 10000 | 1079566 | 5735455 | 6132757 | 1 | 120031 | 120052 | 120035 | 113173 | 3 | 113694 | 50010 | 30020 | 10000 | 10000 | 60020 | 20000 | 10000 | 120055 | 120052 | 1 | 1 | 50021 | 10 | 9 | 10 | 40010 | 10000 | 10000 | 0 | 10 | 10000 | 1 | 10000 | 0 | 0 | 0 | 10000 | 1 | 1 | 0 | 0 | 3140 | 1 | 107 | 1 | 1 | 119670 | 40002 | 14 | 11 | 13 | 10000 | 40010 | 120056 | 120056 | 120053 | 120036 | 120056 |
| 50024 | 120035 | 899 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 120020 | 119594 | 109468 | 25 | 60013 | 40010 | 10001 | 10000 | 30152 | 10000 | 10000 | 1081571 | 5737948 | 6136155 | 1 | 120031 | 122514 | 122719 | 113932 | 3 | 114719 | 56321 | 31960 | 10000 | 10000 | 60020 | 20000 | 10000 | 120052 | 120052 | 1 | 1 | 50021 | 10 | 9 | 10 | 40010 | 10000 | 10000 | 0 | 10 | 10000 | 1 | 10000 | 0 | 0 | 12 | 10000 | 1 | 0 | 0 | 0 | 3140 | 1 | 107 | 1 | 1 | 119667 | 40000 | 14 | 14 | 13 | 10000 | 40010 | 120053 | 120036 | 120056 | 120056 | 120036 |
| 50024 | 120055 | 899 | 0 | 0 | 0 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 120040 | 119510 | 109468 | 25 | 60010 | 40012 | 10000 | 10000 | 30010 | 10000 | 10000 | 1079593 | 5735455 | 6133866 | 0 | 120028 | 120052 | 120055 | 113153 | 3 | 113691 | 50284 | 30020 | 10000 | 10000 | 60020 | 20000 | 10000 | 120052 | 120052 | 1 | 1 | 50021 | 10 | 9 | 10 | 40010 | 10000 | 10000 | 0 | 10 | 10000 | 0 | 10000 | 0 | 0 | 3 | 10000 | 1 | 1 | 0 | 0 | 3140 | 1 | 107 | 1 | 1 | 119670 | 40002 | 0 | 0 | 0 | 10000 | 40010 | 120036 | 120036 | 120053 | 120056 | 120056 |
| 50024 | 120055 | 899 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 120040 | 119513 | 109449 | 25 | 60010 | 40012 | 10000 | 10000 | 30010 | 10000 | 10000 | 1079566 | 5736284 | 6132757 | 0 | 120032 | 120055 | 120052 | 113173 | 3 | 113691 | 50010 | 30020 | 10000 | 10000 | 60020 | 20000 | 10000 | 120055 | 120052 | 1 | 1 | 50021 | 10 | 9 | 10 | 40010 | 10000 | 10000 | 0 | 10 | 10000 | 0 | 10000 | 0 | 0 | 0 | 10000 | 1 | 1 | 0 | 0 | 3140 | 1 | 107 | 1 | 1 | 119670 | 40002 | 11 | 0 | 13 | 10000 | 40010 | 120053 | 120036 | 120053 | 120056 | 120056 |
| 50024 | 120052 | 899 | 0 | 0 | 0 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 120040 | 119513 | 109465 | 25 | 60013 | 40012 | 10001 | 10000 | 30010 | 10000 | 10056 | 1079593 | 5735455 | 6132757 | 0 | 120011 | 120035 | 120052 | 113153 | 3 | 113694 | 50010 | 30020 | 10000 | 10000 | 60020 | 20000 | 10000 | 120035 | 120035 | 1 | 1 | 50021 | 10 | 9 | 10 | 40010 | 10000 | 10000 | 0 | 10 | 10000 | 1 | 10000 | 1 | 0 | 0 | 10002 | 1 | 1 | 0 | 0 | 3140 | 1 | 107 | 1 | 1 | 119667 | 40000 | 14 | 14 | 13 | 10000 | 40010 | 120056 | 120056 | 120036 | 120056 | 120053 |
Count: 8
Code:
ldr d0, [x6, x7, lsl #3] ldr d0, [x6, x7, lsl #3] ldr d0, [x6, x7, lsl #3] ldr d0, [x6, x7, lsl #3] ldr d0, [x6, x7, lsl #3] ldr d0, [x6, x7, lsl #3] ldr d0, [x6, x7, lsl #3] ldr d0, [x6, x7, lsl #3]
mov x7, 8
(fused SUBS/B.cc loop)
Result (median cycles for code divided by count): 0.3338
| retire uop (01) | cycle (02) | 03 | mmu table walk instruction (07) | l2 tlb miss instruction (0a) | l2 tlb miss data (0b) | 18 | 19 | 1e | 3f | 4f | 50 | 51 | schedule uop (52) | schedule int uop (53) | schedule ldst uop (55) | dispatch int uop (56) | dispatch ldst uop (58) | int uops in schedulers (59) | simd uops in schedulers (5a) | 60 | 69 | 6d | 6e | map stall dispatch (70) | map rewind (75) | map stall (76) | dispatch uop (78) | map int uop (7c) | map ldst uop (7d) | map int uop inputs (7f) | map ldst uop inputs (80) | 82 | 83 | flush restart other nonspec (84) | 85 | inst all (8c) | inst branch (8d) | inst branch taken (90) | inst branch cond (94) | inst int alu (97) | inst simd load (98) | inst ldst (9b) | 9f | l1d tlb access (a0) | a5 | ld unit uop (a6) | st unit uop (a7) | l1d cache writeback (a8) | ac | af | c2 | branch cond mispred nonspec (c5) | branch mispred nonspec (cb) | cd | cf | d5 | map dispatch bubble (d6) | dd | fetch restart (de) | e0 | ? ldst retires (ed) | ? int retires (ef) | f5 | f6 | f7 | f8 | fd |
| 80205 | 26874 | 200 | 1 | 1 | 0 | 0 | 0 | 0 | 26692 | 0 | 0 | 25 | 80100 | 100 | 80000 | 100 | 80015 | 500 | 1172348 | 0 | 26682 | 26707 | 26707 | 16635 | 6 | 16659 | 80115 | 200 | 80024 | 200 | 160048 | 26707 | 26707 | 1 | 1 | 80201 | 100 | 99 | 100 | 100 | 80000 | 80000 | 100 | 80000 | 0 | 80000 | 0 | 0 | 81 | 80000 | 0 | 1 | 1 | 1 | 5118 | 2 | 16 | 1 | 1 | 26704 | 80000 | 100 | 26708 | 26708 | 26708 | 26708 | 26708 |
| 80204 | 26782 | 200 | 1 | 1 | 0 | 0 | 0 | 0 | 26692 | 0 | 0 | 25 | 80100 | 100 | 80000 | 100 | 80015 | 500 | 1182368 | 0 | 26682 | 26707 | 26707 | 16635 | 6 | 16659 | 80115 | 200 | 80024 | 200 | 160048 | 26707 | 26707 | 1 | 1 | 80201 | 100 | 99 | 100 | 100 | 80000 | 80000 | 100 | 80000 | 0 | 80000 | 0 | 0 | 60 | 80000 | 0 | 1 | 1 | 1 | 5118 | 1 | 16 | 1 | 1 | 26704 | 80000 | 100 | 26708 | 26708 | 26708 | 26708 | 26708 |
| 80204 | 26765 | 201 | 1 | 1 | 0 | 0 | 0 | 0 | 26692 | 0 | 0 | 25 | 80100 | 100 | 80000 | 100 | 80014 | 500 | 1167055 | 0 | 26682 | 26707 | 26707 | 16635 | 6 | 16659 | 80115 | 200 | 80024 | 200 | 160048 | 26707 | 26707 | 1 | 1 | 80201 | 100 | 99 | 100 | 100 | 80000 | 80000 | 100 | 80000 | 0 | 80000 | 0 | 1 | 6 | 80000 | 0 | 1 | 1 | 1 | 5118 | 1 | 16 | 1 | 1 | 26704 | 80000 | 100 | 26708 | 26708 | 26708 | 26708 | 26708 |
| 80204 | 26880 | 200 | 1 | 1 | 0 | 0 | 0 | 0 | 26692 | 0 | 0 | 25 | 80100 | 100 | 80000 | 100 | 80015 | 500 | 1167864 | 0 | 26682 | 26707 | 26707 | 16635 | 6 | 16659 | 80115 | 200 | 80024 | 200 | 160048 | 26707 | 26707 | 1 | 1 | 80201 | 100 | 99 | 100 | 100 | 80000 | 80000 | 100 | 80000 | 0 | 80000 | 0 | 0 | 156 | 80000 | 0 | 1 | 1 | 1 | 5118 | 1 | 16 | 1 | 1 | 26704 | 80000 | 100 | 26708 | 26708 | 26708 | 26708 | 26708 |
| 80204 | 26853 | 201 | 1 | 1 | 0 | 0 | 0 | 0 | 26699 | 0 | 0 | 25 | 80100 | 100 | 80000 | 100 | 80015 | 500 | 1167492 | 0 | 26956 | 26711 | 26719 | 16635 | 6 | 16659 | 80115 | 200 | 80024 | 200 | 160048 | 26711 | 27304 | 1 | 1 | 80201 | 100 | 99 | 100 | 100 | 80000 | 80000 | 100 | 80522 | 0 | 80522 | 0 | 1 | 3159 | 80000 | 0 | 1 | 1 | 1 | 5142 | 1 | 50 | 1 | 1 | 26712 | 80000 | 100 | 26723 | 26723 | 26719 | 26723 | 26713 |
| 80204 | 26707 | 200 | 1 | 1 | 0 | 0 | 0 | 0 | 26692 | 2 | 0 | 25 | 80100 | 100 | 80000 | 100 | 80015 | 500 | 1167540 | 0 | 26682 | 26707 | 26707 | 16635 | 6 | 16659 | 80115 | 200 | 80024 | 200 | 160048 | 26707 | 26711 | 1 | 1 | 80201 | 100 | 99 | 100 | 100 | 80000 | 80000 | 100 | 80000 | 0 | 80000 | 0 | 0 | 0 | 80000 | 0 | 1 | 1 | 1 | 5118 | 1 | 16 | 1 | 1 | 26708 | 80000 | 100 | 26708 | 26708 | 26708 | 26708 | 26708 |
| 80204 | 26707 | 200 | 1 | 1 | 0 | 0 | 0 | 0 | 26692 | 0 | 0 | 25 | 80100 | 100 | 80000 | 100 | 80015 | 500 | 1174434 | 0 | 26687 | 26711 | 26707 | 16635 | 6 | 16659 | 80115 | 200 | 80024 | 200 | 160048 | 26710 | 26707 | 1 | 1 | 80201 | 100 | 99 | 100 | 100 | 80000 | 80000 | 100 | 80000 | 0 | 80000 | 0 | 0 | 15 | 80000 | 0 | 1 | 1 | 1 | 5118 | 1 | 16 | 1 | 1 | 26704 | 80000 | 100 | 26708 | 26710 | 26708 | 26708 | 26708 |
| 80204 | 26721 | 200 | 1 | 1 | 0 | 0 | 0 | 12 | 26692 | 0 | 0 | 25 | 80100 | 100 | 80000 | 100 | 80015 | 500 | 1166596 | 1 | 26686 | 26707 | 26707 | 16635 | 6 | 16659 | 80115 | 200 | 80024 | 200 | 160048 | 26707 | 26707 | 1 | 1 | 80201 | 100 | 99 | 100 | 100 | 80000 | 80000 | 100 | 80000 | 0 | 80000 | 0 | 0 | 24 | 80000 | 0 | 1 | 1 | 1 | 5118 | 1 | 16 | 1 | 1 | 26704 | 80000 | 100 | 26708 | 26708 | 26708 | 26708 | 26708 |
| 80204 | 26758 | 201 | 1 | 1 | 0 | 0 | 0 | 0 | 26692 | 0 | 0 | 25 | 80100 | 100 | 80000 | 100 | 80016 | 500 | 1166432 | 0 | 26682 | 26707 | 26707 | 16635 | 6 | 16659 | 80115 | 200 | 80024 | 200 | 160048 | 26707 | 26707 | 1 | 1 | 80201 | 100 | 99 | 100 | 100 | 80000 | 80000 | 100 | 80000 | 0 | 80000 | 0 | 0 | 105 | 80000 | 0 | 1 | 1 | 1 | 5118 | 1 | 16 | 1 | 1 | 26704 | 80000 | 100 | 26708 | 26708 | 26708 | 26708 | 26708 |
| 80204 | 26707 | 200 | 1 | 1 | 0 | 0 | 0 | 0 | 26692 | 0 | 0 | 25 | 80100 | 100 | 80000 | 100 | 80016 | 500 | 1167316 | 0 | 26682 | 26707 | 26707 | 16635 | 6 | 16659 | 80115 | 200 | 80024 | 200 | 160048 | 26707 | 26707 | 1 | 1 | 80201 | 100 | 99 | 100 | 100 | 80000 | 80000 | 100 | 80000 | 0 | 80000 | 0 | 0 | 57 | 80000 | 0 | 1 | 1 | 1 | 5118 | 1 | 16 | 1 | 1 | 26704 | 80000 | 100 | 26708 | 26708 | 26708 | 26708 | 26708 |
Result (median cycles for code divided by count): 0.3351
| retire uop (01) | cycle (02) | 03 | mmu table walk instruction (07) | 09 | 18 | 19 | 1e | 3f | 4f | 51 | schedule uop (52) | schedule int uop (53) | schedule ldst uop (55) | dispatch int uop (56) | dispatch ldst uop (58) | int uops in schedulers (59) | simd uops in schedulers (5a) | 69 | 6d | 6e | map stall dispatch (70) | map rewind (75) | map stall (76) | dispatch uop (78) | map int uop (7c) | map ldst uop (7d) | map int uop inputs (7f) | map ldst uop inputs (80) | 82 | 83 | flush restart other nonspec (84) | 85 | inst all (8c) | inst branch (8d) | inst branch taken (90) | inst branch cond (94) | inst int alu (97) | inst simd load (98) | inst ldst (9b) | 9f | l1d tlb access (a0) | ld unit uop (a6) | l1d cache writeback (a8) | ac | af | cf | d5 | map dispatch bubble (d6) | dd | fetch restart (de) | e0 | ? ldst retires (ed) | ? int retires (ef) | f5 | f6 | f7 | f8 | fd |
| 80025 | 26877 | 200 | 0 | 0 | 0 | 0 | 0 | 26693 | 0 | 25 | 80010 | 10 | 80000 | 10 | 80000 | 50 | 1166688 | 26683 | 26708 | 26708 | 16652 | 3 | 16688 | 80010 | 20 | 80000 | 20 | 160000 | 26708 | 26708 | 1 | 1 | 80021 | 10 | 9 | 10 | 10 | 80000 | 80000 | 10 | 80000 | 80000 | 0 | 66 | 80000 | 5020 | 6 | 16 | 7 | 6 | 26705 | 80000 | 10 | 26709 | 26709 | 26709 | 26709 | 26709 |
| 80024 | 26745 | 201 | 0 | 0 | 0 | 0 | 0 | 26693 | 0 | 25 | 80010 | 10 | 80000 | 10 | 80000 | 50 | 1166647 | 26683 | 26708 | 26708 | 16652 | 3 | 16688 | 80010 | 20 | 80000 | 20 | 160000 | 26708 | 26708 | 1 | 1 | 80021 | 10 | 9 | 10 | 10 | 80000 | 80000 | 10 | 80000 | 80000 | 0 | 108 | 80000 | 5020 | 6 | 16 | 6 | 5 | 26705 | 80000 | 10 | 26709 | 26709 | 26709 | 26709 | 26709 |
| 80024 | 26816 | 200 | 0 | 0 | 0 | 0 | 0 | 26693 | 0 | 25 | 80010 | 10 | 80000 | 10 | 80000 | 50 | 1166266 | 26683 | 26708 | 26708 | 16652 | 3 | 16688 | 80010 | 20 | 80000 | 20 | 160000 | 26708 | 26708 | 1 | 1 | 80021 | 10 | 9 | 10 | 10 | 80000 | 80000 | 10 | 80000 | 80000 | 0 | 111 | 80000 | 5020 | 5 | 16 | 5 | 6 | 26705 | 80000 | 10 | 26709 | 26709 | 26709 | 26709 | 26709 |
| 80024 | 26817 | 201 | 0 | 0 | 0 | 0 | 0 | 26693 | 0 | 25 | 80010 | 10 | 80000 | 10 | 80000 | 50 | 1174993 | 26683 | 26708 | 26708 | 16652 | 3 | 16688 | 80010 | 20 | 80000 | 20 | 160000 | 26708 | 26708 | 1 | 1 | 80021 | 10 | 9 | 10 | 10 | 80000 | 80000 | 10 | 80000 | 80000 | 0 | 102 | 80000 | 5020 | 5 | 16 | 7 | 7 | 26705 | 80000 | 10 | 26709 | 26709 | 26709 | 26709 | 26709 |
| 80024 | 26819 | 200 | 0 | 0 | 0 | 0 | 0 | 26693 | 0 | 25 | 80010 | 10 | 80000 | 10 | 80000 | 50 | 1157452 | 26683 | 26708 | 26708 | 16652 | 3 | 16688 | 80010 | 20 | 80000 | 20 | 160000 | 26710 | 26708 | 1 | 1 | 80021 | 10 | 9 | 10 | 10 | 80000 | 80000 | 10 | 80000 | 80000 | 0 | 60 | 80000 | 5020 | 5 | 16 | 5 | 5 | 26705 | 80000 | 10 | 26728 | 26709 | 26709 | 26709 | 26709 |
| 80024 | 26708 | 200 | 0 | 1 | 0 | 0 | 0 | 26693 | 0 | 25 | 80010 | 10 | 80000 | 10 | 80000 | 50 | 1173217 | 26683 | 26708 | 26708 | 16652 | 3 | 16688 | 80010 | 20 | 80000 | 20 | 160000 | 26708 | 26708 | 1 | 1 | 80021 | 10 | 9 | 10 | 10 | 80000 | 80000 | 10 | 80000 | 80000 | 0 | 126 | 80000 | 5020 | 8 | 16 | 8 | 8 | 26705 | 80000 | 10 | 26709 | 26711 | 26709 | 26709 | 26709 |
| 80024 | 26840 | 201 | 0 | 0 | 0 | 0 | 0 | 26693 | 0 | 25 | 80010 | 10 | 80000 | 10 | 80000 | 50 | 1172834 | 26683 | 26708 | 26708 | 16652 | 3 | 16688 | 80010 | 20 | 80000 | 20 | 160000 | 26708 | 26708 | 1 | 1 | 80021 | 10 | 9 | 10 | 10 | 80000 | 80000 | 10 | 80000 | 80000 | 0 | 9 | 80000 | 5020 | 7 | 16 | 7 | 8 | 26705 | 80000 | 10 | 26709 | 26709 | 26709 | 26709 | 26709 |
| 80024 | 26771 | 200 | 0 | 0 | 0 | 0 | 0 | 26693 | 0 | 25 | 80010 | 10 | 80000 | 10 | 80000 | 50 | 1166032 | 26685 | 26708 | 26708 | 16652 | 3 | 16688 | 80010 | 20 | 80000 | 20 | 160000 | 26708 | 26708 | 1 | 1 | 80021 | 10 | 9 | 10 | 10 | 80000 | 80000 | 10 | 80000 | 80000 | 0 | 54 | 80000 | 5020 | 5 | 16 | 6 | 6 | 26705 | 80000 | 10 | 26709 | 26709 | 26709 | 26709 | 26709 |
| 80024 | 26708 | 200 | 0 | 0 | 0 | 0 | 0 | 26693 | 0 | 25 | 80010 | 10 | 80000 | 10 | 80000 | 50 | 1166750 | 26683 | 26708 | 26708 | 16652 | 3 | 16688 | 80010 | 20 | 80000 | 20 | 160000 | 26708 | 26708 | 1 | 1 | 80021 | 10 | 9 | 10 | 10 | 80000 | 80000 | 10 | 80000 | 80000 | 0 | 3 | 80130 | 5020 | 8 | 16 | 6 | 5 | 26705 | 80000 | 10 | 26709 | 26709 | 26709 | 26709 | 26709 |
| 80024 | 26844 | 200 | 0 | 0 | 0 | 0 | 0 | 26693 | 0 | 25 | 80010 | 10 | 80000 | 10 | 80000 | 50 | 1173570 | 26683 | 26708 | 26708 | 16652 | 3 | 16688 | 80010 | 20 | 80000 | 20 | 160000 | 26708 | 26708 | 1 | 1 | 80021 | 10 | 9 | 10 | 10 | 80000 | 80000 | 10 | 80000 | 80000 | 0 | 111 | 80000 | 5020 | 8 | 16 | 8 | 6 | 26705 | 80000 | 10 | 26709 | 26709 | 26709 | 26709 | 26709 |