Firestorm: LDR (register, lsl, Q) measurements

Code:

  ldr q0, [x6, x7, lsl #4]

Initialization

  mov x7, #4
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 2.000

Issues: 2.000

Integer unit issues: 1.000

Load/store unit issues: 1.000

SIMD/FP unit issues: 0.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	09	l2 tlb miss data (0b)	0f	1e	3a	3f	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst simd load (98)	inst ldst (9b)	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	st unit uop (a7)	a9	ac	af	b5	bb	l1d tlb miss nonspec (c1)	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
2006	383	3	1	0	0	0	0	0	0	361	0	25	2000	1000	1000	1000	1000	5000	14298	0	351	376	376	74	3	113	2000	1000	1000	1000	2000	376	376	1	1	1001	1000	1000	1000	0	1000	0	0	0	1000	0	0	0	0	73	1	16	1	1	381	1000	1000	1000	385	384	384	384	384
2004	383	3	1	0	0	0	0	0	0	362	0	25	2000	1000	1000	1000	1000	5000	14298	0	357	384	383	80	3	116	2000	1000	1000	1000	2000	383	384	1	1	1001	1000	1000	1020	20	1019	2	2	20	1000	0	19	19	0	73	1	16	1	1	380	1000	1000	1000	385	384	384	385	384
2004	384	3	1	0	0	0	0	0	1	361	0	25	2000	1000	1000	1000	1000	5000	14298	1	351	376	376	74	3	109	2000	1000	1000	1000	2000	376	376	1	1	1001	1000	1000	1000	0	1000	0	0	0	1000	0	0	0	0	73	1	16	1	1	373	1000	1000	1000	377	377	377	377	377
2004	376	3	0	0	0	0	0	47	0	368	0	25	2000	1000	1000	1000	1000	5000	14640	0	351	376	376	74	3	109	2000	1000	1000	1000	2000	376	376	1	1	1001	1000	1000	1000	0	1000	0	0	6	1000	0	0	0	0	73	1	16	1	1	373	1000	1000	1000	377	377	377	377	377
2004	376	3	0	0	0	0	0	0	0	361	0	25	2000	1000	1000	1000	1000	5000	14298	0	468	383	383	81	3	116	2000	1000	1000	1000	2000	383	383	1	1	1001	1000	1000	1020	19	1019	2	1	20	1000	0	0	0	0	73	1	16	1	1	373	1000	1000	1000	377	377	377	377	377
2004	391	2	0	0	0	0	0	0	0	361	2	25	2000	1000	1000	1000	1000	5000	14598	1	357	384	383	80	3	116	2000	1000	1000	1000	2000	383	383	1	1	1001	1000	1000	1019	19	1019	0	1	20	1000	0	19	19	1	73	1	16	1	1	380	1000	1000	1000	384	385	384	384	385
2004	384	3	1	0	1	1	0	20	1	368	0	25	2000	1000	1000	1000	1000	5000	14605	0	358	383	383	80	3	116	2000	1000	1000	1000	2000	383	384	1	1	1001	1000	1000	1019	20	1019	0	1	20	1000	0	19	19	2	73	1	16	1	1	380	1000	1000	1000	384	384	384	385	384
2004	383	2	1	0	0	0	0	20	1	368	1	25	2000	1000	1000	1000	1000	5000	14640	0	351	376	376	74	3	109	2000	1000	1000	1000	2000	376	376	1	1	1001	1000	1000	1000	0	1000	0	0	0	1000	0	0	0	0	73	1	16	1	1	373	1000	1000	1000	377	377	377	377	377
2004	376	3	0	0	1	0	0	20	0	368	0	25	2000	1000	1000	1000	1000	5000	14548	0	358	383	382	80	3	117	2000	1000	1000	1000	2000	383	383	1	1	1001	1000	1000	1021	19	1019	1	1	20	1000	0	19	19	0	73	1	16	1	1	381	1000	1000	1000	384	385	384	384	384
2004	384	3	1	0	0	0	0	24	0	361	0	25	2000	1000	1000	1000	1000	5000	14298	0	351	376	376	74	3	109	2000	1000	1000	1000	2000	376	376	1	1	1001	1000	1000	1000	2	1000	0	0	0	1000	0	19	19	2	73	1	16	1	1	380	1000	1000	1000	385	384	384	385	385

Test 2: Latency 1->2 roundtrip

Chain cycles: 3

Code:

  ldr q0, [x6, x7, lsl #4]
  fmov x0, d0
  eor x8, x8, x0
  eor x8, x8, x0
  add x6, x6, x8

Initialization

  mov x7, #4
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 9.0051

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1i tlb fill (04)	l1d tlb fill (05)	mmu table walk data (08)	09	l2 tlb miss data (0b)	1e	3a	3f	43	4d	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	69	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst ldst (9b)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	af	b5	bb	l1d tlb miss nonspec (c1)	c2	branch mispred nonspec (cb)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
60206	120067	899	0	1	1	2	1	2	3	120036	1	119507	98283	25	70106	50104	10002	10000	40100	10000	10000	1174851	5715676	5898174	1	120027	0	120051	120051	111892	3	112458	60100	40200	10065	10000	70200	20000	10000	120051	120051	1	1	50201	100	99	100	40100	10000	10000	100	10002	2	10002	0	2	2	10001	0	2	1	1	0	3215	9	67	9	9	119663	50004	10000	50100	120052	120098	120113	120055	120052
60204	120051	900	0	1	0	0	1	2	3	120036	1	119508	98283	25	70106	50104	10002	10000	40100	10000	10000	1174833	5715676	5898124	1	120027	0	120051	120051	111892	3	112458	60400	40200	10000	10000	70200	20000	10000	120051	120051	1	1	50201	100	99	100	40100	10000	10000	100	10001	2	10003	0	1	2	10001	0	2	1	1	0	3215	9	67	9	9	119663	50004	10000	50100	120052	120052	120052	120052	120052
60204	120051	899	0	1	1	0	0	2	3	120036	1	119507	98283	25	70109	50167	10002	10000	40100	10000	10000	1174842	5715820	5898124	1	120027	0	120051	120051	111892	3	112458	60100	40200	10000	10060	70200	20000	10000	120051	120082	1	1	50201	100	99	100	40100	10000	10000	100	10002	2	10004	4	1	2	10001	0	2	1	0	0	3215	4	67	10	11	119663	50004	10000	50100	120052	120052	120053	120052	120052
60204	120051	899	0	1	1	0	1	2	3	120036	1	119509	98284	25	70106	50104	10002	10000	40100	10000	10000	1174833	5715676	5898124	1	120027	0	120051	120051	111892	3	112458	60100	40200	10000	10000	70200	20000	10000	120051	120058	1	1	50201	100	99	100	40100	10000	10000	100	10003	2	10004	0	1	2	10001	0	2	1	1	0	3215	10	67	9	10	119663	50004	10000	50100	120052	120052	120052	120052	120052
60204	120051	900	0	1	0	0	0	2	3	120036	1	119507	98283	25	70106	50104	10002	10000	40100	10000	10000	1174833	5715676	5898124	1	120027	0	120051	120052	111895	3	112458	60100	40200	10000	10000	70200	20000	10000	120051	120051	1	1	50201	100	99	100	40100	10000	10000	100	10002	1	10003	0	1	2	10001	1	2	1	1	0	3215	9	67	4	10	119663	50004	10000	50100	120052	120052	120052	120052	120052
60204	120099	899	0	1	0	0	1	2	3	120036	1	119527	98284	25	70106	50104	10002	10000	40100	10000	10000	1174833	5715676	5898124	0	120027	0	120051	120052	111892	3	112458	60100	40200	10000	10000	70200	20000	10000	120051	120051	1	1	50201	100	99	100	40100	10000	10000	100	10001	2	10002	0	0	218	10001	1	2	1	0	0	3215	9	67	10	9	119663	50004	10000	50100	120052	120052	120052	120052	120052
60204	120051	899	0	1	0	0	1	2	3	120036	1	119507	99316	25	70106	50104	10002	10000	40100	10000	10000	1174833	5715676	5898124	1	120027	0	120051	120051	111892	3	112458	60100	40200	10000	10000	70200	20000	10000	120051	120051	1	1	50201	100	99	100	40100	10000	10000	100	10003	2	10002	0	1	2	10001	0	2	1	1	0	3215	9	67	9	9	119663	50004	10000	50100	120052	120052	120052	120052	120052
60204	120051	899	0	1	0	0	1	2	3	120036	1	119507	98283	25	70106	50104	10002	10000	40100	10000	10058	1174860	5720099	5898124	1	120027	0	120051	120051	111892	3	112458	60405	40200	10000	10000	70200	20000	10000	120051	120051	1	1	50201	100	99	100	40100	10000	10000	100	10001	2	10003	0	1	2	10001	0	2	1	1	0	3215	9	67	4	9	119663	50004	10000	50100	120052	120052	120052	120052	120052
60204	120051	899	0	1	0	1	1	2	3	120036	1	119507	98283	25	70106	50104	10002	10002	40100	10000	10000	1174833	5715676	5898124	1	120027	0	120052	120051	111892	3	112458	60100	40200	10000	10000	70200	20000	10000	120051	120051	1	1	50201	100	99	100	40100	10000	10000	100	10002	1	10002	0	0	2	10001	0	2	1	2	0	3215	4	67	10	9	119663	50004	10000	50100	120052	120052	120052	120052	120052
60204	120051	900	0	1	0	1	0	2	3	120036	1	119507	98283	25	70106	50104	10002	10000	40100	10000	10000	1174833	5715676	5898124	1	120027	0	120051	120051	111892	3	112458	60100	40200	10000	10000	70200	20000	10000	120051	120051	1	1	50201	100	99	100	40100	10000	10000	100	10001	2	10004	0	1	2	10001	0	2	1	2	0	3215	5	67	8	4	119663	50004	10000	50100	120052	120052	120052	120052	120052

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 9.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	l2 tlb miss data (0b)	0f	18	19	1e	1f	3f	4d	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	69	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst ldst (9b)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	af	bb	l1d tlb miss nonspec (c1)	c2	branch cond mispred nonspec (c5)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
60026	120043	899	0	0	1	0	0	0	1	0	120028	119498	99966	25	70013	50012	10001	10000	40010	10000	10000	1119820	5719125	5902882	0	120019	3	120043	120043	111941	3	112442	60010	40020	10000	10000	70440	20000	10000	120043	120043	1	1	50021	10	9	10	40010	10000	10000	10	10003	2	10002	0	1	1	10000	1	1	1	0	3140	4	97	3	3	119676	50002	10000	50010	120044	120044	120044	120044	120044
60024	120043	899	1	0	1	0	0	0	1	0	120028	119564	99966	25	70013	50012	10001	10000	40010	10000	10000	1119820	5719125	5902882	0	120019	0	120043	120043	111935	3	112442	60010	40020	10000	10000	70020	20000	10000	120046	120046	1	1	50021	10	9	10	40010	10000	10000	10	10001	1	10002	0	2	1	10000	1	1	1	0	3140	3	97	2	4	119676	50002	10000	50010	120044	120044	120044	120044	120044
60024	120043	899	1	0	0	0	0	0	0	0	120022	119491	98327	25	70010	50010	10000	10000	40010	10000	10000	1203587	5713980	5897195	0	120013	0	120037	120037	111927	3	112480	60010	40020	10000	10000	70020	20000	10000	120037	120037	1	1	50021	10	9	10	40010	10000	10000	10	10000	0	10000	0	0	0	10000	0	0	0	0	3140	3	65	2	3	119696	50000	10000	50010	120038	120038	120038	120038	120038
60024	120037	899	0	0	0	0	0	0	0	0	120022	119627	98327	25	70010	50010	10000	10000	40010	10000	10000	1203587	5713980	5897195	0	120013	0	120037	120037	111927	3	112475	60010	40020	10000	10000	70020	20000	10000	120037	120037	1	1	50021	10	9	10	40010	10000	10000	10	10000	0	10000	0	0	0	10000	0	0	0	0	3140	3	65	3	3	119659	50000	10000	50010	120038	120038	120038	120038	120038
60024	120037	899	0	0	0	0	0	0	0	0	120022	119491	98327	25	70010	50010	10000	10000	40010	10000	10000	1203587	5713980	5897195	1	120013	3	120086	120042	111927	3	112468	60010	40020	10000	10000	70020	20000	10000	120073	120100	1	1	50021	10	9	10	40010	10000	10000	10	10000	0	10000	0	0	0	10000	0	0	0	0	3140	2	65	3	2	119659	50000	10000	50010	120038	120038	120038	120038	120038
60024	120037	899	0	0	0	0	0	0	0	0	120022	119491	98327	25	70010	50010	10002	10000	40010	10000	10000	1182360	5713980	5897195	0	120057	0	120037	120037	111927	3	112468	60010	40020	10000	10000	70020	20000	10000	120037	120037	1	1	50021	10	9	10	40010	10000	10000	10	10000	0	10000	0	0	0	10000	0	0	0	1	3140	2	65	3	4	119659	50000	10000	50010	120038	120041	120038	120038	120038
60024	120038	899	0	0	0	0	0	0	0	0	120022	119491	98327	25	70010	50010	10000	10000	40010	10000	10000	1228817	5713980	5897195	1	120013	0	120037	120037	111927	3	112468	60010	40020	10000	10000	70020	20000	10000	120037	120037	1	1	50021	10	9	10	40010	10000	10000	10	10000	0	10000	0	0	0	10000	0	0	0	0	3140	3	65	3	3	119659	50000	10000	50010	120038	120072	120049	120058	120038
60024	120037	899	0	0	0	0	0	0	0	0	120022	119491	98327	25	70010	50010	10000	10000	40010	10000	10000	1203587	5713980	5897195	2	120013	0	120037	120037	111927	3	112468	60010	40020	10000	10000	70020	20000	10000	120037	120037	1	1	50021	10	9	10	40010	10000	10000	10	10000	0	10000	0	2	3	10000	0	0	0	0	3140	3	65	4	3	119659	50000	10000	50010	120038	120038	120038	120038	120038
60024	120037	899	0	0	0	0	0	0	12	0	120023	119491	98328	25	70010	50010	10000	10000	40010	10000	10000	1203767	5713980	5900485	0	120203	0	120252	120037	111927	3	112468	60010	40229	10000	10053	70020	20208	10000	120351	120037	2	1	50021	10	9	10	40010	10000	10000	10	10000	0	10000	0	0	3	10000	0	0	0	0	3140	2	65	2	4	119661	50000	10000	50010	120038	120038	120038	120038	120038
60024	120037	899	0	0	0	0	0	0	12	0	120022	119493	97844	25	70010	50010	10000	10000	40010	10055	10000	1203587	5713296	5897397	1	120016	0	120037	120056	111929	3	112471	60010	40433	10102	10000	71468	20000	10000	120141	120143	4	1	50021	10	9	10	40010	10000	10000	10	10000	0	10000	0	0	24	10000	0	0	0	0	3140	2	65	3	4	119659	50000	10000	50010	120038	120038	120038	120038	120038

Test 3: Latency 1->3 roundtrip

Chain cycles: 3

Code:

  ldr q0, [x6, x7, lsl #4]
  fmov x0, d0
  eor x8, x8, x0
  eor x8, x8, x0
  add x7, x7, x8

Initialization

  mov x7, #4
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 11.0035

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l2 tlb miss data (0b)	0e	19	1e	22	23	3f	4d	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst ldst (9b)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	ac	af	b5	l1d cache miss ld nonspec (bf)	cf	d0	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
60206	140047	1049	0	0	0	0	0	0	140020	139556	25	70103	50100	10000	10000	40100	10000	10000	1245607	5323927	5345349	140011	140035	140083	131949	3	132416	60100	40200	10000	10000	70200	20000	10000	140035	140035	1	1	50201	100	99	100	40100	10000	10000	100	10000	0	0	10000	0	0	10000	0	0	3210	0	1	93	1	1	139699	50000	0	0	0	10000	50100	140036	140036	140036	140036	140036
60204	140035	1085	0	0	0	0	0	0	140020	139556	25	70100	50100	10000	10000	40100	10000	10000	1245607	5323927	5345349	140011	140085	140035	131949	3	132416	60100	40200	10000	10000	70200	20000	10000	140035	140035	1	1	50201	100	99	100	40100	10000	10000	100	10000	0	0	10000	0	0	10000	0	0	3210	0	1	93	1	1	139699	50000	0	0	0	10000	50100	140036	140036	140036	140036	140036
60204	140035	1049	0	0	0	0	0	0	140020	139556	77	70100	50100	10000	10000	40100	10000	10000	1245661	5323927	5345387	140011	140035	140035	131949	3	132416	60100	40200	10000	10000	70200	20000	10000	140047	140035	1	1	50201	100	99	100	40100	10000	10000	100	10000	4	0	10000	0	0	10000	0	0	3210	0	1	93	1	1	139703	50000	0	0	0	10000	50100	140036	140036	140036	140036	140036
60204	140035	1048	0	0	0	0	0	0	140020	139556	25	70100	50100	10000	10000	40100	10000	10000	1245607	5323927	5345349	140011	140035	140035	131950	3	132416	60100	40200	10000	10000	70200	20000	10000	140035	140035	1	1	50201	100	99	100	40100	10000	10000	100	10000	0	0	10000	0	0	10000	1	0	3210	0	1	93	1	1	139702	50000	0	0	0	10000	50100	140036	140036	140036	140036	140036
60204	140035	1049	0	0	0	0	0	0	140020	139556	25	70100	50100	10000	10000	40100	10000	10000	1245607	5323927	5345349	140023	140035	140035	131949	3	132416	60100	40200	10000	10000	70200	20000	10000	140035	140035	1	1	50201	100	99	100	40100	10000	10000	100	10000	0	0	10000	0	0	10000	0	0	3210	0	1	93	1	1	139702	50000	0	0	0	10000	50100	140036	140036	140036	140036	140036
60204	140035	1049	0	0	0	93	0	0	140020	139556	25	70100	50100	10000	10000	40100	10000	10000	1245607	5323927	5345349	140011	140035	140047	131961	3	132416	60100	40200	10000	10000	70200	20000	10000	140081	140043	1	1	50201	100	99	100	40100	10000	10000	100	10000	0	0	10000	0	0	10000	0	0	3210	0	1	93	1	1	139702	50000	0	0	0	10000	50100	140036	140036	140041	140036	140036
60204	140035	1049	0	0	0	0	0	0	140020	139556	25	70100	50100	10000	10000	40100	10000	10000	1245607	5323927	5345349	140011	140035	140035	131949	3	132416	60100	40200	10000	10000	70200	20000	10000	140035	140035	1	1	50201	100	99	100	40100	10000	10000	100	10000	0	0	10000	0	9	10000	0	0	3210	0	1	93	1	1	139700	50000	0	0	0	10000	50100	140036	140037	140036	140036	140036
60204	140035	1049	0	0	0	0	1	0	140020	139556	25	70100	50100	10000	10000	40100	10045	10000	1245611	5323927	5346970	140056	140035	140035	131949	3	132416	60100	40200	10000	10000	70200	20000	10000	140035	140035	1	1	50201	100	99	100	40100	10000	10000	100	10000	0	0	10000	0	0	10000	0	0	3210	0	1	93	1	1	139699	50000	0	0	0	10000	50100	140036	140036	140036	140036	140036
60204	140035	1049	0	1	0	15	0	0	140020	139556	25	70100	50100	10000	10000	40100	10000	10000	1245607	5323927	5345349	140011	140035	140035	131949	3	132416	60100	40200	10000	10000	70200	20000	10000	140035	140035	1	1	50201	100	99	100	40100	10000	10000	100	10000	0	0	10000	0	0	10000	0	0	3210	0	1	93	1	1	139699	50000	0	0	0	10000	50100	140036	140036	140036	140036	140036
60204	140035	1049	0	0	0	0	0	0	140020	139556	25	70100	50100	10000	10000	40100	10000	10000	1245607	5323927	5345349	140011	140035	140035	131949	3	132416	60100	40200	10000	10000	70200	20000	10000	140035	140035	1	1	50201	100	99	100	40100	10000	10000	100	10000	0	0	10000	0	3	10001	0	0	3210	0	1	93	1	1	139699	50011	0	0	0	10000	50100	140384	140036	140036	140036	140402

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 11.0035

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	l2 tlb miss data (0b)	18	19	1e	1f	3a	3f	4d	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst ldst (9b)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	af	c2	branch mispred nonspec (cb)	cd	cf	d0	d2	l1i cache miss demand (d3)	d5	map dispatch bubble (d6)	da	db	dd	fetch restart (de)	e0	? int output thing (e9)	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
60026	140035	1049	0	0	0	0	0	0	0	140020	139649	25	70010	50010	10000	10000	40010	10000	10000	1245753	5326922	5349557	0	140011	140035	140035	132004	3	132443	60010	40020	10000	10000	70020	20000	10000	140035	140035	1	1	50021	10	9	10	40010	10000	10000	10	10000	0	10000	0	0	0	10000	0	0	0	3140	0	0	0	9	88	1	0	2	2	139705	50000	0	0	10000	50010	140072	140039	140036	140036	140037
60024	140035	1049	0	0	0	0	0	0	0	140020	139639	25	70010	50010	10000	10000	40433	10000	10000	1245753	5326922	5349557	1	140011	140035	140146	131983	3	132443	60010	40020	10000	10000	70020	20000	10049	140035	140035	1	1	50021	10	9	10	40010	10000	10000	10	10000	0	10000	0	0	0	10002	0	0	0	3140	0	0	0	2	88	0	0	2	2	139705	50000	0	0	10000	50010	140113	140062	140037	140086	140036
60024	140035	1049	0	0	0	0	0	0	0	140020	139711	25	70010	50010	10000	10000	40010	10000	10000	1245753	5326922	5349557	1	140015	140035	140035	131983	3	132443	60010	40020	10000	10000	70020	20000	10000	140035	140035	1	1	50021	10	9	10	40010	10000	10000	10	10000	0	10000	1	0	0	10000	2	0	0	3869	0	0	0	4	363	0	0	4	12	141992	50296	0	0	10000	50010	143024	142867	142864	143098	142993
60024	142955	1071	1	0	32	32	4299	2904	5	143146	141144	915	70495	50379	10074	10050	45648	11310	11014	1331895	5398227	5426545	1	143000	143473	143515	133168	434	134567	68507	47797	11090	11964	83436	23854	11912	144545	144339	49	1	50021	10	9	10	40010	10000	10000	10	10049	2	10003	1	0	12691	10000	4	0	0	4037	0	0	0	2	88	0	0	6	1	141731	50006	0	0	10000	50010	140038	140036	140036	140036	140036
60024	140116	1114	0	1	0	0	0	0	2	140111	139639	25	70010	50010	10000	10000	42282	10040	10000	1245753	5326922	5349557	1	143127	140035	140131	131983	28	132443	60010	40020	10000	10040	70020	20000	10000	140077	140035	3	1	50021	10	9	10	40010	10000	10000	10	10000	0	10000	89	0	0	10000	0	0	0	3263	1	0	0	2	148	0	0	2	2	139705	50000	0	0	10000	50010	140036	140036	140383	140036	140036
60024	140035	1049	0	0	0	0	0	598	0	140020	139639	25	70010	50010	10000	10000	40010	10000	10000	1245753	5327040	5349872	0	140011	140035	140035	131983	3	132443	60010	40020	10000	10000	70020	20000	10000	140035	140035	1	1	50021	10	9	10	40010	10000	10000	10	10000	0	10000	0	0	0	10000	0	0	0	3140	0	0	0	2	88	0	0	2	2	139796	50000	0	0	10000	50010	140036	140036	140036	140036	140036
60024	140035	1048	0	0	0	0	0	0	0	140020	139639	25	70010	50010	10000	10000	40010	10000	10000	1245753	5326922	5349557	0	140011	140035	140035	131983	3	132443	60010	40020	10000	10000	70020	20000	10000	140035	140035	1	1	50021	10	9	10	40010	10000	10000	10	10000	0	10000	0	0	6	10000	0	0	0	3140	0	0	0	2	88	0	0	2	2	139753	50000	0	0	10000	50010	140036	140036	140036	140036	140036
60024	140035	1049	0	0	0	0	0	0	0	140020	139639	25	70010	50010	10000	10000	40010	10000	10000	1245753	5326922	5349557	0	140011	140035	140035	131983	3	132443	60010	40020	10000	10000	70020	20000	10000	140035	140035	1	1	50021	10	9	10	40010	10000	10000	10	10000	0	10000	0	0	0	10000	0	0	0	3140	0	0	0	2	88	0	0	2	2	139784	50000	0	0	10000	50010	140036	140036	140036	140036	140036
60024	140035	1049	0	0	0	0	3	0	0	140020	139639	25	70010	50010	10000	10000	40010	10000	10000	1245753	5326922	5349557	0	140011	140035	140035	131983	3	132443	60010	40020	10000	10000	70020	20000	10000	140035	140035	1	1	50021	10	9	10	40010	10000	10000	10	10000	0	10000	0	0	0	10000	0	0	0	3140	0	0	0	2	88	0	0	2	2	139755	50000	0	0	10000	50010	140036	140036	140036	140036	140073
60024	140035	1049	0	0	0	0	0	0	0	140020	139639	25	70010	50010	10000	10000	40010	10000	10000	1245753	5326922	5349557	0	140016	140035	140035	131983	3	132443	60010	40020	10000	10000	70020	20000	10000	140035	140035	1	1	50021	10	9	10	40010	10000	10000	10	10000	0	10000	0	0	0	10000	0	0	0	3140	0	0	0	2	17	0	0	2	2	139709	50000	0	0	10000	50010	140036	140036	140036	140036	140036

Test 4: throughput

Count: 8

Code:

  ldr q0, [x6, x7, lsl #4]
  ldr q0, [x6, x7, lsl #4]
  ldr q0, [x6, x7, lsl #4]
  ldr q0, [x6, x7, lsl #4]
  ldr q0, [x6, x7, lsl #4]
  ldr q0, [x6, x7, lsl #4]
  ldr q0, [x6, x7, lsl #4]
  ldr q0, [x6, x7, lsl #4]

Initialization

  mov x7, 8

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.3340

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk instruction (07)	mmu table walk data (08)	l2 tlb miss instruction (0a)	l2 tlb miss data (0b)	0e	0f	18	19	1e	1f	22	23	3a	3f	43	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	67	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	92	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	a5	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
160206	26748	201	1	1	0	1	0	0	0	0	0	21	0	1	0	1	26703	0	7	7	1	25	160118	80117	80000	80120	80017	400606	1169543	1	26713	26718	26718	6663	6	6667	160142	80220	80024	80224	160048	26896	26792	1	1	80201	100	99	0	100	100	80000	80000	0	100	80019	21	0	0	80059	1	0	1	64	80039	0	0	19	0	19	0	1	1	1	5117	2	16	1	1	26737	80016	13	13	1	80000	80100	26741	26719	26741	26719	26719
160204	26718	200	1	1	0	1	0	0	0	0	0	66	0	0	0	1	26725	0	7	7	2	25	160117	80116	80000	80124	80016	400600	1168765	0	26713	26739	26740	6663	6	6689	160136	80224	80024	80224	160048	26897	26788	1	1	80201	100	99	0	100	100	80000	80000	0	100	80020	21	0	0	80019	1	1	0	64	80000	6	0	19	0	19	1	1	1	1	5117	1	16	1	1	26715	80016	0	13	0	80000	80100	26741	26741	26741	26741	26741
160204	26718	200	1	1	2	1	1	0	0	0	0	20	0	0	0	2	26703	0	7	0	2	25	160112	80116	80000	80120	80017	400600	1171513	0	26691	26718	26740	6641	6	6667	160143	80220	80024	80224	160040	26749	26721	1	1	80201	100	99	0	100	100	80000	80000	0	100	80020	20	0	0	80059	1	0	1	20	80000	0	1	58	44	19	0	1	1	1	5117	1	16	1	1	26737	80016	0	0	1	80000	80100	26741	26741	26741	26741	26741
160204	26718	200	1	1	0	1	0	0	0	0	0	20	0	1	0	0	26703	0	0	0	0	25	160118	80116	80000	80120	80018	400595	1168765	0	26691	26718	26718	6641	6	6667	160136	80224	80024	80224	160048	26740	26740	1	1	80201	100	99	0	100	100	80000	80000	0	100	80018	19	43	0	80059	0	1	0	20	80000	0	0	19	0	19	1	1	1	1	5117	1	16	1	1	26725	80016	0	13	1	80000	80100	26719	26741	26741	26719	26741
160204	26740	201	1	1	1	1	0	0	0	0	0	20	0	1	0	0	26703	0	0	0	0	25	160116	80116	80000	80124	80016	400596	1163174	3	26923	26740	26740	6641	6	6688	160143	80224	80024	80224	160048	26925	26798	1	1	80201	100	99	0	100	100	80000	80000	0	100	80020	19	44	0	80060	1	0	1	20	80040	0	0	59	44	19	2	1	1	1	5117	1	16	1	1	26715	80016	0	0	1	80000	80100	26719	26741	26719	26741	26719
160204	26718	202	1	1	0	1	1	0	0	0	0	67	0	1	0	0	26703	3	7	7	2	25	160116	80116	80000	80124	80019	400588	1164637	1	26691	26740	26740	6641	6	6688	160134	80224	80024	80224	160048	26871	26783	1	1	80201	100	99	0	100	100	80000	80000	0	100	80020	20	0	0	80019	1	1	2	20	80000	6	0	19	0	19	1	1	1	1	5117	1	16	1	1	26715	80016	13	13	1	80000	80100	26719	26741	26741	26741	26719
160204	26740	200	1	1	1	1	1	0	0	0	0	67	0	0	0	0	26725	2	7	7	19	25	160116	80116	80000	80120	80018	400604	1169543	0	26713	26718	26718	6641	6	6667	160142	80224	80024	80224	160048	26822	26852	1	1	80201	100	99	0	100	100	80000	80000	0	100	80020	20	43	0	80019	0	1	1	63	80040	0	0	58	0	19	1	1	1	1	5117	1	16	1	1	26737	80016	13	13	1	80000	80100	26741	26719	26719	26719	26719
160204	26718	200	1	1	1	1	1	0	0	0	0	22	0	0	0	1	26705	0	0	0	0	25	160117	80116	80000	80120	80017	400593	1163174	0	26713	26718	26718	6641	6	6667	160137	80224	80024	80224	160040	26779	26817	1	1	80201	100	99	0	100	100	80000	80000	0	100	80019	21	0	0	80060	0	1	1	20	80040	6	0	19	44	19	1	1	1	1	5117	1	16	1	1	26737	80176	0	0	1	80000	80100	26741	26722	26722	26719	26743
160204	26718	200	1	1	1	1	0	0	0	0	0	20	0	0	0	1	26703	0	7	7	2	25	160117	80116	80000	80124	80015	400592	1164781	0	26713	26718	26718	6663	6	6688	160143	80224	80024	80224	160048	26924	26768	1	1	80201	100	99	0	100	100	80000	80000	0	100	80019	19	44	0	80059	1	1	0	63	80171	6	0	19	44	19	0	1	1	1	5117	1	16	1	1	26715	80016	0	13	0	80000	80100	26719	26719	26741	26719	26719
160204	26740	207	1	1	1	1	0	0	0	0	0	111	0	1	0	1	26727	0	7	7	2	25	160116	80116	80000	80124	80015	400604	1171513	0	26713	26718	26718	6663	6	6666	160137	80224	80024	80220	160048	26740	26740	1	1	80201	100	99	0	100	100	80000	80000	0	100	80019	20	0	0	80060	1	0	1	64	80000	0	0	19	44	19	0	1	1	1	5117	1	16	1	1	26731	80016	0	0	1	80000	80100	26719	26741	26741	26741	26720

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.3340

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	09	l2 tlb miss data (0b)	0e	0f	18	19	1e	22	3a	3f	43	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	67	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	92	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	branch mispred nonspec (cb)	cf	d5	map dispatch bubble (d6)	da	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
160026	26723	200	1	1	1	0	1	0	0	0	20	0	3	26723	0	7	0	0	25	160010	80010	80000	80010	80000	400050	1168681	0	0	26691	26716	26716	6661	3	6696	160010	80020	80000	80020	160000	26716	26716	1	1	80021	10	9	0	10	10	80000	80000	1	10	80019	20	44	80019	0	0	0	63	80000	6	1	19	44	19	2	0	5020	3	16	5	3	3	26732	80000	13	0	0	80000	80010	26717	26739	26717	26717	26717
160024	26738	200	1	0	1	1	0	1	0	0	20	0	0	26705	0	0	0	2	25	160010	80010	80000	80010	80000	400050	1172113	0	2	26714	26738	26738	6661	3	6696	160010	80020	80000	80020	160000	26716	26716	1	1	80021	10	9	0	10	10	80000	80000	0	10	80019	20	0	80061	1	0	1	61	80000	0	0	19	0	19	0	0	5020	3	16	6	4	3	26713	80000	0	13	0	80000	80010	26717	26717	26720	26720	26718
160024	26717	202	1	0	1	0	0	0	0	0	182	0	1	26939	0	0	0	0	25	160010	80010	80000	80010	80000	400050	1176587	1	0	26691	26716	26716	6661	3	6696	160010	80020	80000	80020	160000	26716	26716	1	1	80021	10	9	0	10	10	80000	80000	0	10	80020	19	0	80019	2	1	1	20	80000	0	0	19	0	19	1	0	5020	3	16	7	3	3	26973	80000	0	0	0	80000	80010	26717	26717	26717	26717	26717
160024	26716	200	1	0	1	1	0	0	0	0	20	0	1	26701	0	0	0	0	25	160010	80010	80000	80010	80000	400050	1168681	1	1	26691	26716	26738	6665	3	6704	160010	80020	80000	80020	160000	26716	26716	1	1	80021	10	9	0	10	10	80000	80000	0	10	80020	20	44	80019	1	2	1	64	80000	0	0	19	0	19	1	0	5020	2	16	5	3	3	26880	80000	13	0	1	80000	80010	26717	26740	26717	26717	26717
160024	26716	200	1	1	1	1	0	0	0	0	21	0	1	26711	0	0	7	44	25	160304	80174	80000	80010	80000	400050	1168595	1	0	26713	26720	26738	6665	3	6696	160010	80020	80000	80020	160000	26721	26724	1	1	80021	10	9	0	10	10	80000	80000	0	10	80021	19	0	80060	1	0	1	20	80000	0	1	19	0	19	0	0	5020	3	16	5	3	3	26985	80000	0	0	0	80000	80010	26717	26717	26717	26717	26717
160024	26716	200	1	1	1	0	0	0	0	0	66	0	0	26723	2	0	0	0	25	160010	80010	80000	80010	80000	400050	1163081	1	1	26691	26716	26720	6661	3	6718	160010	80020	80000	80020	160000	26716	26720	1	1	80021	10	9	0	10	10	80000	80000	0	10	80021	19	0	80059	0	0	0	20	80000	0	0	19	44	19	1	0	5020	3	16	5	2	3	26966	80000	13	13	1	80000	80010	26717	26717	26718	26717	26718
160024	26742	200	1	1	1	1	0	0	0	0	32	0	1	26701	0	0	0	10	25	160010	80010	80000	80010	80000	400050	1168681	1	0	26691	26738	26716	6661	3	6696	160010	80020	80000	80020	160000	26716	26716	1	1	80021	10	9	0	10	10	80000	80000	0	10	80019	19	44	80019	1	0	0	20	80000	0	0	59	44	19	1	0	5020	3	16	6	4	3	26722	80000	0	0	0	80000	80010	26739	26720	26725	26721	26739
160024	26740	200	1	0	0	0	0	0	0	0	20	1	1	26701	0	0	0	19	25	160010	80010	80000	80010	80000	400050	1168595	1	0	26691	26716	26716	6661	3	6696	160010	80020	80000	80020	160000	26716	26716	1	1	80021	10	9	0	10	10	80000	80000	0	10	80019	20	0	80059	0	0	0	63	80041	6	1	19	0	19	1	0	5020	2	16	6	3	3	26735	80000	0	0	0	80000	80010	26717	26717	26717	26717	26717
160024	26716	200	1	1	1	0	0	0	0	0	20	0	3	26701	0	0	0	2	25	160010	80010	80000	80010	80000	400050	1171762	1	0	26692	26716	26716	6661	3	6696	160010	80020	80000	80020	160000	26716	26738	1	1	80021	10	9	0	10	10	80000	80000	0	10	80020	19	0	80060	0	0	1	64	80000	0	0	19	0	19	1	0	5020	3	16	6	4	4	26713	80000	13	0	0	80000	80010	26718	26717	26717	26717	26717
160024	26716	200	1	1	1	1	0	0	0	0	20	0	1	26701	2	0	7	0	25	160010	80010	80000	80010	80000	400050	1163081	1	0	26713	26738	26716	6683	3	6718	160010	80020	80000	80020	160000	26716	26716	1	1	80021	10	9	0	10	10	80000	80000	1	10	80019	19	0	80019	1	0	0	63	80000	0	0	19	0	19	1	0	5020	2	16	6	3	3	26799	80000	13	0	1	80000	80010	26725	26750	26717	26717	26717

LDR (register, lsl, Q)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->2 roundtrip

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: Latency 1->3 roundtrip

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 4: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations