Firestorm: LDR (register, lsl, S) measurements

Code:

  ldr s0, [x6, x7, lsl #2]

Initialization

  mov x7, #4
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 1.000

SIMD/FP unit issues: 0.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	0e	0f	1e	22	24	3a	3f	43	46	49	4f	51	schedule uop (52)	schedule ldst uop (55)	dispatch ldst uop (58)	simd uops in schedulers (5a)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map ldst uop (7d)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst simd load (98)	inst ldst (9b)	9d	l1d tlb access (a0)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	ea	eb	ec	? ldst retires (ed)	f5	f6	f7	f8	fd
1005	389	3	1	1	41	1	0	1	374	2	18	0	12	25	1000	1000	1000	14838	1	349	391	389	212	3	232	1000	1000	2000	389	374	1	1	1001	1000	1000	0	1000	39	1035	0	0	1036	6	1	35	39	73	1	16	1	1	371	0	6	0	1000	375	375	375	390	390
1004	389	2	0	0	41	1	0	1	359	2	0	0	12	25	1000	1000	1000	14060	0	364	391	374	212	3	247	1000	1000	2000	389	389	1	1	1001	1000	1000	0	1000	39	1000	0	35	1035	6	1	0	39	73	1	16	1	1	371	6	6	2	1000	390	375	390	375	375
1004	374	3	0	0	45	1	0	2	359	2	0	12	16	25	1000	1000	1000	14838	1	364	374	374	197	3	232	1000	1000	2000	394	389	1	1	1001	1000	1000	0	1000	0	1000	0	39	1000	0	1	39	43	73	1	16	1	1	371	0	6	0	1000	395	375	395	390	390
1004	394	3	0	0	45	0	0	0	359	0	12	12	16	25	1000	1000	1000	14060	0	369	394	394	217	3	252	1000	1000	2000	374	389	1	1	1001	1000	1000	0	1000	0	1035	0	0	1039	0	1	39	0	73	1	16	1	1	391	0	6	4	1000	395	375	395	395	395
1004	374	3	0	0	45	0	0	2	374	2	12	12	0	25	1000	1000	1000	14060	1	369	374	394	217	3	252	1000	1000	2000	374	389	1	1	1001	1000	1000	0	1000	0	1039	0	0	1039	6	1	35	0	73	1	16	1	1	391	0	0	0	1000	390	375	395	395	395
1004	394	3	0	0	45	0	0	2	379	2	12	12	16	25	1000	1000	1000	14774	0	369	374	394	217	3	232	1000	1000	2000	389	374	1	1	1001	1000	1000	0	1000	0	1039	0	39	1039	6	0	35	0	73	1	16	1	1	386	6	6	0	1000	395	395	395	395	395
1004	394	3	0	0	45	0	0	2	374	2	12	0	16	25	1000	1000	1000	14989	1	349	374	394	197	3	252	1000	1000	2000	394	374	1	1	1001	1000	1000	0	1000	39	1039	0	42	1000	0	0	35	43	73	1	16	1	1	371	10	10	4	1000	395	395	395	375	395
1004	394	3	0	0	46	1	0	0	359	2	0	12	0	25	1000	1000	1000	14060	1	349	394	374	217	3	247	1000	1000	2000	374	374	1	1	1001	1000	1000	0	1000	39	1039	0	39	1039	0	1	35	43	73	1	16	1	1	391	10	0	4	1000	395	395	395	395	395
1004	394	3	0	1	45	0	0	0	379	0	12	12	16	25	1000	1000	1000	14989	1	364	374	394	212	3	232	1000	1000	2000	389	374	1	1	1001	1000	1000	0	1000	39	1000	0	35	1035	0	0	35	39	73	1	16	1	1	391	10	10	2	1000	395	395	395	395	395
1004	394	2	0	0	45	0	0	0	359	0	12	0	16	25	1000	1000	1000	14838	1	369	394	374	197	3	252	1000	1000	2000	394	374	1	1	1001	1000	1000	0	1000	0	1039	0	0	1039	6	0	39	0	73	1	16	1	1	391	6	6	2	1000	395	395	375	395	395

Test 2: Latency 1->2 roundtrip

Chain cycles: 3

Code:

  ldr s0, [x6, x7, lsl #2]
  fmov x0, d0
  eor x8, x8, x0
  eor x8, x8, x0
  add x6, x6, x8

Initialization

  mov x7, #4
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 9.0050

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	09	l2 tlb miss data (0b)	0e	0f	18	19	1e	1f	22	23	24	3a	3f	4d	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	af	b5	l1d cache miss ld nonspec (bf)	c2	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
50205	120047	899	0	1	0	0	0	0	0	168	88	0	0	0	0	120020	119493	109514	25	60103	40102	10001	10000	30111	10008	10155	1078014	5736422	6134359	120026	120035	120050	113233	7	113939	50122	30228	10010	10010	60256	20452	10010	120050	120047	1	1	50201	100	99	100	40100	10000	10000	1	100	10000	0	1	10000	0	0	0	10000	1	1	0	1	1	1	3251	0	16	0	0	119730	40002	6	6	8	10000	40100	120051	120051	120051	120051	120036
50204	120035	899	0	0	0	0	0	0	0	1	0	1	0	0	0	120394	119493	109528	25	60100	40102	10001	10000	30108	10008	10006	1079035	5746052	6134928	120026	120050	120035	113218	7	113748	50122	30228	10010	10010	60256	20020	10010	120035	120047	1	1	50201	100	99	100	40100	10000	10000	0	100	10008	0	1	10000	3	0	0	10000	0	1	0	1	1	1	3221	0	16	0	0	119736	40000	9	0	5	10000	40100	120051	120051	120036	120051	120051
50204	120050	899	0	0	0	0	0	0	0	0	0	0	0	0	0	120085	119493	109527	25	60103	40100	10001	10000	30108	10008	10202	1079111	5735695	6134359	120026	120053	120421	113233	7	113734	50122	30228	10010	10010	60256	20020	10010	120035	120035	1	1	50201	100	99	100	40100	10000	10000	0	100	10000	0	0	10000	0	0	0	10000	1	1	0	1	1	1	3221	0	16	1	0	119727	40002	6	9	0	10000	40100	120051	120423	120052	120051	120036
50204	120050	899	1	0	0	0	1	0	0	3	0	0	0	0	0	120032	119493	109514	25	60100	40102	10001	10000	30108	10218	10006	1079084	5735695	6134928	120011	120050	120047	113233	7	113753	50128	30228	10010	10010	60256	20020	10010	120050	120047	1	1	50201	100	99	100	40100	10000	10000	0	100	10000	0	0	10000	0	0	9	10000	1	1	0	1	1	1	3221	3	16	0	0	119736	40002	0	9	0	10000	40100	120051	120051	120048	120051	120051
50204	120035	900	0	0	1	1	1	4	0	12	0	0	0	0	0	120128	119519	109463	25	60100	40102	10001	10000	30100	10000	10000	1078889	5736284	6136166	120026	120050	120035	113145	3	113667	50100	30200	10000	10000	60200	20000	10000	120050	120035	1	1	50202	100	99	100	40100	10000	10000	0	100	10000	0	1	10000	0	0	0	10000	0	1	0	0	0	0	3210	1	101	1	1	119646	40000	6	9	8	10000	40100	120139	120052	120051	120051	120150
50204	120346	902	0	0	0	0	0	1	4	1	0	1	0	0	0	120035	119512	109463	25	60103	40102	10000	10000	30100	10000	10000	1079017	5736188	6133818	120023	120035	120035	113145	3	113636	50100	30200	10000	10000	60200	20000	10000	120054	120048	1	1	50201	100	99	100	40100	10000	10000	0	100	10000	0	1	10000	3	0	0	10005	1	0	0	0	0	0	3326	1	107	1	1	119660	40002	0	0	5	10000	40100	120051	120051	120048	120048	120051
50204	120407	899	0	0	0	0	0	4	0	1	0	0	0	0	0	120032	119509	109449	133	60103	40100	10000	10000	30100	10000	10000	1078999	5735455	6133977	120312	120050	120050	113141	3	113667	51089	30200	10000	10000	60200	20000	10000	120047	120092	1	1	50201	100	99	100	40100	10000	10000	1	100	10000	0	1	10008	0	0	0	10000	0	1	0	0	0	0	3325	1	135	1	1	119657	40054	6	6	8	10000	40100	120051	120048	120051	120048	120051
50204	120050	899	0	0	0	0	0	0	0	0	0	0	0	0	0	120032	119509	109449	25	60103	40102	10000	10000	30100	10000	10000	1088427	5736332	6136166	120030	120035	120050	113143	3	113658	50100	30200	10000	10000	60574	20000	10000	120051	120233	1	1	50201	100	99	100	40100	10000	10000	1	100	10000	0	1	10000	0	0	0	10000	1	0	0	0	0	0	3210	1	101	2	2	119657	40002	6	10	8	10000	40100	120048	120036	120051	120051	120036
50204	120035	899	0	0	0	0	0	0	0	0	0	0	0	0	0	120053	119509	109463	25	60103	40102	10001	10000	30100	10000	10000	1078999	5735455	6133818	120026	120035	120050	113141	3	113667	50100	30200	10000	10000	60200	20000	10000	120050	120047	1	1	50201	100	99	100	40100	10000	10000	0	100	10000	0	1	10000	0	0	3	10000	1	1	0	0	0	0	3210	1	107	1	1	119657	40002	9	9	0	10000	40100	120036	120051	120051	120051	120036
50204	120050	899	0	0	0	0	0	0	0	1	0	0	0	0	0	120032	119519	109449	25	60103	40100	10000	10000	30100	10000	10000	1078999	5736236	6145144	120026	120432	120050	113145	3	113658	50100	30200	10000	10000	61494	20000	10000	120050	120035	1	1	50201	100	99	100	40100	10000	10000	0	100	10000	0	0	10000	0	0	0	10000	1	1	0	0	0	0	3210	1	135	1	3	119657	40002	9	6	5	10000	40100	120051	120051	120051	120048	120051

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 9.0051

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	09	0e	0f	19	1e	22	23	3a	3f	4d	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	ac	af	b5	l1d cache miss ld nonspec (bf)	branch mispred nonspec (cb)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
50025	120051	899	1	0	0	0	664	1	0	0	120036	119518	109449	25	60013	40012	10001	10000	30010	10000	10000	1079810	5736860	6134699	0	120011	120051	120051	113169	3	113690	50010	30020	10000	10000	60020	20000	10000	120051	120051	1	1	50021	10	9	10	40010	10000	10000	0	10	10000	0	1	10000	0	0	10000	1	1	0	3140	9	107	10	9	119666	40002	11	10	9	10000	40010	120052	120052	120052	120052	120052
50024	120051	900	0	0	0	0	1	1	0	0	120036	119509	109464	25	60013	40021	10001	10000	30010	10000	10000	1079953	5736812	6133866	0	120027	120051	120051	113169	3	113690	50010	30020	10000	10000	60020	20000	10000	120051	120051	1	1	50021	10	9	10	40010	10000	10000	0	10	10000	0	1	10000	0	0	10000	1	1	0	3140	9	107	9	11	119666	40002	10	10	9	10000	40010	120052	120036	120052	120052	120052
50024	120051	899	0	0	0	0	1	1	0	0	120036	119509	109464	25	60013	40012	10001	10000	30010	10000	10000	1080133	5737676	6133764	0	120027	120051	120051	113169	3	113690	50010	30020	10000	10000	60020	20000	10000	120051	120057	1	1	50021	10	9	10	40010	10000	10000	0	10	10000	0	1	10000	0	0	10000	1	1	0	3140	10	107	11	8	119666	40002	10	10	9	10000	40010	120052	120052	120052	120052	120052
50024	120051	899	0	0	0	0	1	1	0	0	120020	119509	109464	25	60013	40012	10001	10000	30010	10000	10000	1080115	5737772	6133931	0	120027	120051	120051	113169	3	113690	50010	30020	10000	10000	60020	20000	10000	120051	120051	1	1	50021	10	9	10	40010	10000	10000	0	10	10000	0	1	10000	0	3	10000	1	1	0	3140	10	107	10	9	119666	40000	10	10	9	10000	40010	120052	120052	120052	120052	120052
50024	120035	900	0	0	0	0	1	1	0	0	120036	119509	109464	25	60013	40012	10001	10000	30010	10000	10000	1080124	5736380	6133662	0	120027	120051	120051	113169	3	113690	50010	30020	10000	10000	60020	20000	10000	120051	120051	1	1	50021	10	9	10	40010	10000	10000	0	10	10000	0	1	10000	0	0	10000	1	1	0	3140	11	107	18	12	119666	40000	10	10	9	10000	40010	120052	120052	120036	120052	120052
50024	120051	899	0	0	0	0	1	1	0	0	120065	119509	109464	25	60013	40012	10001	10000	30010	10000	10000	1080385	5736380	6133662	0	120027	120051	120051	113169	3	113690	50010	30020	10000	10000	60020	20000	10000	120035	120051	1	1	50021	10	9	10	40010	10000	10000	0	10	10000	0	1	10000	0	0	10000	1	1	0	3140	9	107	9	11	119666	40002	10	10	9	10000	40010	120052	120052	120052	120052	120052
50024	120051	899	0	0	0	0	1	1	0	0	120036	119509	109449	25	60010	40012	10001	10000	30010	10000	10000	1080034	5737292	6133968	0	120027	120035	120051	113169	3	113690	50010	30020	10000	10000	60020	20000	10000	120051	120051	1	1	50021	10	9	10	40010	10000	10000	0	10	10000	0	1	10000	1	0	10000	0	0	0	3140	11	107	11	9	119666	40002	10	10	9	10000	40010	120052	120036	120052	120036	120052
50024	120051	900	0	0	0	0	1	0	0	0	120039	119509	109464	25	60010	40010	10000	10000	30010	10000	10000	1079647	5736236	6133662	0	120027	120051	120051	113169	3	113674	50010	30020	10000	10000	60020	20000	10000	120051	120035	1	1	50021	10	9	10	40010	10000	10000	0	10	10000	0	1	10000	0	0	10000	0	1	0	3140	10	107	9	10	119667	40002	10	10	9	10000	40010	120052	120052	120036	120052	120052
50024	120051	899	0	0	0	0	0	1	0	0	120036	119509	109464	25	60013	40012	10001	10000	30010	10000	10000	1079584	5736236	6133662	0	120027	120051	120051	113169	3	113690	50010	30020	10000	10000	60020	20000	10000	120051	120051	1	1	50021	10	9	10	40010	10000	10000	0	10	10000	0	1	10000	0	0	10000	0	1	0	3140	10	107	11	9	119666	40002	10	10	9	10000	40010	120052	120052	120036	120052	120052
50024	120051	899	0	0	0	0	1	1	0	0	120037	119509	109464	25	60013	40012	10001	10000	30010	10000	10000	1079620	5736236	6132757	0	120027	120051	120051	113169	3	113690	50010	30020	10000	10000	60020	20000	10000	120051	120051	1	1	50021	10	9	10	40010	10000	10000	0	10	10000	0	1	10000	0	0	10000	1	0	0	3140	9	107	9	11	119666	40002	10	10	9	10000	40010	120036	120052	120052	120052	120036

Test 3: Latency 1->3 roundtrip

Chain cycles: 3

Code:

  ldr s0, [x6, x7, lsl #2]
  fmov x0, d0
  eor x8, x8, x0
  eor x8, x8, x0
  add x7, x7, x8

Initialization

  mov x7, #4
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 9.0051

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	09	l2 tlb miss data (0b)	0e	0f	18	19	1e	1f	22	23	24	3f	4d	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	69	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	af	b5	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	cf	d0	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
50205	120047	899	0	0	0	1	0	0	0	0	0	0	0	0	120032	119519	109461	25	60103	40102	10001	10000	30100	10000	10000	1079200	5735455	6135338	0	120023	0	120047	120047	113143	3	113636	50100	30200	10000	10000	60200	20000	10000	120047	120035	1	1	50201	100	99	100	40100	10000	10000	1	100	10000	0	10000	0	0	0	10000	1	0	0	0	0	3210	0	3	135	2	2	119660	40002	6	6	5	10000	40100	120048	120051	120048	120048	120048
50204	120047	900	0	0	0	0	0	0	0	1	0	1	0	0	120032	119519	109461	25	60103	40102	10000	10000	30100	10000	10000	1079200	5735455	6134461	1	120023	0	120050	120047	113145	3	113636	50100	30200	10000	10000	60200	20000	10000	120047	120047	1	1	50201	100	99	100	40100	10000	10000	0	100	10000	0	10000	1	0	0	10000	1	0	1	0	0	3210	0	2	135	2	2	119660	40002	6	6	5	10000	40100	120048	120048	120048	120048	120048
50204	120047	899	0	0	0	0	0	0	0	1	0	1	0	0	120032	119493	109461	25	60100	40102	10001	10000	30100	10062	10000	1079200	5736044	6133818	0	120023	0	120047	120035	113145	3	113636	50100	30200	10000	10000	60200	20000	10000	120035	120047	1	1	50201	100	99	100	40100	10000	10000	0	100	10000	1	10000	0	0	0	10000	1	0	1	0	0	3210	0	2	135	2	2	119704	40000	6	0	5	10000	40100	120048	120048	120048	120036	120036
50204	120047	900	0	0	0	0	0	0	0	0	0	1	0	0	120035	119493	109449	25	60100	40102	10001	10000	30100	10000	10000	1079200	5735455	6133818	0	120023	0	120035	120047	113143	3	113636	50100	30200	10000	10000	60200	20000	10000	120035	120047	1	1	50201	100	99	100	40100	10000	10000	0	100	10000	0	10000	1	0	0	10000	1	0	1	0	0	3210	0	2	135	2	2	119660	40002	6	0	5	10000	40100	120051	120048	120048	120036	120048
50204	120035	899	0	0	0	0	0	0	0	0	0	1	0	0	120032	119519	109461	25	60103	40102	10000	10000	30100	10000	10000	1079200	5735455	6133818	1	120023	0	120035	120047	113141	3	113636	50100	30200	10000	10000	60200	20000	10065	120047	120047	1	1	50201	100	99	100	40100	10000	10000	0	100	10000	0	10000	0	0	0	10000	1	0	1	0	0	3210	0	2	135	2	2	119660	40002	9	6	5	10000	40100	120048	120048	120048	120036	120048
50204	120047	899	0	0	0	0	0	0	0	1	0	1	0	0	120032	119509	109461	25	60100	40102	10001	10000	30100	10000	10000	1079200	5735455	6133920	1	120023	0	120047	120047	113143	3	113658	50100	30391	10000	10000	60200	20000	10000	120035	120057	1	1	50201	100	99	100	40100	10000	10000	0	100	10000	0	10000	0	0	3	10000	1	0	1	0	0	3210	0	2	135	2	2	119660	40002	9	6	0	10000	40100	120048	120036	120048	120048	120048
50204	120047	899	0	0	0	0	0	0	0	1	0	1	0	0	120032	119519	109447	25	60103	40102	10000	10000	30100	10000	10000	1079200	5736044	6133818	0	120023	0	120047	120047	113141	3	113658	50100	30200	10000	10000	60200	20000	10000	120035	120047	1	1	50201	100	99	100	40100	10000	10000	0	100	10000	1	10000	0	0	0	10000	1	0	1	0	0	3210	0	2	107	2	2	119646	40002	6	6	0	10000	40100	120048	120048	120048	120036	120048
50204	120152	899	0	0	0	0	0	0	0	1	0	0	0	0	120032	119519	109449	25	60103	40102	10000	10000	30100	10000	10000	1079200	5736044	6133818	0	120011	0	120047	120047	113143	3	113636	50100	30200	10000	10000	60200	20000	10000	120035	120047	1	1	50201	100	99	100	40100	10000	10000	0	100	10000	0	10000	0	0	0	10000	1	0	1	0	0	3210	0	2	135	2	2	119725	40002	6	0	5	10000	40100	120036	120036	120048	120048	120048
50204	120035	899	0	0	0	0	0	0	0	1	0	1	0	0	120032	119519	109461	25	60103	40102	10001	10000	30100	10000	10000	1079200	5736044	6133818	1	120023	0	120035	120076	113143	3	113636	50100	30200	10000	10000	60200	20000	10000	120050	120035	1	1	50201	100	99	100	40100	10000	10000	0	100	10000	1	10000	0	0	0	10000	1	0	1	0	0	3210	0	3	305	5	2	121538	40211	0	6	5	10000	40100	122340	122312	122319	122336	122424
50204	122423	917	0	1	0	0	1	25	26	3445	2200	1	0	0	120035	119493	109503	25	60100	40182	10024	10026	31970	10423	11086	1132683	5791927	6174220	1	122079	0	122594	122039	113851	268	115094	55008	33442	11389	11454	66950	22892	11496	122563	122303	28	1	50201	100	99	100	40100	10000	10000	0	100	10033	0	10038	0	2	91340	10032	1	0	1	0	2	3378	32	5	289	9	4	122315	40380	10	10	0	10000	40100	120052	120052	120052	121694	123690

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 9.0047

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	l2 tlb miss data (0b)	0e	0f	18	1e	1f	22	23	3f	4d	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	69	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	ac	af	b5	l1d cache miss ld nonspec (bf)	c2	branch mispred nonspec (cb)	cd	cf	d0	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
50025	120047	899	0	0	1	0	0	1	0	1	0	120032	119505	109461	25	60010	40010	10000	10000	30010	10000	10000	1079523	5736044	6133499	0	120023	0	120047	120047	113153	3	113686	50010	30020	10000	10000	60020	20000	10000	120035	120047	1	1	50021	10	9	10	40010	10000	10000	0	10	10001	1	10000	0	0	10000	1	1	0	0	0	3140	0	6	107	5	4	119662	40002	6	6	5	10000	40010	120048	120048	120138	120048	120048
50024	120047	899	0	0	0	0	0	1	0	1	0	120032	119508	109461	25	60013	40012	10001	10000	30010	10000	10000	1079523	5736044	6133499	0	120023	0	120047	120047	113165	3	113686	50010	30020	10000	10000	60020	20000	10000	120047	120047	1	1	50021	10	9	10	40010	10000	10000	0	10	10000	1	10000	0	0	10000	1	1	0	0	0	3140	0	4	107	5	4	119662	40002	6	6	5	10000	40010	120048	120048	120048	120048	120048
50024	120047	899	0	0	0	0	0	1	0	1	0	120032	119505	109461	25	60013	40012	10001	10000	30010	10000	10000	1079523	5736044	6133499	0	120062	0	120047	120047	113165	3	113686	50010	30020	10000	10000	60020	20000	10000	120047	120047	1	1	50021	10	9	10	40010	10000	10000	0	10	10000	1	10000	0	0	10000	1	1	0	0	0	3140	0	4	107	4	5	119662	40002	6	6	5	10000	40010	120098	120081	120048	120048	120048
50024	120035	899	0	0	0	0	0	1	0	1	0	120032	119505	109449	25	60013	40012	10001	10000	30010	10000	10000	1079523	5736044	6133499	0	120023	0	120047	120035	113165	3	113686	50010	30020	10000	10000	60020	20000	10000	120047	120047	1	1	50021	10	9	10	40010	10000	10000	0	10	10000	1	10000	0	0	10000	1	1	0	0	0	3140	0	6	107	4	4	119662	40002	6	0	5	10000	40010	120048	120048	120048	120048	120048
50024	120047	899	0	0	0	0	0	1	0	1	0	120032	119505	109461	25	60010	40012	10001	10000	30010	10000	10000	1079523	5736044	6133499	0	120011	0	120035	120047	113165	3	113686	50010	30020	10000	10000	60020	20000	10000	120047	120047	1	1	50021	10	9	10	40010	10000	10000	0	10	10000	1	10000	0	0	10000	0	1	0	0	0	3140	0	4	107	4	5	119662	40002	6	6	5	10000	40010	120049	120048	120048	120048	120048
50024	120047	899	0	0	0	0	0	1	0	1	0	120032	119505	109461	25	60021	40012	10001	10000	30010	10000	10000	1079523	5736044	6133499	0	120023	0	120047	120047	113165	3	113686	50010	30020	10000	10000	60020	20000	10000	120047	120047	1	1	50021	10	9	10	40010	10000	10000	0	10	10000	1	10000	1	0	10000	1	1	0	0	0	3140	0	4	107	4	4	119662	40002	6	6	5	10000	40010	120048	120053	120048	120048	120048
50024	120047	899	0	0	1	0	0	1	0	1	0	120032	119505	109449	25	60013	40012	10000	10000	30010	10000	10000	1079523	5736044	6133499	0	120023	0	120047	120047	113165	3	113686	50010	30020	10000	10000	60020	20000	10000	120047	120047	1	1	50021	10	9	10	40010	10000	10000	0	10	10000	1	10000	0	0	10000	1	1	0	0	0	3140	5	4	107	4	5	119650	40002	6	6	5	10000	40010	120048	120048	120048	120048	120048
50024	120047	899	0	0	0	0	0	1	0	1	0	120032	119505	109461	46	60013	40012	10001	10000	30010	10000	10000	1079523	5736044	6133499	0	120011	0	120097	120035	113165	3	113686	50010	30020	10000	10000	60020	20106	10000	120047	120048	1	1	50021	10	9	10	40010	10000	10000	0	10	10000	1	10000	0	0	10000	1	1	0	0	0	3140	0	4	107	4	5	119662	40002	6	6	0	10000	40010	120048	120048	120036	120048	120048
50024	120047	899	0	0	0	0	0	46	0	0	0	120032	119505	109461	25	60013	40012	10001	10000	30010	10000	10000	1079523	5736044	6133499	0	120023	0	120047	120035	113165	3	113686	50010	30020	10000	10000	60020	20000	10000	120047	120047	1	1	50021	10	9	10	40010	10000	10000	0	10	10000	1	10000	0	0	10000	1	1	0	0	0	3140	0	6	107	5	5	119662	40002	6	0	5	10000	40010	120048	120048	120100	120057	120048
50024	120047	899	0	0	0	1	0	37	0	1	0	120032	119505	109462	25	60013	40012	10001	10000	30010	10000	10000	1079523	5736044	6133499	0	120023	0	120035	120035	113165	3	113686	50010	30020	10000	10000	60020	20000	10000	120047	120047	1	1	50021	10	9	10	40010	10000	10000	0	10	10000	1	10000	0	0	10000	1	1	0	0	0	3140	0	5	107	5	4	119662	40002	6	6	5	10000	40010	120048	120048	120036	120048	120048

Test 4: throughput

Count: 8

Code:

  ldr s0, [x6, x7, lsl #2]
  ldr s0, [x6, x7, lsl #2]
  ldr s0, [x6, x7, lsl #2]
  ldr s0, [x6, x7, lsl #2]
  ldr s0, [x6, x7, lsl #2]
  ldr s0, [x6, x7, lsl #2]
  ldr s0, [x6, x7, lsl #2]
  ldr s0, [x6, x7, lsl #2]

Initialization

  mov x7, 8

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.3341

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l2 tlb miss data (0b)	0e	0f	18	19	1e	22	23	3a	3f	43	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d cache miss ld (a3)	a5	ld unit uop (a6)	l1d cache writeback (a8)	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
80205	26729	200	0	0	1	0	0	45	0	0	1	26730	2	0	0	20	25	80100	100	80000	100	80014	500	1165668	1	26703	26823	26707	16656	6	16684	80115	200	80024	200	160048	26732	26728	1	1	80201	100	99	100	100	80000	80000	0	100	80000	43	0	80000	0	41	80042	0	1	42	0	1	1	1	5118	0	16	0	0	26707	15	0	7	80000	100	26734	26733	26733	26733	26708
80204	26732	201	0	0	0	0	0	44	0	0	0	26692	2	0	1	20	25	80100	100	80000	100	80013	500	1167246	1	26682	26732	26732	16635	6	16659	80115	200	80024	200	160048	26728	26728	1	1	80201	100	99	100	100	80000	80000	0	100	80000	43	0	80042	0	0	80041	0	1	42	44	1	1	1	5118	0	16	0	0	26737	15	0	7	80000	100	26733	26733	26733	26708	26733
80204	26732	200	0	1	1	0	0	44	0	0	1	26717	2	0	1	21	25	80100	100	80000	100	80015	500	1177534	1	26707	26707	26733	16635	6	16684	80114	200	80024	200	160048	26734	26711	1	1	80201	100	99	100	100	80000	80000	0	100	80000	0	31	80000	0	3	80041	3	1	41	0	1	1	1	5118	0	16	0	0	26747	15	0	7	80000	100	26733	26729	26729	26708	26733
80204	26728	200	0	0	0	0	0	44	0	0	1	26717	0	12	1	17	25	80100	100	80000	100	80015	500	1168428	0	26707	26707	26732	16660	6	16684	80115	200	80024	200	160048	26707	26732	1	1	80201	100	99	100	100	80000	80000	0	100	80000	43	0	80042	0	41	80000	0	0	0	44	1	1	1	5118	0	16	0	0	26736	0	15	0	80000	100	26733	26733	26708	26708	26729
80204	26732	200	0	0	0	1	1	45	1	0	1	26692	2	1	1	17	25	80100	100	80000	100	80015	500	1166596	1	26703	26732	26707	16660	6	16684	80116	200	80024	200	160048	26732	26732	1	1	80201	100	99	100	100	80000	80000	0	100	80000	43	0	80042	0	41	80041	0	0	42	0	1	1	1	5118	0	16	0	0	26711	0	11	7	80000	100	26733	26708	26733	26733	26729
80204	26732	200	0	0	0	0	0	44	0	0	1	26717	2	0	12	17	25	80100	100	80000	100	80015	500	1168428	1	26703	26707	26732	16660	6	16659	80113	200	80024	200	160048	26707	26732	1	1	80201	100	99	100	100	80000	80000	0	100	80000	43	0	80041	0	41	80000	3	0	42	44	1	1	1	5118	0	16	0	0	26744	0	15	7	80000	100	26735	26733	26733	26733	26733
80204	26707	200	0	0	0	0	0	44	0	0	0	26692	2	1	0	20	25	80100	100	80000	100	80015	500	1166596	1	26703	26732	26707	16656	6	16684	80115	200	80024	200	160048	26732	26732	1	1	80201	100	99	100	100	80000	80000	0	100	80000	43	0	80000	0	0	80000	0	1	42	44	1	1	1	5118	0	16	0	0	26814	0	15	0	80000	100	26733	26733	26729	26733	26733
80204	26728	200	0	0	0	0	0	47	0	0	0	26692	0	0	1	20	25	80100	100	80000	100	80013	500	1167246	1	26703	26732	26732	16660	6	16659	80114	200	80024	200	160048	26732	26732	1	1	80201	100	99	100	100	80000	80000	0	100	80000	44	0	80041	0	42	80000	3	1	41	43	1	1	1	5118	0	16	0	0	26824	0	11	4	80000	100	26733	26729	26729	26733	26708
80204	26732	200	0	0	0	0	0	45	1	0	1	26717	0	1	1	20	25	80100	100	80000	100	80015	500	1168174	1	26682	26732	26732	16660	6	16659	80113	200	80024	200	160048	26732	26707	1	1	80201	100	99	100	100	80000	80000	0	100	80000	0	0	80041	0	41	80041	0	1	0	44	1	1	1	5118	0	16	0	0	26729	15	0	4	80000	100	26708	26708	26733	26733	26708
80204	26732	200	0	0	0	0	0	44	1	0	1	26717	2	1	1	0	25	80100	100	80000	100	80014	500	1166596	1	26703	26707	26732	16656	6	16684	80113	200	80024	200	160048	26732	26728	1	1	80201	100	99	100	100	80000	80000	1	100	80000	43	0	80041	0	41	80041	3	1	42	44	1	1	1	5118	0	16	0	0	26737	0	11	7	80000	100	26733	26733	26733	26733	26733

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.3341

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	l2 tlb miss data (0b)	0e	0f	18	19	1e	22	24	3a	3f	43	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	a5	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	cf	d5	map dispatch bubble (d6)	db	dd	fetch restart (de)	e0	e7	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
80025	26728	200	0	0	1	0	0	0	45	1	0	0	26693	2	12	0	17	25	80010	10	80000	10	80000	50	1166934	0	26683	26728	26708	16673	3	16688	80010	20	80000	20	160000	26724	26724	1	1	80021	10	9	10	10	80000	80000	0	10	80000	0	39	0	80039	0	0	38	80000	3	1	0	43	5020	2	16	5	2	3	26734	0	0	11	7	4	80000	10	26730	26725	26725	26709	26709
80024	26728	200	0	0	0	0	0	0	45	0	0	2	26714	2	21	0	17	25	80010	10	80000	10	80000	50	1168891	0	26703	26728	26723	16652	3	16708	80010	20	80000	20	160000	26728	26724	1	1	80021	10	9	10	10	80000	80000	1	10	80000	0	39	0	80042	0	0	0	80038	3	0	38	0	5020	4	16	4	3	4	26795	0	0	11	7	0	80000	10	26730	26730	26729	26709	26730
80024	26729	200	0	0	0	0	0	0	45	0	0	0	26713	2	0	12	13	25	80010	10	80000	10	80000	50	1166750	0	26683	26728	26729	16668	3	16709	80010	20	80000	20	160000	26728	26724	1	1	80021	10	9	10	10	80000	80000	1	10	80000	0	0	0	80000	0	0	38	80042	3	1	38	0	5026	2	16	4	3	3	26705	0	0	11	7	0	80000	10	26729	26712	26729	26709	26729
80024	26724	200	0	0	0	0	0	0	0	0	0	2	26725	0	12	0	17	49	80400	10	80130	10	80000	50	1166934	0	26703	26728	26708	16652	3	16708	80010	20	80000	20	160000	26708	26724	1	1	80021	10	9	10	10	80000	80000	0	10	80000	0	39	0	80042	0	0	42	80042	3	0	42	43	5020	2	16	5	2	3	26822	0	0	7	7	4	80000	10	26709	26725	26730	26730	26729
80024	26728	200	0	0	0	0	0	0	45	0	0	0	26714	2	12	12	13	25	80010	10	80000	10	80000	50	1167163	0	26703	26729	26708	16673	3	16688	80010	20	80000	20	160000	26728	26724	1	1	80021	10	9	10	10	80000	80000	0	10	80000	0	0	0	80172	0	0	0	80000	0	1	42	43	5020	2	16	4	2	2	26735	0	0	11	7	0	80000	10	26709	26729	26729	26729	26727
80024	26724	200	0	0	0	0	0	0	0	0	0	2	26693	2	0	0	0	25	80010	10	80000	10	80000	50	1166944	0	26699	26723	26708	16673	3	16709	80010	20	80000	20	160000	26729	26708	1	1	80021	10	9	10	10	80000	80000	0	10	80000	0	39	0	80000	0	0	42	80000	3	0	38	43	5020	2	16	4	2	2	26724	0	2	7	7	2	80000	10	26730	26730	26727	26729	26709
80024	26708	200	0	0	0	0	0	0	0	0	0	0	26709	2	12	12	17	25	80010	10	80000	10	80000	50	1166750	0	26704	26729	26724	16673	3	16688	80010	20	80000	20	160000	26729	26724	1	1	80021	10	9	10	10	80000	80000	0	10	80000	0	39	0	80000	0	0	0	80042	3	0	42	43	5020	3	16	4	2	4	26730	0	0	0	0	4	80000	10	26729	26729	26709	26729	26709
80024	26708	200	0	0	0	0	0	0	45	1	0	0	26693	0	0	12	0	25	80010	10	80000	10	80000	50	1166750	1	26699	26729	26730	16673	3	16708	80010	20	80000	20	160000	26729	26708	1	1	80021	10	9	10	10	80000	80000	0	10	80000	0	39	0	80000	0	0	0	80000	3	1	38	43	5020	3	16	4	4	5	27259	0	0	11	7	2	80000	10	26730	26730	26709	26709	26709
80024	26728	200	0	0	0	0	0	0	41	0	0	2	26714	2	12	12	13	25	80010	10	80000	10	80000	50	1166934	1	26699	26729	26724	16652	3	16709	80010	20	80000	20	160000	26728	26708	1	1	80021	10	9	10	10	80000	80000	1	10	80000	0	0	0	80042	0	0	42	80042	3	0	0	43	5020	2	16	4	2	3	26746	0	0	11	0	0	80000	10	26709	26709	26725	26730	26725
80024	26708	200	0	0	0	0	0	0	41	0	0	2	26711	2	0	0	17	25	80010	10	80000	10	80000	50	1166750	0	26703	26729	26728	16676	3	16688	80010	20	80000	20	160000	26729	26723	1	1	80021	10	9	10	10	80000	80000	0	10	80000	0	39	0	80000	1	0	42	80000	3	0	0	0	5020	2	16	4	3	4	26726	0	0	0	7	4	80000	10	26729	26737	26730	26734	26712

LDR (register, lsl, S)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->2 roundtrip

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: Latency 1->3 roundtrip

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 4: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations