Firestorm: LDR (register, sxtw, D) measurements

Code:

  ldr d0, [x6, w7, sxtw]

Initialization

  mov x7, #4
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 1.000

SIMD/FP unit issues: 0.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	09	l2 tlb miss data (0b)	0e	0f	1e	22	24	3a	3f	43	46	49	4f	51	schedule uop (52)	schedule ldst uop (55)	dispatch ldst uop (58)	simd uops in schedulers (5a)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map ldst uop (7d)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	92	inst simd load (98)	inst ldst (9b)	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	ea	eb	ec	? ldst retires (ed)	f5	f6	f7	f8	fd
1005	394	3	0	0	1	0	0	0	44	1	0	1	383	2	1	1	19	25	1000	1000	1000	15526	0	378	403	403	225	3	260	1000	1000	2000	403	402	1	1	1001	0	1000	1000	1020	20	43	1059	0	0	0	38	1038	6	1	39	44	0	0	73	1	16	1	1	395	14	10	7	1000	399	399	399	399	399
1004	403	3	0	0	0	0	1	1	0	1	0	1	379	2	1	1	19	25	1000	1000	1000	14989	0	373	398	394	221	3	256	1000	1000	2000	398	394	1	1	1001	0	1000	1000	1000	0	43	1038	0	0	0	61	1041	6	1	58	43	19	2	73	1	16	1	1	400	13	13	5	1000	404	404	404	403	404
1004	394	3	0	0	0	0	0	0	45	0	0	1	383	2	1	1	19	25	1000	1000	1000	15037	0	373	398	398	221	3	256	1000	1000	2000	394	394	1	1	1001	0	1000	1000	1000	0	43	1038	0	0	0	39	1038	6	1	38	44	0	0	73	1	16	1	1	391	14	14	4	1000	395	399	399	396	399
1004	398	3	0	0	0	0	0	0	45	0	0	1	383	2	12	1	19	25	1000	1000	1000	15555	0	378	403	403	226	3	260	1000	1000	2000	403	402	1	1	1001	0	1000	1000	1019	19	43	1058	1	0	1	60	1040	6	1	59	43	19	0	73	1	16	1	1	400	13	13	5	1000	404	403	404	404	404
1004	398	3	0	0	0	0	0	0	44	1	0	1	383	2	1	1	19	25	1000	1000	1000	15555	0	378	403	403	225	3	261	1000	1000	2000	403	402	1	1	1001	1	1000	1000	1019	19	43	1060	1	0	0	38	1038	6	1	38	44	0	0	73	1	16	1	1	395	10	10	7	1000	399	399	399	399	399
1004	398	3	0	0	0	0	0	0	53	0	0	1	383	2	1	1	19	25	1000	1000	1000	15274	0	373	398	398	221	3	256	1000	1000	2000	398	394	1	1	1001	0	1000	1000	1000	0	43	1038	0	0	0	61	1039	6	1	58	43	18	0	73	1	16	1	1	400	13	13	5	1000	404	404	404	404	404
1004	398	3	0	0	0	0	0	0	44	0	0	1	383	2	1	1	19	25	1000	1000	1000	15208	0	373	402	398	221	3	256	1000	1000	2000	398	394	1	1	1001	0	1000	1000	1000	0	43	1038	0	0	0	38	1038	6	1	38	44	0	0	73	1	16	1	1	391	14	10	7	1000	395	395	399	399	399
1004	394	3	0	0	0	0	0	0	44	0	0	1	383	2	1	1	19	25	1000	1000	1000	15208	0	373	398	398	221	3	254	1000	1000	2000	398	394	1	1	1001	0	1000	1000	1000	0	43	1039	0	0	0	38	1038	6	1	38	43	0	0	73	1	16	1	1	391	14	14	4	1000	395	399	399	395	399
1004	398	2	0	0	0	0	0	0	44	0	0	1	383	2	1	1	19	25	1000	1000	1000	15267	0	373	398	398	221	3	256	1000	1000	2000	398	394	1	1	1001	0	1000	1000	1000	0	44	1038	0	0	0	38	1038	6	1	38	44	0	0	73	1	16	1	1	395	14	14	7	1000	399	399	399	399	399
1004	398	3	0	0	0	0	0	0	44	0	0	1	379	2	1	1	19	25	1000	1000	1000	15274	0	373	398	398	221	3	256	1000	1000	2000	398	394	1	1	1001	0	1000	1000	1000	0	44	1038	0	0	0	38	1038	6	1	38	44	0	0	73	1	16	1	1	395	14	14	7	1000	395	399	399	399	399

Test 2: Latency 1->2 roundtrip

Chain cycles: 3

Code:

  ldr d0, [x6, w7, sxtw]
  fmov x0, d0
  eor x8, x8, x0
  eor x8, x8, x0
  add x6, x6, x8

Initialization

  mov x7, #4
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 9.0050

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk instruction (07)	l2 tlb miss instruction (0a)	0e	0f	1e	1f	22	23	3f	4d	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	69	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	af	b5	l1d cache miss ld nonspec (bf)	c2	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
50205	120047	899	0	0	0	1	1	0	0	0	120035	119529	109461	25	60103	40102	10001	10000	30100	10000	10000	1078999	5736188	6133818	0	120023	0	120050	120047	113145	3	113658	50100	30200	10000	10000	60200	20000	10000	120050	120047	1	1	50201	100	99	100	40100	10000	10000	0	100	10000	1	10000	0	0	0	10000	1	1	0	0	3210	2	107	2	2	119657	40002	0	6	0	10000	40100	120102	120074	120057	120051	120036
50204	120050	899	0	0	0	0	0	0	1	0	120035	119779	109485	25	60103	40102	10000	10000	30100	10000	10000	1078862	5736188	6133818	0	120011	0	120047	120035	113141	3	113636	50100	30200	10000	10000	60200	20000	10000	120035	120047	1	1	50201	100	99	100	40100	10000	10000	0	100	10000	1	10000	0	0	0	10000	1	1	0	0	3210	2	135	2	2	119660	40002	9	0	5	10000	40100	120104	120078	120051	120036	120051
50204	120035	899	0	0	0	0	0	0	0	0	120035	119511	109449	25	60103	40100	10001	10000	30100	10000	10000	1078999	5736188	6136166	0	120026	0	120035	120050	113143	3	113658	50100	30200	10000	10000	60200	20000	10000	120047	120035	1	1	50201	100	99	100	40100	10000	10000	0	100	10000	1	10000	0	0	0	10000	0	1	0	0	3210	2	135	2	2	119661	40000	9	0	8	10000	40100	120110	120091	120052	120036	120036
50204	120035	899	0	0	0	0	21	0	1	0	120020	119572	109463	25	60103	40102	10001	10000	30100	10000	10000	1078862	5736188	6133818	0	120011	0	120050	120050	113145	3	113667	50100	30200	10000	10000	60200	20000	10000	120035	120047	1	1	50201	100	99	100	40100	10000	10000	0	100	10000	1	10000	0	0	0	10000	1	1	0	0	3210	2	101	3	2	119657	40002	9	0	0	10000	40100	120048	120092	120061	120052	120051
50204	120050	899	0	0	0	0	1	0	1	0	120035	119522	109461	25	60103	40100	10001	10000	30100	10000	10000	1079200	5736188	6136166	0	120011	0	120050	120047	113141	3	113658	50100	30200	10000	10000	60200	20000	10000	120051	120047	1	1	50201	100	99	100	40100	10000	10000	0	100	10000	0	10000	1	0	0	10000	1	1	0	0	3210	2	135	2	2	119646	40002	0	6	5	10000	40100	120107	120087	120054	120051	120048
50204	120047	899	0	0	0	0	1	0	0	0	120032	119564	109461	25	60103	40100	10000	10000	30100	10000	10000	1079200	5736188	6133818	0	120023	0	120035	120036	113148	3	113667	50100	30200	10000	10000	60200	20000	10000	120234	120143	1	1	50201	100	99	100	40100	10000	10000	0	100	10003	1	10005	0	0	0	10000	1	1	0	0	3210	2	101	2	2	119658	40000	9	9	0	10000	40100	120048	120105	120071	120055	120048
50204	120050	899	0	0	0	0	1	0	1	0	120020	119557	109461	25	60103	40102	10000	10000	30100	10000	10000	1078862	5736044	6134461	0	120029	0	120047	120417	113141	3	113669	50100	30200	10000	10000	60200	20000	10000	120075	120047	1	1	50201	100	99	100	40100	10000	10000	0	100	10000	0	10000	0	0	0	10000	1	1	0	0	3210	2	135	2	2	119657	40000	0	0	5	10000	40100	120048	120152	120052	120048	120036
50204	120050	899	0	0	0	0	1	0	0	0	120035	119509	109463	25	60103	40100	10000	10000	30100	10000	10000	1078862	5736188	6133818	0	120026	0	120050	120035	113141	3	113658	50100	30200	10000	10065	60200	20000	10000	120035	120047	1	1	50201	100	99	100	40100	10000	10000	0	100	10000	1	10000	0	0	0	10000	0	1	0	0	3210	2	101	2	2	119658	40002	9	0	0	10000	40100	120095	120066	120051	120051	120036
50204	120050	900	0	0	0	0	1	0	1	0	120020	119573	109461	25	60100	40102	10001	10000	30100	10000	10000	1078862	5736188	6133818	0	120026	0	120047	120047	113145	3	113658	50100	30200	10000	10000	60200	20000	10000	120050	120047	1	1	50201	100	99	100	40100	10000	10000	0	100	10000	1	10000	0	0	0	10000	1	1	0	0	3210	2	107	2	3	119662	40002	6	6	8	10000	40100	120036	120099	120058	120050	120051
50204	120050	899	0	0	0	0	0	0	1	0	120020	119511	109449	53	60103	40102	10001	10000	30100	10052	10000	1079044	5735455	6133818	0	120187	0	120048	120050	113145	21	113658	50100	30200	10000	10000	60200	20000	10000	120050	120056	1	1	50201	100	99	100	40100	10000	10000	1	100	10000	0	10000	0	0	0	10000	1	1	0	0	3210	2	101	2	2	119660	40009	6	6	5	10000	40100	120048	120105	120065	120052	120051

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 9.0051

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	09	0e	0f	1e	22	24	3f	4d	4f	50	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	69	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	ac	af	b5	l1d cache miss ld nonspec (bf)	branch cond mispred nonspec (c5)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
50025	120051	899	1	1	1	1	0	0	120020	119492	109470	0	25	60013	40040	10002	10000	30010	10000	10000	1079517	5735455	6133662	0	120093	0	120035	120035	113177	3	113690	50010	30020	10000	10000	60020	20000	10000	120054	120035	1	1	50021	10	9	10	40010	10000	10000	1	10	10000	0	1	10000	0	0	10000	1	1	0	0	3140	17	107	6	3	119666	40002	13	10	9	10000	40010	120036	120055	120055	120055	120055
50024	120035	900	0	0	0	0	0	0	120020	119512	109464	0	25	60010	40012	10001	10000	30010	10000	10000	1079517	5736236	6133662	1	120030	3	120051	120051	113172	23	113758	50010	30020	10000	10000	60020	20106	10000	120035	120051	1	1	50021	10	9	10	40010	10000	10000	0	10	10000	0	1	10000	4	0	10000	1	1	0	0	3140	5	107	3	3	119669	40002	13	13	12	10000	40010	120036	120036	120036	120055	120110
50024	120051	899	0	0	0	0	0	0	120039	119512	109449	0	25	60013	40010	10001	10000	30010	10000	10000	1079517	5735455	6132757	0	120011	0	120035	120054	113172	3	113674	50010	30020	10000	10000	60020	20000	10000	120054	120035	1	1	50021	10	9	10	40010	10000	10000	0	10	10000	0	0	10000	0	0	10000	1	0	0	1	3140	3	107	6	5	119666	40000	0	10	9	10000	40010	120052	120052	120036	120052	120052
50024	120035	899	0	0	0	1	0	0	120036	119492	109464	0	25	60013	40012	10001	10000	30010	10000	10000	1079557	5736236	6133662	0	120011	0	120093	120035	113172	3	113674	50010	30020	10000	10000	60020	20000	10000	120035	120051	1	1	50021	10	9	10	40010	10000	10000	0	10	10000	0	1	10000	0	0	10000	1	1	0	0	3140	4	107	4	4	119666	40000	0	0	12	10000	40010	120055	120052	120036	120036	120055
50024	120054	899	0	0	0	6	0	0	120036	119509	109464	0	25	60013	40010	10004	10000	30010	10000	10000	1079584	5736236	6138103	0	120027	0	120051	120051	113169	3	113690	50010	30020	10000	10000	60020	20000	10000	120051	120035	1	1	50021	10	9	10	40010	10000	10000	0	10	10000	0	0	10000	0	0	10000	1	1	0	0	3140	5	107	5	4	119669	40002	0	10	0	10000	40010	120036	120052	120052	120055	120052
50024	120051	899	0	0	0	0	1	0	120039	119492	109464	0	135	60013	40012	10001	10000	30010	10000	10000	1079517	5736236	6133662	1	120011	0	120051	120051	113153	3	113690	50010	30020	10000	10000	60020	20000	10000	120051	120051	1	1	50021	10	9	10	40010	10000	10000	0	10	10000	0	0	10000	0	0	10000	0	1	0	0	3140	5	107	5	5	119666	40000	0	10	9	10000	40010	120036	120052	120052	120102	120055
50024	120054	899	0	1	0	0	0	0	120020	119492	109464	0	25	60013	40010	10001	10000	30010	10000	10000	1079584	5736380	6133662	1	120027	0	120035	120051	113169	3	113690	50010	30020	10000	10000	60020	20000	10000	120051	120036	1	1	50021	10	9	10	40010	10000	10000	0	10	10000	0	0	10000	0	0	10000	0	1	0	0	3140	5	107	6	4	119669	40000	0	13	9	10000	40010	120055	120036	120036	120036	120052
50024	120035	900	0	0	0	1	0	0	120036	119509	109464	0	25	60013	40010	10001	10000	30010	10000	10000	1079517	5736236	6134645	0	120011	0	120035	120051	113169	3	113674	50010	30020	10000	10000	60020	20000	10000	120051	120051	1	1	50021	10	9	10	40010	10000	10000	0	10	10000	0	1	10000	0	0	10000	1	0	0	0	3140	3	107	4	4	119666	40002	10	10	9	10000	40010	120055	120055	120055	120055	120055
50024	120051	899	0	0	0	1	0	0	120036	119512	109527	0	25	60010	40010	10001	10000	30160	10000	10000	1079557	5736236	6133662	0	120011	0	120054	120051	113172	3	113690	50010	30020	10000	10000	60020	20000	10000	120035	120051	1	1	50021	10	9	10	40010	10000	10000	0	10	10000	0	1	10000	0	0	10000	1	1	0	0	3140	7	107	4	4	119650	40002	0	0	9	10000	40010	120036	120052	120036	120052	120052
50024	120054	899	0	0	0	1	0	0	120020	119512	109449	0	41	60013	40012	10001	10000	30010	10000	10000	1079517	5737090	6136144	0	120011	0	120057	120054	113172	3	113693	50010	30020	10000	10000	60020	20000	10000	120035	120051	1	1	50021	10	9	10	40010	10000	10000	0	10	10000	0	1	10000	0	0	10000	0	0	0	0	3140	6	107	7	4	119666	40000	13	0	0	10000	40010	120036	120055	120055	120036	120036

Test 3: Latency 1->3 roundtrip

Chain cycles: 3

Code:

  ldr d0, [x6, w7, sxtw]
  fmov x0, d0
  eor x8, x8, x0
  eor x8, x8, x0
  add x7, x7, x8

Initialization

  mov x7, #4
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 9.0051

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	l2 tlb miss data (0b)	0e	0f	18	19	1e	1f	22	23	24	3a	3f	4d	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	69	6b	6d	6e	map stall dispatch (70)	int prf full (71)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	af	b5	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
50205	120053	899	1	1	1	0	0	0	0	2	0	1	0	0	1	120038	119512	109455	25	60106	40104	10002	10000	30100	10000	10000	1079044	5735750	6136419	120031	0	120053	120053	113137	0	3	113670	50100	30200	10000	10000	60200	20000	10000	120053	120053	1	1	50201	100	99	100	40100	10000	10000	1	100	10001	2	1	10002	1	0	191	10000	1	1	1	1	1	0	0	3211	2	107	3	3	119660	40004	6	6	5	10000	40100	120100	120080	120057	120054	120054
50204	120053	900	1	1	1	0	0	0	0	1	0	1	0	0	1	120038	119512	109466	25	60106	40104	10001	10000	30100	10000	10000	1079026	5736332	6136419	120017	0	120053	120053	113148	0	3	113670	50100	30200	10000	10000	60200	20000	10000	120053	120053	1	1	50201	100	99	100	40100	10000	10000	0	100	10001	2	0	10001	0	0	1	10000	0	1	1	1	1	0	0	3211	2	135	3	2	119660	40004	6	6	5	10000	40100	120054	120054	120042	120054	120054
50204	120053	899	1	1	1	0	0	0	0	2	0	0	0	0	0	120038	119512	109466	25	60106	40104	10001	10000	30100	10000	10000	1079026	5736332	6136419	120029	0	120053	120053	113148	0	3	113670	50100	30200	10000	10000	60200	20000	10000	120053	120053	1	1	50201	100	99	100	40100	10000	10000	1	100	10003	2	0	10001	0	1	1	10000	1	1	1	1	0	0	0	3211	2	135	2	3	119660	40004	0	6	5	10000	40100	120054	120054	120054	120054	120054
50204	120053	899	1	1	1	0	0	0	0	2	0	0	0	0	1	120038	119512	109466	25	60106	40104	10001	10000	30100	10000	10000	1079026	5736332	6133458	120017	0	120053	120053	113137	0	3	113630	50100	30200	10000	10000	60200	20000	10000	120053	120054	1	1	50201	100	99	100	40100	10000	10000	0	100	10001	2	1	10001	0	0	1	10000	1	1	1	1	1	0	0	3211	3	107	3	4	119660	40004	6	6	5	10000	40100	120054	120054	120054	120054	120058
50204	120054	900	1	1	1	0	0	0	0	2	0	1	0	0	1	120038	119512	109455	25	60106	40104	10002	10000	30100	10000	10000	1079026	5736332	6133458	120029	0	120053	120053	113148	0	3	113670	50100	30200	10000	10000	60200	20000	10000	120053	120053	1	1	50201	100	99	100	40100	10000	10000	1	100	10003	2	1	10002	0	1	7	10000	1	1	1	1	0	0	0	3211	3	107	3	3	119660	40004	6	6	5	10000	40100	120054	120054	120054	120054	120054
50204	120053	899	1	1	1	0	0	0	0	2	0	0	0	0	1	120038	119512	109455	25	60106	40104	10001	10000	30100	10000	10000	1079026	5735750	6136419	120029	0	120053	120053	113148	0	3	113670	50100	30200	10000	10000	60200	20000	10000	120053	120041	1	1	50201	100	99	100	40100	10000	10000	0	100	10002	4	0	10002	0	1	1	10000	0	1	1	1	1	0	0	3211	3	107	2	3	119660	40002	6	6	5	10000	40100	120054	120042	120054	120054	120054
50204	120053	899	1	1	1	0	0	0	0	1	0	0	0	0	0	120026	119513	109466	25	60103	40104	10002	10000	30100	10000	10000	1079026	5736332	6136419	120029	0	120053	120041	113148	0	3	113670	50100	30200	10000	10000	60200	20000	10000	120053	120053	1	1	50201	100	99	100	40100	10000	10000	1	100	10002	1	1	10002	0	1	1	10000	1	1	1	1	0	0	1	3211	4	135	3	3	119660	40004	6	6	5	10000	40100	120054	120042	120054	120054	120042
50204	120041	900	1	1	0	0	0	0	0	3170	2024	1	0	0	1	122357	120632	110253	684	60379	40325	10054	10054	33954	11372	10299	1133951	5794200	6193789	121943	0	122382	122413	113935	0	153	114649	56154	34181	11335	11415	68290	22790	11354	122455	120055	6	1	50201	100	99	100	40100	10000	10000	1	100	10016	1	1	10038	0	0	95781	10034	1	1	1	1	3	0	0	4119	4	370	5	4	121676	40224	6	6	5	10000	40100	122471	122932	123236	123743	120054
50204	120053	940	1	2	2	0	0	23	18	4094	2728	1	0	0	2	123107	121747	111014	1269	60629	40504	10084	10088	36085	12365	11822	1163662	5817482	6211466	122976	0	123002	123471	113226	0	360	114614	56938	34912	11553	11825	67940	23316	11729	123586	123377	32	1	50201	100	99	100	40100	10000	10000	1	100	10003	2	1	10002	0	2	1	10000	1	0	1	0	0	0	0	3211	3	107	3	3	119658	40000	10	10	0	10000	40100	120052	120052	120052	120036	120052
50204	120051	899	0	0	0	0	0	0	0	1	0	0	0	1	0	120020	119493	109464	25	60103	40102	10001	10000	30100	10000	10000	1079008	5736236	6136317	120011	0	120051	120035	113146	0	3	113658	50100	30200	10000	10000	60200	20000	10000	120051	120051	1	1	50201	100	99	100	40100	10000	10000	1	100	10000	0	0	10000	0	0	0	10000	0	0	1	0	0	0	0	3211	3	107	2	3	119646	40002	10	10	9	10000	40100	120052	120052	120052	120052	120036

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 9.0050

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	l2 tlb miss data (0b)	0e	0f	1e	22	24	3a	3f	4d	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	int prf full (71)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	af	b5	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	branch mispred nonspec (cb)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
50025	120056	899	0	0	0	0	0	1	1	0	0	120035	119510	109461	25	60013	40017	10001	10000	30010	10000	10000	1079638	5737783	6133764	1	120017	120053	120089	113171	0	3	113692	50010	30020	10000	10000	60020	20000	10000	120053	120053	1	1	50021	10	9	10	40010	10000	10000	0	10	10001	3	1	10002	0	1	1	10000	1	1	1	1	0	0	3140	7	107	1	1	119656	40002	6	6	8	10000	40010	120054	120054	120073	120073	120042
50024	120041	899	1	0	0	0	0	2	0	0	1	120041	119543	109469	25	60016	40012	10002	10002	30010	10000	10000	1079602	5736332	6133764	0	120032	120056	120041	113159	0	3	113695	50010	30020	10000	10000	60020	20000	10000	120056	120053	1	1	50021	10	9	10	40010	10000	10000	0	10	10001	2	1	10002	0	1	1	10000	1	1	1	1	0	0	3140	1	107	1	1	119671	40004	9	0	0	10000	40010	120054	120088	120096	120061	120057
50024	120056	899	1	1	1	0	0	7	0	0	0	120041	119691	109467	40	60016	40014	10002	10000	30576	10000	10000	1079602	5735750	6133764	1	120032	120063	120056	113174	0	3	113692	50010	30020	10000	10000	60020	20000	10000	120061	120041	1	1	50021	10	9	10	40010	10000	10000	0	10	10001	2	0	10002	0	0	1	10000	1	1	0	1	1	0	3140	1	107	1	1	119671	40004	6	6	8	10000	40010	120054	120122	120061	120057	120042
50024	120056	899	1	0	1	0	0	1	0	0	0	120041	119537	109455	25	60016	40014	10001	10000	30010	10000	10000	1079602	5736476	6133216	1	120017	120041	120057	113174	0	3	113680	50010	30020	10000	10000	60020	20000	10000	120056	120053	1	1	50021	10	9	10	40010	10000	10000	0	10	10001	2	1	10002	0	0	1	10000	1	1	0	1	0	0	3140	1	107	1	1	119671	40004	0	6	8	10000	40010	120042	120095	120079	120058	120054
50024	120041	899	1	0	0	0	0	1	1	0	0	120041	119511	109515	25	60013	40014	10001	10000	30010	10000	10000	1079602	5736476	6133216	1	120032	120041	120056	113174	0	3	113680	50010	30020	10000	10000	60020	20000	10000	120041	120041	1	1	50021	10	9	10	40010	10000	10000	0	10	10001	4	1	10003	0	1	1	10000	1	1	0	1	0	0	3140	1	107	1	1	119656	40002	6	0	5	10000	40010	120054	120116	120058	120054	120042
50024	120056	899	1	0	1	0	0	2	0	0	0	120026	119526	109466	25	60016	40012	10002	10000	30010	10062	10000	1079463	5736332	6133216	1	120029	120041	120041	113174	0	3	113696	50010	30020	10066	10000	60020	20000	10000	120063	120053	1	1	50021	10	9	10	40010	10000	10000	0	10	10001	3	1	10001	0	0	1	10000	1	1	1	1	0	0	3140	1	107	2	1	119656	40004	9	9	8	10000	40010	120057	120120	120060	120054	120057
50024	120056	899	1	0	0	0	0	2	0	0	0	120086	119502	109455	25	60016	40014	10002	10000	30010	10000	10000	1079463	5736476	6133917	1	120017	120056	120053	113174	0	3	113695	50010	30020	10000	10000	60020	20000	10000	120053	120053	1	1	50021	10	9	10	40010	10000	10000	0	10	10001	3	1	10002	0	1	4	10000	0	1	1	1	1	0	3140	1	107	1	1	119668	40004	0	9	8	10000	40010	120105	120079	120058	120057	120088
50024	120056	899	1	1	0	0	0	0	0	0	0	120020	119510	109449	25	60048	40018	10000	10000	30010	10000	10000	1079548	5735455	6132757	1	120107	120035	120047	113153	0	3	113686	50010	30020	10000	10000	60020	20000	10000	120035	120047	1	1	50021	10	9	10	40010	10000	10000	0	10	10000	0	1	10000	0	0	0	10000	0	0	1	0	0	0	3140	1	107	1	1	119665	40002	0	6	8	10000	40010	120051	120101	120055	120051	120051
50024	120035	899	0	0	0	0	0	0	0	0	0	120037	119509	109463	25	60010	40010	10001	10000	30010	10000	10000	1079517	5735455	6132757	1	120023	120050	120035	113168	0	3	113674	50010	30020	10000	10000	60020	20000	10000	120050	120047	1	1	50021	10	9	10	40010	10000	10000	0	10	10000	0	1	10000	0	0	0	10000	1	0	0	0	0	0	3140	1	107	1	1	119650	40002	9	9	8	10000	40010	120048	120107	120049	120048	120051
50024	120050	899	0	0	0	0	0	1	0	0	0	120035	119492	109463	25	60010	40012	10001	10000	30010	10000	10000	1079548	5735455	6132757	1	120026	120035	120050	113168	0	3	113689	50010	30020	10000	10000	60020	20000	10000	120047	120047	1	1	50021	10	9	10	40010	10000	10000	1	10	10000	0	1	10000	1	0	0	10000	1	0	0	0	0	0	3140	1	107	1	1	119650	40000	0	6	5	10000	40010	120048	120117	120036	120048	120051

Test 4: throughput

Count: 8

Code:

  ldr d0, [x6, w7, sxtw]
  ldr d0, [x6, w7, sxtw]
  ldr d0, [x6, w7, sxtw]
  ldr d0, [x6, w7, sxtw]
  ldr d0, [x6, w7, sxtw]
  ldr d0, [x6, w7, sxtw]
  ldr d0, [x6, w7, sxtw]
  ldr d0, [x6, w7, sxtw]

Initialization

  mov x7, 8

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.3340

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	09	l2 tlb miss data (0b)	0e	0f	1e	22	23	3a	3f	43	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	69	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	a5	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
80205	26723	200	1	0	0	0	45	0	0	1	26710	0	12	12	15	25	80100	100	80000	100	80014	500	1168332	1	26697	0	26707	26727	16635	6	16679	80116	200	80024	200	160048	26722	26707	1	1	80201	100	99	100	100	80000	80000	1	100	80000	0	0	0	80039	0	0	35	80035	6	1	0	39	1	1	1	5118	0	16	0	0	26724	0	0	2	80000	100	26727	26713	26723	26728	26728
80204	26725	200	0	0	0	0	41	1	0	2	26850	2	12	12	12	25	80100	100	80000	100	80016	500	1167431	1	26704	0	26707	26722	16650	6	16659	80114	200	80024	200	160048	26722	26722	1	1	80201	100	99	100	100	80000	80000	0	100	80000	0	39	0	80000	0	0	38	80039	6	1	0	0	1	1	1	5118	0	16	0	0	26704	10	0	4	80000	100	26723	26708	26728	26728	26708
80204	26727	200	0	0	1	0	0	0	0	2	26697	2	0	12	4	25	80100	100	80000	100	80014	565	1173997	1	26697	0	26722	26707	16650	6	16662	80115	200	80024	200	160048	26707	26722	1	1	80201	100	99	100	100	80000	80000	0	100	80000	0	39	0	80039	0	0	39	80039	0	1	35	39	1	1	1	5118	0	16	0	0	26727	0	6	2	80000	100	26730	26728	26728	26712	26727
80204	26727	200	0	0	0	0	45	1	0	0	26716	2	12	0	16	25	80100	100	80000	100	80014	500	1165953	1	26682	0	26727	26727	16635	6	16659	80115	200	80024	200	160048	26707	26722	1	1	80201	100	99	100	100	80000	80000	0	100	80000	0	39	0	80039	0	0	0	80000	6	1	0	39	1	1	1	5118	0	16	0	0	26724	10	6	2	80000	100	26728	26728	26728	26708	26728
80204	26722	200	0	0	0	0	0	1	0	1	26837	2	0	0	12	49	80100	100	80000	100	80014	500	1177260	1	26682	0	26727	26707	16655	6	16679	80114	200	80024	200	160048	26708	26789	1	1	80201	100	99	100	100	80000	80000	0	100	80000	0	39	0	80039	0	0	0	80039	0	0	35	43	1	1	1	5118	0	16	0	0	26704	10	6	0	80000	100	26728	26708	26708	26728	26723
80204	26727	200	0	0	0	0	45	0	0	2	26725	2	12	0	0	25	80100	100	80000	100	80015	500	1166596	1	26682	0	26727	26727	16655	6	16679	80115	200	80024	200	160048	26727	26722	1	1	80201	100	99	100	100	80000	80000	0	100	80000	0	43	0	80039	0	0	0	80039	6	0	35	43	1	1	1	5118	0	16	0	0	26724	10	6	4	80000	100	26728	26728	26728	26728	26708
80204	26722	200	0	0	0	0	45	1	0	1	26724	2	18	0	16	25	80100	100	80000	100	80015	500	1167875	1	26702	0	26727	26727	16635	6	16679	80115	200	80024	200	160048	26727	26722	1	1	80201	100	99	100	100	80000	80000	0	100	80000	0	39	0	80039	0	0	35	80035	0	1	35	43	1	1	1	5118	0	16	0	0	26724	6	10	4	80000	100	26723	26708	26708	26708	26708
80204	26747	200	0	0	0	0	45	1	0	2	26720	2	12	18	0	25	80100	100	80000	100	80014	500	1177116	1	26702	0	26788	26783	16655	6	16659	80115	200	80024	200	160048	26763	26722	1	1	80201	100	99	100	100	80000	80000	0	100	80000	0	0	0	80039	0	0	39	80000	6	1	35	0	1	1	1	5118	0	16	0	0	26704	10	6	0	80000	100	26728	26728	26723	26723	26723
80204	26707	200	0	0	0	0	45	0	0	1	26697	2	18	12	16	25	80100	100	80000	100	80015	500	1177116	1	26702	0	26727	26722	16655	6	16674	80114	200	80024	200	160048	26722	26722	1	1	80201	100	99	100	100	80000	80000	0	100	80000	0	39	0	80039	0	0	35	80039	6	1	39	39	1	1	1	5118	0	16	0	0	26724	10	6	4	80000	100	26708	26728	26728	26728	26708
80204	26707	200	0	0	0	0	45	0	0	0	26713	0	12	0	12	25	80100	100	80000	100	80015	500	1167875	1	26682	0	26727	26727	16635	6	16659	80114	200	80024	200	160048	26707	26722	1	1	80201	100	99	100	100	80000	80000	0	100	80000	0	0	0	80039	0	0	35	80039	6	0	0	43	1	1	1	5118	0	16	0	0	26706	10	6	0	80000	100	26723	26708	26728	26771	26727

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.3341

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	09	0e	0f	1e	22	23	3a	3f	43	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	5f	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	cd	cf	d0	d2	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
80025	26727	200	0	0	1	45	1	0	1	26700	2	12	0	16	25	80010	10	80000	10	80000	50	1166750	0	0	26683	26727	26727	16672	3	16707	80010	20	80000	20	160000	26728	26708	1	1	80021	10	9	10	10	80000	80000	1	10	80000	0	0	80039	0	0	80039	0	0	39	43	0	5020	0	0	4	16	4	3	26724	10	10	4	80000	10	26728	26729	26729	26729	26728
80024	26727	200	0	0	0	45	0	0	1	26715	2	0	0	0	25	80010	10	80000	10	80000	50	1166896	0	1	26702	26731	26708	16672	3	16708	80010	20	80000	20	160000	26708	26727	1	1	80021	10	9	10	10	80000	80000	0	10	80000	0	43	80000	0	39	80039	6	1	0	43	0	5020	0	0	4	16	4	3	26724	10	10	0	80000	10	26729	26729	26728	26709	26728
80024	26708	200	0	0	0	45	1	0	1	26712	0	12	1	16	25	80010	10	80000	10	80000	50	1166886	0	0	26702	26728	26731	16672	3	16708	80010	20	80000	20	160000	26712	26727	1	1	80021	10	9	10	10	80000	80000	0	10	80000	0	43	80039	0	39	80000	6	1	0	43	0	5020	0	0	4	16	4	3	26725	0	0	4	80000	10	26728	26728	26728	26709	26729
80024	26708	200	0	0	0	45	1	0	0	26710	2	12	12	0	25	80010	10	80000	10	80000	50	1166750	0	0	26703	26708	26727	16652	3	16688	80010	20	80000	20	160000	26727	26727	1	1	80021	10	9	10	10	80000	80000	0	10	80000	0	0	80039	0	39	80039	6	1	39	43	0	5020	0	0	4	16	4	4	26724	10	0	4	80000	10	26728	26709	26729	26729	26728
80024	26727	200	0	0	0	0	1	0	1	26720	2	12	12	19	25	80010	10	80000	10	80000	50	1165883	0	1	26683	26708	26728	16652	3	16707	80010	20	80000	20	160000	26708	26711	1	1	80021	10	9	10	10	80000	80000	0	10	80000	0	43	80039	0	946	80169	0	1	0	43	0	5020	0	0	4	16	4	4	26724	0	10	4	80000	10	26709	26728	26709	26728	26729
80024	26708	201	0	0	0	0	1	0	0	26693	0	12	0	0	25	80010	10	80000	10	80000	50	1166886	0	1	26703	26708	26727	16672	3	16688	80010	20	80000	20	160000	26728	26708	1	1	80021	10	9	10	10	80000	80000	0	10	80000	0	43	80039	0	39	80000	0	0	39	43	0	5020	0	0	3	16	4	3	26705	0	10	4	80000	10	26729	26729	26728	26728	26729
80024	26728	200	0	0	0	45	1	0	1	26712	2	0	12	0	25	80010	10	80000	10	80000	50	1166750	0	0	26683	26728	26708	16676	3	16707	80010	20	80000	20	160000	26728	26727	1	1	80021	10	9	10	10	80000	80000	0	10	80000	0	0	80039	0	0	80039	0	0	0	43	0	5020	0	0	4	16	4	4	26728	10	0	4	80000	10	26728	26728	26729	26709	26709
80024	26727	200	1	0	0	0	0	0	0	26713	0	12	12	0	25	80010	10	80000	10	80000	50	1166896	0	1	26703	26727	26727	16672	3	16707	80010	20	80000	20	160000	26727	26708	1	1	80021	10	9	10	10	80000	80000	0	10	80000	0	43	80039	0	39	80000	6	1	39	43	0	5020	0	0	4	16	4	4	26725	10	10	4	80000	10	26728	26728	26728	26728	26729
80024	26731	200	0	0	0	0	1	0	0	26712	0	0	0	0	25	80010	10	80000	10	80000	50	1168843	0	0	26703	26727	26727	16672	3	16707	80010	20	80000	20	160000	26708	26727	1	1	80021	10	9	10	10	80000	80000	0	10	80000	0	43	80039	0	0	80039	0	1	0	0	0	5020	0	0	4	16	4	3	26705	10	0	4	80000	10	26709	26709	26729	26728	26728
80024	26727	200	0	1	1	45	1	0	0	26718	0	12	12	16	25	80010	10	80000	10	80000	50	1168843	0	1	26683	26728	26728	16672	3	16711	80010	20	80000	20	160000	26728	26708	1	1	80021	10	9	10	10	80000	80000	1	10	80000	0	43	80039	0	39	80039	6	0	39	43	0	5020	0	0	4	16	4	3	26725	10	10	4	80000	10	26728	26729	26709	26729	26728

LDR (register, sxtw, D)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->2 roundtrip

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: Latency 1->3 roundtrip

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 4: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations