Firestorm: LDR (register, sxtw, Q) measurements

Code:

  ldr q0, [x6, w7, sxtw]

Initialization

  mov x7, #4
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 1.000

SIMD/FP unit issues: 0.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	0e	0f	1e	22	3a	3f	43	46	49	4f	51	schedule uop (52)	schedule ldst uop (55)	dispatch ldst uop (58)	simd uops in schedulers (5a)	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map ldst uop (7d)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst simd load (98)	inst ldst (9b)	9d	l1d tlb access (a0)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	ea	eb	ec	? ldst retires (ed)	f5	f6	f7	f8	fd
1005	394	3	0	0	45	0	1	379	2	12	12	16	25	1000	1000	1000	15037	369	394	394	217	3	256	1000	1000	2000	394	394	1	1	1001	1000	1000	0	1000	43	1039	0	39	1039	6	1	39	43	73	4	16	2	2	391	10	14	4	1000	395	395	398	399	395
1004	398	2	0	0	45	0	1	379	2	12	12	16	25	1000	1000	1000	15018	369	394	394	216	3	252	1000	1000	2000	394	394	1	1	1001	1000	1000	0	1000	43	1039	0	39	1039	6	1	39	43	73	2	16	2	2	391	10	10	4	1000	395	395	395	400	395
1004	394	3	0	0	45	1	1	379	2	12	12	16	25	1000	1000	1000	14989	369	395	394	217	3	252	1000	1000	2000	394	394	1	1	1001	1000	1000	1	1000	43	1039	0	39	1039	6	1	39	44	73	2	16	2	2	391	10	10	4	1000	395	395	400	401	395
1004	394	3	0	0	45	1	1	379	2	12	12	13	25	1000	1000	1000	14989	369	394	394	217	3	252	1000	1000	2000	394	394	1	1	1001	1000	1000	0	1000	43	1039	0	39	1039	6	1	39	43	73	2	16	2	2	391	10	10	4	1000	395	395	395	404	395
1004	394	2	0	0	44	0	1	379	2	12	12	16	25	1000	1000	1000	15037	373	394	394	217	3	252	1000	1000	2000	394	394	1	1	1001	1000	1000	0	1000	43	1039	0	39	1039	6	1	39	43	73	2	16	2	2	391	10	10	4	1000	395	395	395	426	399
1004	394	3	0	0	45	0	1	379	2	12	1	16	25	1000	1000	1000	14989	369	394	394	216	3	256	1000	1000	2000	394	394	1	1	1001	1000	1000	0	1000	43	1039	0	39	1039	6	1	39	43	73	2	16	2	2	391	10	10	4	1000	395	395	395	395	395
1004	394	3	0	0	45	1	1	379	2	12	12	16	25	1000	1000	1000	14989	369	394	394	217	3	252	1000	1000	2000	394	401	1	1	1001	1000	1000	0	1000	43	1039	0	39	1039	6	1	39	43	73	2	16	2	2	391	10	10	7	1000	395	395	398	396	395
1004	394	3	0	0	45	1	1	379	2	12	12	16	25	1000	1000	1000	14989	369	394	394	217	3	252	1000	1000	2000	394	394	1	1	1001	1000	1000	0	1000	43	1039	0	39	1039	6	1	39	43	73	2	16	2	2	391	10	10	4	1000	395	395	395	400	395
1004	394	3	0	0	45	0	1	379	2	12	12	19	25	1000	1000	1000	15018	369	394	394	217	3	252	1000	1000	2000	398	394	1	1	1001	1000	1000	0	1000	43	1039	0	39	1039	6	1	39	43	73	2	16	2	2	391	10	10	4	1000	395	396	399	395	395
1004	394	3	0	0	45	1	1	379	2	12	12	16	25	1000	1000	1000	14989	369	394	394	217	3	256	1000	1000	2000	394	394	1	1	1001	1000	1000	0	1000	43	1039	0	39	1039	6	1	39	43	73	2	16	2	2	391	10	10	4	1000	395	395	396	396	395

Test 2: Latency 1->2 roundtrip

Chain cycles: 3

Code:

  ldr q0, [x6, w7, sxtw]
  fmov x0, d0
  eor x8, x8, x0
  eor x8, x8, x0
  add x6, x6, x8

Initialization

  mov x7, #4
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 9.0054

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	09	0e	0f	18	19	1e	1f	22	23	3a	3f	4d	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	b5	l1d cache miss ld nonspec (bf)	cf	d0	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
50205	120051	899	3	0	0	0	0	52	0	0	0	0	120036	119510	109467	25	60103	40100	10000	10000	30100	10000	10000	1079008	5736236	6136317	0	120011	120035	120035	113232	3	113658	50100	30200	10000	10000	60200	20000	10000	120051	120035	1	1	50201	100	99	100	40100	10000	10000	0	100	10000	0	1	10000	0	0	0	0	10000	1	1	3210	0	2	107	1	1	119661	40002	0	0	9	10000	40100	120036	120036	120055	120055	120036
50204	120051	899	0	0	0	0	0	229	0	0	0	0	120020	119513	109467	25	60103	40102	10001	10000	30100	10000	10000	1079008	5736236	6136317	0	120027	120054	120054	113204	3	113671	50100	30200	10000	10000	60200	20000	10000	120035	120035	1	1	50202	100	99	100	40100	10000	10000	0	100	10000	0	1	10000	0	6	0	0	10000	1	0	3210	0	1	107	1	1	119661	40002	0	0	0	10000	40100	120059	120036	120055	120055	120055
50204	120035	899	0	0	0	0	0	1	0	0	0	0	120020	119493	109449	25	60100	40102	10001	10000	30100	10000	10000	1078862	5735455	6136317	0	120027	120035	120051	113195	3	113668	50100	30200	10000	10000	60582	20000	10000	120051	120051	1	1	50201	100	99	100	40100	10000	10000	0	100	10000	0	0	10000	0	0	0	0	10000	0	1	3210	0	1	107	1	1	119658	40000	13	0	9	10000	40100	120055	120055	120055	120055	120055
50204	120054	899	0	0	0	0	0	283	0	1	0	0	120039	119510	109464	25	60103	40100	10001	10000	30100	10000	10000	1079035	5735455	6134461	0	120027	120054	120035	113179	3	113671	50100	30200	10000	10000	60200	20000	10000	120051	120080	1	1	50201	100	99	100	40100	10000	10000	0	100	10000	0	1	10000	0	0	0	0	10000	1	0	3210	0	1	107	1	1	119661	40002	0	13	12	10000	40100	120055	120055	120052	120055	120036
50204	120054	899	0	0	0	0	0	6	0	1	0	0	120039	119510	109464	25	60100	40100	10001	10000	30100	10000	10000	1078862	5736332	6134461	1	120027	120051	120035	113194	3	113658	50100	30200	10000	10000	60574	20000	10000	120035	120054	1	1	50201	100	99	100	40100	10000	10000	1	100	10000	0	0	10000	0	0	0	0	10000	1	1	3210	0	1	101	2	1	119661	40002	13	0	12	10000	40100	120055	120055	120052	120055	120055
50204	120035	899	0	0	0	0	0	1	0	1	0	0	120044	119513	109449	25	60100	40100	10001	10000	30100	10000	10000	1079035	5735455	6136317	1	120011	120054	120054	113195	3	113671	50100	30200	10000	10000	60200	20000	10000	120035	120035	1	1	50201	100	99	100	40100	10000	10000	0	100	10000	0	0	10000	0	0	0	0	10000	0	1	3210	0	1	107	1	1	119646	40002	0	10	9	10000	40100	120055	120055	120055	120052	120055
50204	120054	899	0	0	0	0	0	4	0	0	0	0	120039	119513	109467	25	60100	40100	10001	10000	30100	10000	10000	1079008	5736380	6136317	0	120030	120054	120054	113206	3	113671	50100	30200	10000	10000	60200	20000	10000	120035	120051	1	1	50201	100	99	100	40100	10000	10000	0	100	10000	0	1	10000	0	0	0	0	10000	1	0	3210	0	1	107	1	1	119658	40002	13	10	0	10000	40100	120052	120055	120055	120052	120055
50204	120054	899	0	0	0	0	0	0	0	0	0	0	120039	119563	109449	25	60103	40102	10001	10000	30100	10000	10000	1078862	5736236	6134461	0	120027	120035	120035	113181	3	113900	50100	30200	10000	10000	60200	20000	10000	120036	120051	1	1	50201	100	99	100	40100	10000	10000	1	100	10000	0	1	10000	0	1	0	0	10000	1	0	3210	0	1	101	1	1	119646	40000	0	0	0	10000	40100	120052	120036	120052	120052	120055
50204	120054	899	0	0	0	0	0	516	0	0	0	0	120036	119513	109467	25	60103	40100	10000	10000	30100	10000	10000	1079008	5735455	6136317	0	120030	120054	120098	113161	3	113668	50100	30200	10000	10000	60200	20000	10000	120054	120051	1	1	50201	100	99	100	40100	10000	10000	0	100	10000	0	1	10000	0	0	0	0	10000	1	0	3210	0	1	107	1	1	119658	40002	0	13	12	10000	40100	120055	120055	120052	120036	120055
50204	120035	899	0	0	0	0	0	0	0	1	0	0	120039	119510	109449	25	60103	40100	10001	10000	30100	10000	10000	1079035	5735455	6134461	0	120071	120054	120035	113200	3	113668	50100	30200	10000	10000	60200	20000	10000	120054	120035	1	1	50201	100	99	100	40100	10000	10000	0	100	10000	0	1	10000	0	0	0	0	10000	1	1	3210	0	1	107	1	1	119661	40002	13	0	0	10000	40100	120055	120055	120036	120055	120055

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 9.0056

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	09	l2 tlb miss data (0b)	0e	0f	18	19	1e	1f	22	23	3a	3f	43	49	4d	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	69	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	b5	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	branch cond mispred nonspec (c5)	cf	d2	d5	map dispatch bubble (d6)	da	db	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
50025	120053	899	1	0	1	1	1	0	0	0	2	0	1	0	0	120038	0	0	119511	109455	25	60016	40014	10002	10000	30010	10000	10000	1079575	5735750	6133216	0	120029	0	120056	120056	113171	3	113695	50010	30020	10000	10000	60020	20000	10000	120056	120053	1	1	50021	10	9	10	40010	10000	10000	1	10	10002	1	0	10003	0	0	1	4	10000	1	1	1	1	1	0	3140	0	3	119	0	2	1	1	119671	40004	6	6	5	10000	40010	120057	120057	120581	120042	120584
50024	120056	899	1	1	1	1	0	0	0	0	11	0	0	0	0	120041	0	0	119511	109469	25	60016	40014	10001	10000	30010	10000	10000	1079463	5736476	6133764	0	120032	0	120053	120060	113174	3	113680	50010	30020	10000	10000	60020	20000	10000	120053	120053	1	1	50021	10	9	10	40010	10000	10000	0	10	10001	1	1	10003	0	0	1	1	10000	1	1	1	1	2	0	3140	0	1	107	0	0	2	1	119671	40004	9	6	0	10000	40010	120057	120042	120057	120057	120057
50024	120056	899	1	2	0	1	0	0	0	0	2	0	0	0	0	120026	0	0	119514	109469	25	60016	40012	10002	10000	30010	10052	10000	1079575	5736476	6133917	1	120017	0	120041	120041	113171	3	113680	50010	30020	10000	10000	60020	20000	10000	120056	120056	1	1	50021	10	9	10	40010	10000	10000	0	10	10005	3	2	10002	0	0	0	2	10001	0	2	0	1	1	0	3140	0	1	107	0	0	1	1	119668	40004	6	0	0	10000	40010	120042	120042	120057	120042	120057
50024	120041	900	1	1	0	0	0	0	0	0	2	0	0	0	0	120026	0	0	119513	109455	25	60016	40014	10001	10000	30010	10000	10000	1079602	5736476	6133764	1	120017	0	120083	120060	113174	3	113695	50010	30180	10000	10000	60020	20000	10000	120056	120061	1	1	50021	10	9	10	40010	10000	10000	0	10	10002	2	0	10002	0	0	0	1	10000	1	1	1	1	0	0	3140	0	1	107	0	0	1	1	119672	40002	6	0	5	10000	40010	120042	120057	120057	120054	120042
50024	120056	899	1	1	1	0	0	0	0	0	2	0	0	0	0	120041	0	0	119514	109469	25	60016	40012	10002	10000	30010	10000	10050	1079602	5736476	6133764	1	120059	0	120056	120056	113159	3	113695	50010	30020	10000	10000	60020	20106	10000	120041	120053	1	1	50021	10	9	10	40010	10000	10000	0	10	10002	2	1	10002	1	1	1	1	10000	1	1	1	1	1	0	3140	0	1	97	0	1	1	1	119671	40002	9	9	8	10000	40010	120057	120054	120057	120057	120042
50024	120060	900	1	1	1	1	0	0	0	0	7	0	0	0	0	120026	0	0	119514	109469	25	60016	40012	10002	10000	30010	10000	10000	1079602	5735750	6133917	1	120017	0	120056	120056	113174	3	113695	50010	30020	10000	10000	60020	20000	10000	120056	120053	1	1	50021	10	9	10	40010	10000	10000	0	10	10001	2	1	10001	0	0	0	1	10000	1	1	0	1	1	0	3146	0	1	107	0	1	1	1	119671	40004	0	0	0	10000	40010	120057	120158	120057	120057	120054
50024	120053	899	1	0	0	1	0	0	0	0	2	0	0	0	0	120041	0	0	119514	109469	25	60016	40014	10001	10000	30010	10000	10000	1079620	5736476	6135232	1	120029	0	120056	120053	113159	3	113695	50010	30020	10000	10000	60336	20000	10000	120061	120041	1	1	50021	10	9	10	40010	10000	10000	0	10	10003	2	1	10001	0	0	1	1	10000	1	1	0	1	1	0	3140	0	1	107	0	0	1	1	119676	40006	6	0	5	10000	40010	120050	120050	120050	120062	120062
50024	120061	899	1	1	1	0	0	0	0	0	3	0	0	0	0	120041	0	0	119514	109455	52	60013	40012	10002	10000	30010	10000	10000	1079463	5735750	6133917	1	120032	0	120056	120041	113174	3	113680	50010	30020	10000	10000	60020	20000	10000	120056	120054	1	1	50021	10	9	10	40010	10000	10000	0	10	10001	2	1	10001	0	0	0	1	10000	1	1	1	1	0	0	3140	0	1	107	0	0	1	1	119656	40004	9	0	8	10000	40010	120057	120057	120057	120245	120057
50024	120048	899	1	0	1	1	0	0	0	1	317	280	1	0	0	120334	0	0	119514	109455	25	60016	40014	10001	10000	30010	10000	10000	1079463	5737213	6133216	0	120032	0	120056	120053	113174	3	113695	50010	30020	10000	10000	60020	20000	10000	120058	120140	1	1	50021	10	9	10	40010	10000	10000	0	10	10003	2	1	10002	0	0	1	1	10000	1	1	0	1	0	0	3140	0	1	107	0	0	1	2	119668	40004	0	0	8	10000	40010	120042	120458	120054	120057	120143
50024	120056	899	1	0	1	1	0	0	3	1	2	0	0	0	0	120038	0	0	119511	109469	25	60016	40014	10002	10002	30012	10000	10050	1079629	5736332	6133917	1	120032	0	120056	120133	113161	3	113743	50010	30020	10000	10053	60020	20000	10000	120056	120053	1	1	50021	10	9	10	40010	10000	10000	0	10	10003	3	1	10001	0	0	2	10	10000	1	1	1	1	1	0	3140	0	1	107	0	0	2	2	119656	40004	6	9	8	10000	40010	120057	120057	120042	120057	120057

Test 3: Latency 1->3 roundtrip

Chain cycles: 3

Code:

  ldr q0, [x6, w7, sxtw]
  fmov x0, d0
  eor x8, x8, x0
  eor x8, x8, x0
  add x7, x7, x8

Initialization

  mov x7, #4
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 9.0050

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	l2 tlb miss data (0b)	0e	0f	18	19	1e	1f	22	23	24	3a	3f	4d	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	69	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	ac	af	b5	l1d cache miss ld nonspec (bf)	c2	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
50205	120047	899	0	0	0	1	0	2	0	0	0	0	0	0	120035	119509	109463	25	60103	40102	10001	10002	30100	10000	10000	1078999	5736188	6133818	0	120023	0	120050	120050	113158	3	113636	50100	30200	10000	10000	60200	20000	10000	120050	120047	1	1	50201	100	99	100	40100	10000	10000	0	100	10000	0	1	10000	0	0	10000	1	1	0	0	0	3210	1	107	1	1	119657	40000	9	6	8	10000	40100	120036	120036	120051	120051	120051
50204	120097	899	0	0	0	0	0	0	1	0	1	0	0	0	120035	119519	109449	25	60103	40102	10001	10002	30100	10000	10000	1078862	5737471	6133818	0	120026	3	120070	120055	113235	3	113636	50100	30200	10000	10000	60200	20128	10000	120047	120035	1	1	50201	100	99	100	40100	10000	10000	0	100	10000	0	1	10000	0	0	10000	0	1	0	0	0	3210	1	135	1	1	119660	40002	9	6	5	10000	40100	120051	120036	120051	120048	120048
50204	120050	899	0	0	0	0	0	0	1	0	0	0	0	0	120035	119493	109463	25	60100	40102	10001	10000	30248	10000	10000	1079008	5738320	6137794	0	120030	0	120035	120047	113145	3	113658	50100	30200	10000	10000	60200	20000	10000	120050	120047	1	1	50201	100	99	100	40100	10000	10000	0	100	10000	0	1	10000	0	0	10000	0	1	0	0	0	3210	1	101	1	1	119657	40000	9	6	8	10000	40100	120051	120036	120048	120051	120051
50204	120035	900	0	0	1	0	0	0	1	0	0	0	0	0	120020	119514	109461	25	60103	40100	10001	10000	30100	10000	10000	1078999	5736188	6133818	0	120058	0	120035	120050	113145	3	113786	50100	30200	10000	10000	60200	20000	10000	120050	120035	2	1	50201	100	99	100	40100	10000	10000	0	100	10000	0	1	10000	0	1	10000	0	1	0	0	0	3210	1	101	2	1	119657	40002	9	9	5	10000	40100	120036	120051	120051	120051	120051
50204	120035	899	0	0	0	0	0	0	0	0	0	0	0	0	120035	119493	109449	25	60103	40104	10000	10000	30100	10000	10000	1078999	5735455	6136166	0	120034	0	120047	120050	113145	3	113667	50100	30200	10000	10000	60200	20000	10000	120035	120047	1	1	50201	100	99	100	40100	10000	10000	0	100	10000	0	1	10000	0	0	10000	1	1	0	0	0	3210	1	135	1	1	119660	40000	0	6	5	10000	40100	120051	120036	120051	120036	120048
50204	120050	899	0	0	0	0	0	0	1	0	0	0	0	0	120035	119519	109468	25	60103	40104	10001	10000	30100	10000	10000	1078999	5735455	6133818	0	120027	0	120035	120047	113145	3	113658	50100	30200	10000	10000	60200	20000	10000	120050	120035	1	1	50201	100	99	100	40100	10000	10000	0	100	10000	0	1	10001	0	0	10000	1	1	0	0	0	3210	1	107	1	1	119646	40002	0	6	8	10000	40100	120048	120048	120036	120048	120051
50204	120050	899	0	0	0	0	0	0	1	0	0	0	0	0	120020	119509	109449	25	60100	40102	10001	10000	30100	10000	10000	1078862	5735455	6133818	0	120024	0	120050	120050	113141	3	113658	50100	30200	10000	10000	60200	20000	10000	120047	120035	1	1	50201	100	99	100	40100	10000	10000	0	100	10000	0	1	10000	0	0	10000	0	1	2	0	0	3879	1	312	3	2	121545	40220	0	8	8	10000	40100	122405	122337	122472	122379	122509
50204	122445	916	1	0	1	0	0	6	1	88	0	0	0	1	122342	120847	110181	778	60443	40308	10055	10056	33381	11424	11328	1140453	5786100	6200137	0	122134	0	123021	123735	114087	393	115595	59135	35398	11981	11997	70577	23956	11621	123533	123621	41	1	50201	100	99	100	40100	10000	10000	0	100	10010	2	1	10024	0	88823	10039	1	1	0	0	0	4186	1	399	4	2	122692	40285	9	0	8	10000	40100	120036	120052	120048	120036	123101
50204	120875	955	0	1	0	0	31	37	447	0	0	0	0	0	120032	119495	109463	25	60131	40100	10001	10000	30100	10000	10000	1078999	5736188	6134461	1	120023	0	120050	120035	113145	3	113667	50100	30200	10000	10000	60200	20000	10000	120047	120047	1	1	50201	100	99	100	40100	10000	10000	0	100	10000	0	1	10000	0	0	10000	1	1	0	0	0	3210	2	101	1	1	119657	40002	0	6	0	10000	40100	120051	120051	120051	120048	120051
50204	120035	899	0	0	0	0	0	0	7	0	0	0	1	0	120035	119513	109463	25	60103	40102	10001	10000	30100	10000	10000	1078862	5735455	6133818	1	120017	0	120035	120050	113145	3	113636	50100	30200	10000	10000	60200	20000	10000	120050	120035	1	1	50201	100	99	100	40100	10000	10000	0	100	10000	0	1	10000	0	0	10000	0	1	0	0	0	3210	1	107	2	1	119663	40002	9	6	0	10000	40100	120048	120048	120048	120051	120036

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 9.0051

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	0f	18	19	1e	22	24	3f	4d	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	5f	60	69	6d	6e	map stall dispatch (70)	int prf full (71)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d cache miss ld (a3)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	b5	l1d cache miss ld nonspec (bf)	branch mispred nonspec (cb)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
50025	120051	899	0	0	0	0	25	1	0	120039	119509	109464	25	60013	40012	10001	10000	30010	10000	10000	1079557	5736332	6134962	0	1	120027	120075	120052	113169	0	3	113694	50010	30020	10000	10000	60020	20000	10000	120051	120051	1	1	50021	10	9	10	40010	10000	10000	1	10	10005	0	10002	2	4	2	3658	10002	1	1	0	3140	1	107	1	1	119666	40002	10	10	0	10000	40010	120054	120052	120052	120052	120052
50024	120051	899	0	0	0	0	13	1	0	120038	119509	109449	25	60013	40012	10001	10000	30010	10062	10000	1079557	5736236	6133662	0	1	120027	120074	120058	113227	0	3	113679	50010	30020	10000	10000	60020	20000	10000	120051	120051	1	1	50021	10	9	10	40010	10000	10000	0	10	10000	1	10000	0	0	0	0	10000	1	1	0	3140	1	107	1	1	119666	40002	10	10	9	10000	40010	120052	120036	120036	120052	120052
50024	120051	900	0	0	0	0	1	1	0	120036	119509	109449	25	60024	40012	10001	10000	30010	10000	10000	1079557	5736236	6133662	0	1	120027	120090	120052	113169	0	3	113690	50010	30020	10000	10000	60020	20000	10000	120051	120051	1	1	50021	10	9	10	40010	10000	10000	0	10	10000	1	10000	0	0	0	0	10000	1	0	0	3140	1	107	1	1	119666	40000	10	10	0	10000	40010	120052	120052	120052	120052	120052
50024	120051	899	0	0	0	0	1	1	0	120037	119509	109464	25	60013	40012	10001	10000	30010	10000	10000	1079517	5736236	6133662	0	0	120027	120078	120052	113169	0	3	113690	50010	30020	10000	10000	60020	20000	10000	120051	120051	1	1	50021	10	9	10	40010	10000	10000	0	10	10000	1	10000	0	0	0	0	10000	1	1	0	3140	1	107	1	1	119666	40002	10	10	9	10000	40010	120052	120052	120052	120036	120036
50024	120051	899	0	0	4	0	133	0	0	120036	119509	109449	25	60013	40012	10001	10000	30010	10000	10000	1079557	5736236	6133662	0	0	120027	120051	120051	113169	0	3	113690	50010	30020	10000	10000	60020	20000	10000	120051	120051	1	1	50021	10	9	10	40010	10000	10000	0	10	10000	1	10000	0	0	0	0	10000	0	1	0	3140	1	107	1	1	119666	40002	10	10	9	10000	40010	120052	120055	120052	120052	120036
50024	120051	899	0	0	0	0	1	1	0	120020	119509	109464	25	60013	40012	10001	10000	30010	10000	10000	1079557	5736236	6133662	0	0	120027	120052	120051	113169	0	3	113674	50010	30020	10000	10000	60020	20000	10000	120035	120035	1	1	50021	10	9	10	40010	10000	10000	0	10	10000	1	10000	0	0	0	0	10000	1	1	0	3140	1	107	1	1	119666	40000	10	10	9	10000	40010	120052	120052	120052	120052	120052
50024	120051	899	0	0	0	0	0	1	0	120071	119509	109464	25	60013	40012	10001	10000	30010	10000	10000	1079557	5736236	6132757	0	0	120027	120072	120054	113169	0	3	113674	50010	30020	10000	10000	60020	20000	10000	120051	120051	1	1	50021	10	9	10	40010	10000	10000	0	10	10000	1	10000	0	0	0	0	10000	0	1	0	3140	1	107	1	1	119666	40000	10	10	9	10000	40010	120052	120052	120052	120052	120052
50024	120051	899	0	0	0	0	1	1	0	120036	119509	109449	25	60013	40012	10001	10000	30010	10000	10000	1079557	5735455	6132757	1	1	120011	120062	120051	113169	0	3	113690	50010	30020	10000	10000	60020	20000	10000	120051	120051	1	1	50021	10	9	10	40010	10000	10000	0	10	10000	1	10000	0	0	0	0	10000	1	1	0	3140	1	107	1	1	119666	40002	10	10	9	10000	40010	120052	120052	120052	120052	120055
50024	120051	899	0	0	0	0	0	1	0	120020	119509	109464	25	60013	40012	10000	10000	30010	10000	10000	1082249	5735455	6133662	0	0	120027	120053	120051	113169	0	3	113690	50010	30020	10000	10000	60020	20000	10000	120051	120051	1	1	50021	10	9	10	40010	10000	10000	0	10	10000	1	10000	0	0	0	0	10000	1	0	0	3140	1	107	1	1	119666	40000	10	0	9	10000	40010	120052	120052	120052	120052	120052
50024	120051	900	0	0	4	0	0	1	0	120036	119492	109464	25	60010	40012	10001	10000	30010	10000	10000	1079517	5736236	6133662	0	0	120027	120054	120051	113169	0	3	113690	50010	30020	10000	10000	60020	20000	10000	120051	120051	1	1	50021	10	9	10	40010	10000	10000	0	10	10000	1	10000	0	0	0	0	10000	1	0	1	3140	1	107	1	1	119666	40000	10	10	9	10000	40010	120052	120036	120052	120052	120052

Test 4: throughput

Count: 8

Code:

  ldr q0, [x6, w7, sxtw]
  ldr q0, [x6, w7, sxtw]
  ldr q0, [x6, w7, sxtw]
  ldr q0, [x6, w7, sxtw]
  ldr q0, [x6, w7, sxtw]
  ldr q0, [x6, w7, sxtw]
  ldr q0, [x6, w7, sxtw]
  ldr q0, [x6, w7, sxtw]

Initialization

  mov x7, 8

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.3341

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	09	0e	0f	1e	22	24	3a	3f	43	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
80205	26722	202	0	0	0	0	45	0	0	0	26692	3	12	0	16	25	80100	100	80000	100	80023	500	1167280	0	26682	26727	26734	16655	6	16679	80115	200	80024	200	160048	26707	26722	1	1	80201	100	99	100	100	80000	80000	0	100	80000	0	80039	0	0	39	80039	6	1	35	43	1	1	1	5118	0	16	26724	0	9	6	0	80000	100	26728	26728	26733	26728	26728
80204	26730	200	0	0	0	0	41	1	0	2	26692	2	12	12	16	25	80100	100	80000	100	80016	500	1171522	1	26702	26722	26722	16655	6	16679	80115	200	80024	200	160048	26727	26707	1	1	80201	100	99	100	100	80000	80000	0	100	80000	39	80039	0	0	39	80000	6	1	0	43	1	1	1	5118	0	16	26719	0	0	6	2	80000	100	26728	26708	26723	26728	26723
80204	26707	200	0	0	0	0	41	1	0	2	26707	2	0	18	84	25	80100	100	80000	100	80016	500	1167153	1	26702	26707	26727	16635	6	16679	80293	200	80024	200	160048	26707	26722	1	1	80201	100	99	100	100	80000	80000	0	100	80000	0	80000	0	0	0	80035	6	1	39	43	1	1	1	5118	0	16	26719	0	6	6	4	80000	100	26728	26728	26728	26708	26728
80204	26727	200	0	0	0	0	45	0	0	0	26712	0	18	12	0	25	80100	100	80000	100	80016	500	1169098	0	26702	26727	26707	16655	6	16674	80115	200	80024	200	160048	26727	26722	1	1	80201	100	99	100	100	80000	80000	0	100	80000	39	80039	0	0	0	80039	6	1	35	43	1	1	1	5118	0	16	26724	0	10	6	2	80000	100	26728	26723	26723	26728	26723
80204	26727	201	0	0	0	0	0	0	0	2	26712	2	12	12	12	25	80100	100	80000	100	80014	500	1169269	0	26682	26727	26727	16655	6	16679	80115	200	80024	200	160048	26727	26707	1	1	80201	100	99	100	100	80000	80000	0	100	80000	39	80000	0	0	0	80039	6	0	39	0	1	1	1	5118	0	16	26724	0	10	10	0	80000	100	26708	26728	26728	26708	26723
80204	26707	200	0	0	0	0	45	0	0	2	26712	0	18	12	16	25	80100	100	80000	100	80015	500	1170579	0	26702	26707	26707	16824	6	16679	80114	200	80024	200	160048	26730	26722	1	1	80201	100	99	100	100	80000	80000	0	100	80000	39	80039	0	0	39	80051	6	1	35	0	1	1	1	5118	0	16	26815	0	10	10	4	80000	100	26728	26708	26723	26712	26728
80204	26727	200	0	0	0	0	45	0	0	0	26712	2	12	0	16	25	80100	100	80000	100	80016	500	1173093	0	26702	26707	26722	16655	6	16674	80114	200	80024	200	160048	26707	26722	1	1	80201	100	99	100	100	80000	80000	0	100	80000	39	80000	0	0	35	80039	6	1	35	39	1	1	1	5118	0	16	26719	0	0	0	4	80000	100	26723	26728	26723	26728	26723
80204	26727	200	0	0	0	0	45	0	0	0	26712	2	12	0	0	25	80100	100	80000	100	80015	500	1166596	1	26702	26727	26707	16635	14	16661	80115	200	80024	200	160048	26727	26707	1	1	80201	100	99	100	100	80000	80000	0	100	80000	0	80000	0	0	39	80035	6	0	35	0	1	1	1	5118	0	16	26724	0	0	6	0	80000	100	26708	26723	26723	26728	26723
80204	26727	201	0	0	0	0	41	0	0	2	26707	0	0	0	0	25	80100	100	80000	100	80016	500	1173225	1	26702	26727	26727	16655	6	16679	80115	200	80024	200	160048	26727	26722	1	1	80201	100	99	100	100	80000	80000	0	100	80000	39	80000	0	0	39	80039	0	1	35	0	1	1	1	5118	0	16	26724	0	0	0	0	80000	100	26723	26728	26728	26728	26728
80204	26707	200	0	0	0	0	45	0	0	0	26712	0	12	12	0	25	80100	100	80000	100	80015	500	1172155	0	26702	26727	26727	16635	6	16659	80116	200	80024	200	160048	26727	26722	1	1	80201	100	99	100	100	80000	80000	1	100	80000	0	80039	0	0	36	80039	6	0	35	43	1	1	1	5118	0	16	26704	0	10	10	4	80000	100	26728	26708	26728	26728	26728

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.3340

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	0e	0f	18	19	1e	22	24	3a	3f	43	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst ldst (9b)	9f	l1d tlb access (a0)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
80025	26722	200	0	0	0	0	41	1	0	1	26707	2	18	18	14	25	80010	10	80000	10	80000	50	1167605	1	26772	26722	26736	16667	3	16702	80010	20	80000	20	160000	26722	26722	1	1	80021	10	9	10	10	80000	80000	10	80000	39	80035	0	35	80035	6	1	35	39	5020	6	16	1	1	26719	6	0	2	80000	10	26723	26723	26723	26709	26723
80024	26722	200	0	0	0	0	62	1	0	1	26707	2	18	18	12	25	80010	10	80000	10	80000	50	1167605	0	26697	26929	26739	16669	3	16702	80010	20	80000	20	160000	26722	26722	1	1	80021	10	9	10	10	80000	80000	10	80000	39	80035	0	35	80035	6	1	35	39	5020	1	16	3	1	26719	6	0	2	80000	10	26723	26709	26723	26723	26723
80024	26722	200	0	0	0	0	41	1	0	1	26707	0	18	18	11	25	80010	10	80000	10	80000	50	1167366	1	26796	26731	26722	16667	3	16688	80010	20	80000	20	160000	26722	26708	1	1	80021	10	9	10	10	80000	80000	10	80000	39	80035	1	35	80035	6	1	35	0	5020	1	16	1	1	26719	6	6	2	80000	10	26723	26723	26723	26723	26723
80024	26722	201	0	0	0	0	41	0	0	1	26699	2	0	0	11	25	80010	10	80000	10	80000	50	1166750	0	26802	26730	26722	16667	3	16702	80010	20	80000	20	160000	26722	26722	1	1	80021	10	9	10	10	80000	80000	10	80000	39	80165	3	35	80035	6	0	35	39	5020	1	16	1	1	26720	6	6	0	80000	10	26723	26723	26723	26723	26723
80024	26722	200	0	0	0	0	41	0	0	0	26707	2	0	18	12	25	80010	10	80000	10	80000	50	1167605	0	26798	26727	26728	16652	3	16702	80010	20	80000	20	160000	26708	26722	1	1	80021	10	9	10	10	80000	80000	10	80000	39	80036	0	35	80035	6	1	35	39	5020	1	16	1	1	26719	6	0	2	80000	10	26723	26723	26709	26723	26723
80024	26722	200	0	0	0	0	41	0	0	0	26707	2	18	18	12	25	80010	10	80000	10	80000	50	1166750	1	26799	26727	26722	16667	3	16702	80010	20	80000	20	160000	26722	26722	1	1	80021	10	9	10	10	80000	80000	10	80000	39	80035	0	35	80035	6	1	35	0	5020	1	16	1	1	26719	6	6	2	80000	10	26723	26723	26723	26709	26723
80024	26722	200	0	0	1	0	41	0	0	1	26707	2	0	18	12	25	80010	10	80000	10	80000	50	1172240	1	26793	26728	26739	16667	3	16702	80010	20	80000	20	160000	26722	26708	1	1	80021	10	9	10	10	80000	80000	10	80000	39	80035	0	35	80035	0	1	35	39	5020	2	16	1	2	26719	6	6	0	80000	10	26709	26723	26723	26723	26709
80024	26708	200	0	0	0	0	41	1	0	1	26707	2	18	18	12	25	80010	10	80000	10	80000	50	1167605	1	26821	26739	26722	16667	3	16688	80010	20	80000	20	160000	26722	26722	1	1	80021	10	9	10	10	80000	80000	10	80000	39	80035	0	35	80035	6	1	35	0	5020	1	16	1	1	26705	6	6	0	80000	10	26723	26723	26709	26723	26723
80024	26722	200	0	0	0	0	41	1	0	1	26693	0	18	0	12	25	80010	10	80000	10	80000	50	1167605	0	26889	26730	26722	16667	3	16702	80010	20	80000	20	160000	26722	26722	1	1	80021	10	9	10	10	80000	80000	10	80000	39	80035	0	35	80000	6	1	0	0	5020	1	16	1	1	26719	6	6	2	80000	10	26709	26726	26723	26723	26726
80024	26722	200	0	0	0	0	0	1	0	1	26707	2	18	18	41	25	80010	10	80000	10	80000	50	1167605	1	26815	26730	26727	16667	3	16702	80010	20	80000	20	160000	26722	26722	1	1	80021	10	9	10	10	80000	80000	10	80000	39	80035	0	38	80000	6	1	35	39	5020	1	16	1	1	26719	6	6	2	80000	10	26723	26709	26723	26723	26709

LDR (register, sxtw, Q)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->2 roundtrip

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: Latency 1->3 roundtrip

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 4: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations