Firestorm: LDR (register, sxtw, S) measurements

Code:

  ldr s0, [x6, w7, sxtw]

Initialization

  mov x7, #4
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 1.000

SIMD/FP unit issues: 0.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	l2 tlb miss data (0b)	0e	0f	1e	22	3a	3f	43	46	49	4f	51	schedule uop (52)	schedule ldst uop (55)	dispatch ldst uop (58)	simd uops in schedulers (5a)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map ldst uop (7d)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	92	inst simd load (98)	inst ldst (9b)	9d	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	ea	eb	ec	? ldst retires (ed)	f5	f6	f7	f8	fd
1005	403	3	1	0	0	0	0	67	1	2	388	3	7	7	20	25	1000	1000	1000	15480	0	378	403	403	225	3	260	1000	1000	2000	403	403	1	1	1001	0	1000	1000	1	1020	19	43	1059	0	0	2	64	1040	6	1	59	43	19	0	73	2	16	2	2	402	13	13	5	1000	404	406	403	403	404
1004	403	3	1	1	1	0	0	67	0	2	388	2	7	7	19	25	1000	1000	1000	15555	1	378	403	402	225	3	261	1000	1000	2000	402	403	1	1	1001	0	1000	1000	0	1019	20	43	1059	1	0	2	63	1039	6	1	59	43	19	1	73	2	16	2	2	403	13	13	5	1000	404	404	406	403	404
1004	403	3	1	1	1	0	0	66	0	3	388	3	9	7	19	25	1000	1000	1000	15547	1	377	403	403	226	3	260	1000	1000	2000	403	403	1	1	1001	0	1000	1000	0	1021	22	43	1059	0	0	1	61	1040	6	1	59	43	19	2	73	2	16	2	2	400	13	13	5	1000	404	403	404	404	404
1004	403	3	1	0	1	0	0	66	0	2	388	3	7	7	19	25	1000	1000	1000	15555	0	377	403	403	226	3	260	1000	1000	2000	403	403	1	1	1001	1	1000	1000	0	1019	20	43	1060	1	0	1	63	1040	6	1	58	43	19	1	73	2	16	2	2	400	13	13	5	1000	405	404	403	404	404
1004	403	3	1	0	0	0	0	67	0	2	388	3	7	7	20	25	1000	1000	1000	15480	0	378	403	403	226	3	260	1000	1000	2000	403	403	1	1	1001	0	1000	1000	0	1020	19	43	1059	0	0	1	60	1040	6	1	60	43	19	0	73	2	16	2	2	404	13	13	5	1000	403	404	404	404	404
1004	403	3	1	0	1	0	0	66	0	3	388	3	7	7	19	25	1000	1000	1000	15526	0	378	402	403	225	3	261	1000	1000	2000	403	403	1	1	1001	0	1000	1000	0	1020	20	43	1058	1	0	1	61	1040	6	1	58	43	19	2	73	2	16	2	2	399	13	13	5	1000	403	405	404	404	404
1004	402	3	1	0	0	0	0	66	0	2	387	3	7	7	20	25	1000	1000	1000	15567	0	379	403	402	225	3	261	1000	1000	2000	402	403	1	1	1001	1	1000	1000	0	1020	20	43	1058	1	0	0	61	1040	6	1	59	43	19	0	73	2	16	2	2	399	13	13	5	1000	403	404	404	404	404
1004	403	3	1	1	1	0	0	66	0	3	388	3	7	7	19	25	1000	1000	1000	15555	0	377	403	403	226	3	260	1000	1000	2000	403	403	1	1	1001	1	1000	1000	0	1020	20	43	1059	0	0	0	61	1039	6	1	59	43	19	1	73	2	16	2	2	400	13	13	5	1000	404	403	403	404	404
1004	403	2	1	0	1	0	0	66	1	3	388	3	7	7	20	25	1000	1000	1000	15555	0	378	402	403	225	3	261	1000	1000	2000	403	403	1	1	1001	0	1000	1000	1	1019	20	43	1058	0	0	0	61	1040	6	1	58	43	19	1	73	2	16	2	2	400	13	13	5	1000	403	404	404	404	404
1004	403	3	1	0	0	0	0	66	0	2	388	3	7	7	20	25	1000	1000	1000	15508	0	378	403	403	225	3	261	1000	1000	2000	403	403	1	1	1001	0	1000	1000	0	1019	20	43	1059	0	0	1	60	1039	6	1	59	43	19	0	73	2	16	2	2	411	13	13	5	1000	403	404	404	404	404

Test 2: Latency 1->2 roundtrip

Chain cycles: 3

Code:

  ldr s0, [x6, w7, sxtw]
  fmov x0, d0
  eor x8, x8, x0
  eor x8, x8, x0
  add x6, x6, x8

Initialization

  mov x7, #4
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 9.0051

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	l2 tlb miss data (0b)	0e	0f	19	1e	22	3f	4d	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	69	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	ac	af	b5	l1d cache miss ld nonspec (bf)	c2	branch cond mispred nonspec (c5)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
50205	120051	899	0	0	1	0	0	1	0	120039	119513	109467	25	60103	40100	10001	10000	30100	10000	10000	1079035	5736380	6136317	1	120059	0	120054	120054	113141	3	113671	50100	30200	10000	10000	60200	20128	10000	120056	120052	1	1	50201	100	99	100	40100	10000	10000	1	100	10000	0	1	10000	0	0	10000	1	1	0	0	0	3210	3	107	1	1	119658	40002	13	0	9	10000	40100	120052	120052	120036	120052	120052
50204	120035	899	0	0	0	0	0	1	0	120036	119493	109467	25	60103	40102	10001	10000	30100	10000	10000	1078862	5736380	6136317	1	120030	0	120051	120051	113149	3	113658	50100	30200	10000	10000	60200	20000	10000	120035	120051	1	1	50201	100	99	100	40100	10000	10000	0	100	10000	0	1	10000	1	24	10000	1	0	0	0	0	3210	1	101	1	1	119661	40002	13	10	12	10000	40100	120052	120036	120036	120036	120055
50204	120035	899	0	0	0	0	0	10	0	120020	119513	109467	25	60103	40102	10001	10000	30100	10000	10000	1079035	5735455	6136657	1	120011	3	120054	120054	113141	3	113658	50100	30200	10000	10000	60200	20000	10000	120051	120035	1	1	50201	100	99	100	40100	10000	10000	1	100	10000	0	1	10000	0	0	10000	0	0	0	0	0	3210	1	107	1	2	119661	40002	13	13	12	10000	40100	120036	120055	120055	120052	120052
50204	120051	899	0	0	0	0	0	1	1	120039	119493	109464	25	60100	40102	10001	10000	30100	10000	10000	1079008	5736236	6136368	1	120030	0	120035	120054	113149	3	113671	50100	30200	10000	10000	60200	20000	10000	120054	120051	1	1	50201	100	99	100	40100	10000	10000	0	100	10000	0	1	10000	0	0	10000	1	0	0	0	0	3210	1	107	1	1	119647	40000	0	13	12	10000	40100	120102	120093	120055	120052	120055
50204	120054	899	0	0	0	0	0	1	1	120036	119513	109467	25	60103	40102	10001	10000	30100	10000	10000	1079008	5736236	6136317	1	120027	0	120054	120054	113149	3	113671	50100	30200	10000	10000	60200	20000	10000	120054	120054	1	1	50201	100	99	100	40100	10000	10000	0	100	10000	0	1	10000	0	0	10000	0	1	0	0	0	3210	1	107	1	1	119658	40002	13	13	9	10000	40100	120055	120052	120052	120052	120052
50204	120051	899	0	0	0	0	0	1	1	120036	119506	109464	25	60103	40100	10001	10000	30100	10000	10000	1078862	5736380	6136317	1	120027	0	120054	120051	113141	3	113671	50100	30200	10000	10000	60200	20000	10000	120054	120051	1	1	50201	100	99	100	40100	10000	10000	0	100	10000	0	1	10000	0	0	10000	0	1	0	0	0	3210	1	107	1	1	119658	40002	13	13	0	10000	40100	120036	120055	120052	120055	120052
50204	120035	900	0	0	1	1	0	0	1	120039	119510	109464	25	60103	40102	10000	10000	30100	10000	10000	1079008	5736236	6136317	1	120011	0	120035	120051	113146	3	113668	50100	30200	10000	10000	60200	20000	10000	120051	120051	1	1	50201	100	99	100	40100	10000	10000	0	100	10000	0	1	10000	0	0	10000	1	0	0	0	0	3210	1	107	1	1	119661	40002	13	0	12	10000	40100	120036	120052	120055	120055	120055
50204	120054	899	0	0	0	0	0	6	1	120036	119513	109467	25	60103	40102	10001	10000	30100	10000	10000	1079035	5736380	6134461	1	120030	0	120051	120051	113149	3	113671	50100	30200	10000	10000	60200	20000	10000	120051	120051	1	1	50201	100	99	100	40100	10000	10000	0	100	10000	0	1	10000	1	0	10000	1	1	0	0	0	3210	1	101	1	1	119661	40002	13	10	9	10000	40100	120057	120131	120052	120132	120148
50204	120139	899	1	1	0	0	0	1	1	120039	119510	109464	25	60100	40102	10001	10000	30100	10000	10000	1079035	5736380	6134461	1	120014	0	120035	120051	113149	3	113658	50100	30200	10000	10000	60200	20000	10000	120035	120095	1	1	50201	100	99	100	40100	10000	10000	0	100	10000	0	1	10000	0	6	10000	1	1	0	0	0	3237	2	126	1	1	119832	40000	10	0	9	10000	40100	120052	120037	120055	120036	120036
50204	120051	899	0	0	0	0	0	12	0	120039	119510	109467	25	60103	40100	10001	10000	30100	10000	10000	1079035	5736524	6136470	1	120027	0	120054	120056	113146	3	113660	50100	30200	10000	10000	60592	20000	10000	120035	120035	1	1	50201	100	99	100	40100	10000	10000	0	100	10000	0	1	10000	0	0	10001	0	0	0	0	0	3210	1	107	1	1	119658	40002	0	13	0	10000	40100	120055	120055	120052	120036	120055

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 9.0057

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	09	l2 tlb miss data (0b)	0e	0f	18	1e	22	23	3a	3f	4d	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	69	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	af	b5	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	branch cond mispred nonspec (c5)	cf	d5	map dispatch bubble (d6)	d9	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
50025	120057	899	1	1	0	0	0	1	0	1	0	0	0	120045	119499	109473	25	60013	40012	10002	10000	30010	10000	10000	1079463	5736524	6133968	0	120033	0	120041	120057	113178	3	113703	50010	30020	10000	10000	60020	20000	10000	120060	120041	1	1	50021	10	9	10	40010	10000	10000	0	10	10001	2	1	10003	0	1	1	10000	1	1	1	1	1	0	3140	3	107	0	4	2	119672	40004	13	10	12	10000	40010	120058	120061	120058	120058	120058
50024	120057	899	1	0	0	0	0	0	0	2	1	0	0	120045	119518	109470	25	60016	40014	10001	10000	30010	10000	10000	1079638	5736668	6133216	0	120036	0	120057	120060	113178	3	113696	50010	30020	10000	10000	60020	20000	10000	120060	120057	1	1	50021	10	9	10	40010	10000	10000	1	10	10002	2	0	10001	0	1	1	10001	1	1	1	1	1	0	3140	2	107	0	4	2	119675	40002	13	13	12	10000	40010	120061	120042	120042	120061	120042
50024	120060	899	1	1	1	0	0	0	0	2	1	0	0	120036	119518	109455	25	60016	40014	10001	10000	30010	10000	10000	1079638	5736668	6133968	0	120017	0	120060	120060	113159	3	113699	50010	30020	10000	10000	60020	20000	10000	120058	120057	1	1	50021	10	9	10	40010	10000	10000	0	10	10002	2	1	10001	0	1	1	10000	1	1	1	1	2	0	3140	2	107	0	4	2	119675	40004	13	10	12	10000	40010	120061	120061	120058	120061	120045
50024	120060	899	1	1	0	0	0	0	1	2	0	0	1	120045	119518	109774	25	60016	40029	10002	10000	30010	10000	10000	1079638	5736668	6133968	0	120036	0	120060	120060	113178	3	113699	50010	30020	10000	10000	60020	20000	10000	120041	120041	1	1	50021	10	9	10	40010	10000	10000	0	10	10003	1	1	10002	0	3	1	10000	1	1	1	1	1	1	3140	2	107	0	4	3	119672	40004	10	0	12	10000	40010	120042	120061	120042	120061	120061
50024	120041	899	1	0	1	0	0	0	0	2	0	0	1	120042	119518	109455	25	60013	40012	10002	10000	30010	10000	10000	1079463	5736524	6133968	0	120036	0	120060	120060	113178	3	113699	50010	30020	10000	10000	60020	20000	10000	120041	120057	1	1	50021	10	9	10	40010	10000	10000	0	10	10001	2	0	10002	0	0	1	10000	1	1	0	1	1	0	3140	2	107	0	6	6	119672	40004	13	13	9	10000	40010	120058	120061	120042	120058	120061
50024	120057	899	1	0	0	1	0	0	0	2	0	0	0	120045	119515	109470	25	60016	40014	10002	10000	30010	10000	10000	1079611	5736923	6137757	1	120017	0	120060	120060	113159	3	113699	50010	30020	10000	10000	60020	20000	10000	120059	120084	1	1	50021	10	9	10	40010	10000	10000	0	10	10003	3	0	10002	1	0	1	10000	1	1	1	1	0	1	3140	2	107	1	2	2	119675	40004	0	13	0	10000	40010	120042	120042	120061	120042	120042
50024	120057	900	1	0	1	0	0	0	0	7	0	0	0	120026	119518	109473	25	60016	40012	10001	10000	30010	10000	10000	1079638	5735750	6133216	0	120033	0	120060	120057	113159	3	113699	50010	30020	10000	10000	60020	20000	10000	120057	120057	1	1	50021	10	9	10	40010	10000	10000	0	10	10003	2	0	10002	0	1	1	10000	1	1	1	1	0	0	3140	2	107	0	2	2	119675	40006	13	10	12	10000	40010	120061	120061	120061	120042	120042
50024	120113	900	1	0	0	1	0	0	0	11	0	0	0	120045	119518	109473	25	60013	40012	10002	10000	30010	10000	10000	1079453	5736663	6134858	0	120017	0	120060	120041	113178	3	113699	50012	30020	10000	10000	60020	20000	10000	120060	120057	1	1	50021	10	9	10	40010	10000	10000	0	10	10002	2	1	10002	0	0	1	10000	0	1	1	1	1	0	3140	2	107	0	2	2	119675	40004	13	13	12	10000	40010	120061	120042	120042	120061	120042
50024	120060	899	1	1	1	1	0	0	0	2	0	0	0	120045	119518	109473	25	60016	40014	10001	10000	30012	10000	10000	1079630	5736663	6133979	0	120036	0	120060	120041	113159	3	113699	50010	30020	10000	10000	60020	20000	10000	120041	120041	1	1	50021	10	9	10	40010	10000	10000	0	10	10001	1	1	10002	0	0	1	10000	1	1	1	1	0	0	3140	3	107	0	2	2	119656	40004	0	13	12	10000	40010	120061	120061	120061	120061	120061
50024	120060	899	1	1	1	1	0	0	0	1	1	0	0	120026	119518	109470	25	60016	40014	10001	10000	30010	10000	10000	1079611	5736524	6133216	0	120017	0	120060	120057	113178	3	113696	50012	30020	10000	10000	60020	20000	10000	120060	120057	1	1	50021	10	9	10	40010	10000	10000	0	10	10002	1	1	10003	0	0	1	10000	1	1	1	1	2	0	3140	6	107	0	2	2	119672	40002	13	0	9	10000	40010	120058	120061	120061	120061	120058

Test 3: Latency 1->3 roundtrip

Chain cycles: 3

Code:

  ldr s0, [x6, w7, sxtw]
  fmov x0, d0
  eor x8, x8, x0
  eor x8, x8, x0
  add x7, x7, x8

Initialization

  mov x7, #4
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 9.0050

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	l2 tlb miss data (0b)	0e	0f	18	19	1e	1f	22	24	3a	3f	4d	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	af	b5	l1d cache miss ld nonspec (bf)	c2	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
50205	120047	899	0	0	1	0	0	0	433	0	1	0	0	120032	119519	109449	25	60103	40100	10001	10000	30100	10000	10000	1078999	5736188	6133818	1	120011	120050	120047	113145	3	113667	50100	30200	10000	10000	60200	20000	10000	120050	120047	1	1	50201	100	99	100	40100	10000	10000	1	100	10000	0	1	10000	0	0	0	10000	1	1	0	0	0	3210	1	101	1	1	119657	40002	9	0	5	10000	40100	120051	120051	120051	120054	120036
50204	120050	899	0	0	0	0	0	0	120	0	0	0	0	120035	119509	109463	25	60100	40102	10001	10000	30100	10000	10000	1078999	5735455	6133818	0	120026	120050	120050	113145	16	113636	50100	30200	10000	10000	60200	20000	10000	120050	120035	1	1	50201	100	99	100	40100	10000	10000	0	100	10000	0	1	10000	0	0	0	10000	1	1	0	0	0	3210	1	101	1	1	119657	40002	6	6	8	10000	40100	120051	120051	120051	120051	120036
50204	120050	899	0	0	1	1	0	0	292	0	0	0	0	120020	119509	109463	25	60103	40102	10000	10000	30100	10000	10000	1078862	5736188	6134461	0	120023	120148	120042	113146	3	113658	50100	30200	10000	10000	60200	20000	10000	120050	120047	1	1	50201	100	99	100	40100	10000	10000	0	100	10000	0	1	10000	1	0	0	10000	1	1	0	0	0	3210	1	101	1	1	119657	40002	6	6	0	10000	40100	120036	120036	120048	120048	120048
50204	120047	899	0	0	0	0	0	0	85	0	1	0	0	120020	119493	109449	25	60100	40102	10000	10000	30100	10000	10000	1078999	5736188	6134461	0	120023	120050	120050	113146	3	113658	50100	30200	10000	10000	60200	20000	10000	120035	120047	1	1	50201	100	99	100	40100	10000	10000	0	100	10000	0	0	10000	0	0	0	10000	1	1	0	0	0	3210	1	135	1	1	119657	40000	0	0	5	10000	40100	120048	120048	120051	120075	120051
50204	120048	899	0	0	0	1	0	0	94	0	1	0	0	120032	119513	109461	25	60103	40100	10000	10000	30100	10000	10000	1079026	5735455	6133818	0	120026	120050	120050	113145	3	113668	50100	30200	10000	10000	60200	20000	10000	120035	120047	1	1	50201	100	99	100	40100	10000	10000	0	100	10000	0	1	10000	1	0	0	10000	0	1	0	0	0	3210	1	107	1	1	119657	40002	6	6	8	10000	40100	120051	120051	120051	120048	120048
50204	120035	899	0	0	0	0	0	0	85	0	0	0	0	120020	119493	109449	25	60103	40102	10001	10000	30100	10000	10000	1078999	5735455	6136166	0	120031	120035	120050	113145	3	113636	50100	30200	10000	10000	60200	20000	10000	120035	120035	1	1	50201	100	99	100	40100	10000	10000	0	100	10000	0	1	10000	0	0	0	10000	0	1	0	0	0	3210	1	101	1	1	119646	40002	9	0	8	10000	40100	120051	120051	120051	120036	120036
50204	120035	899	0	0	0	0	0	0	339	0	0	0	0	120020	119509	109461	25	60103	40102	10001	10000	30100	10064	10000	1078999	5736188	6136449	0	120014	120050	120035	113145	15	113637	50100	30200	10000	10000	60200	20000	10000	120035	120047	1	1	50201	100	99	100	40100	10000	10000	0	100	10000	0	0	10000	1	0	0	10000	1	1	0	0	0	3210	1	135	1	1	119657	40000	9	9	0	10000	40100	120051	120051	120051	120051	120054
50204	120050	899	0	0	0	0	0	0	28	0	1	0	0	120082	119493	109449	25	60103	40102	10000	10000	30100	10000	10000	1078999	5736188	6134461	0	120026	120050	120035	113145	3	113667	50100	30200	10000	10000	60200	20000	10000	120035	120047	1	1	50201	100	99	100	40100	10000	10000	0	100	10034	2	0	10026	1	2	85371	10034	1	1	2	0	0	3897	2	318	1	1	120956	40227	9	9	5	10000	40100	120048	120048	120131	120036	120051
50204	120050	899	1	1	0	0	21	25	3595	1936	1	0	1	123153	121009	110344	877	60433	40387	10063	10048	34521	11574	11242	1145225	5809843	6192101	0	120026	120035	120050	113347	387	115333	54576	33441	10000	10000	60200	21296	10163	120050	120607	17	1	50201	100	99	100	40100	10000	10000	0	100	10046	0	1	10023	1	0	75290	10010	1	1	0	0	0	3210	2	310	3	4	122932	40279	0	9	8	10000	40100	124275	123874	122760	123460	123376
50204	123177	959	1	0	1	1	0	3	1	0	1	0	0	120035	119509	109449	25	60103	40102	10000	10000	30100	10000	10000	1078999	5736188	6133818	0	120026	120050	120052	113141	3	113667	50100	30200	10000	10000	60200	20000	10000	120050	120047	1	1	50201	100	99	100	40100	10000	10000	0	100	10000	0	0	10000	9	0	0	10000	0	0	0	0	0	3210	1	135	1	1	119660	40002	0	9	0	10000	40100	120036	120048	120051	120051	120051

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 9.0053

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	09	l2 tlb miss data (0b)	0e	0f	18	19	1e	1f	22	23	3a	3f	4d	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	af	b5	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	branch cond mispred nonspec (c5)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
50025	120053	943	1	1	0	1	0	1	8	16	11	1408	1	0	1	120773	120123	109466	464	60100	40057	10034	10026	30010	10845	10792	1079575	5773634	6159590	0	120749	121554	120186	113638	3	114511	50010	32425	10854	10143	62900	20000	10000	120436	120041	2	1	50021	10	9	10	40010	10000	10000	1	10	10002	2	0	10003	0	1	4	10000	1	1	1	1	0	0	0	3140	5	107	3	2	119668	40002	6	6	0	10000	40010	120042	120044	120043	120145	120057
50024	120053	899	1	1	1	0	0	0	0	0	2	0	0	0	1	123295	121147	110658	1007	60424	40287	10074	10072	35091	11885	11773	1160917	5821982	6227771	0	122647	123425	123428	114207	457	115589	58503	35847	11974	11992	63898	20106	10000	120082	120057	1	1	50021	10	9	10	40010	10000	10000	1	10	10003	3	1	10002	0	2	1	10000	1	1	0	1	0	0	1	3140	5	107	1	1	119671	40004	6	6	0	10000	40010	120054	120057	120054	120057	120054
50024	120053	899	1	1	1	1	0	0	0	0	1	0	1	0	0	120038	119511	109466	25	60016	40012	10002	10000	30010	10000	10000	1079575	5736476	6133764	0	120029	120053	120041	113171	3	113692	50010	30020	10000	10000	60020	20000	10000	120059	120053	1	1	50021	10	9	10	40010	10000	10000	0	10	10003	3	1	10001	0	1	1	10000	1	1	1	1	0	0	0	3140	6	107	1	1	119668	40004	0	0	5	10000	40010	120042	120054	120054	120054	120054
50024	120053	900	1	2	0	1	0	0	0	0	143	0	0	0	1	120026	119511	109455	25	60016	40014	10001	10000	30010	10000	10049	1079575	5735750	6133764	0	120029	120056	120053	113171	3	113692	50010	30180	10000	10000	60020	20000	10000	120109	120055	1	1	50021	10	9	10	40010	10000	10000	0	10	10002	2	1	10002	0	1	1	10000	1	1	0	1	1	0	0	3140	3	107	1	1	119671	40010	6	6	5	10000	40010	120057	120057	120142	120240	120054
50024	120053	899	1	0	0	1	0	0	0	0	2	0	0	0	0	120038	119511	109752	25	60013	40014	10002	10000	30010	10000	10000	1079602	5736572	6133764	0	120032	120056	120053	113159	3	113692	50010	30020	10000	10000	60020	20000	10000	120053	120053	1	1	50021	10	9	10	40010	10000	10000	0	10	10001	1	1	10001	1	0	4	10000	1	1	1	1	0	0	0	3140	2	107	1	1	119668	40002	6	9	5	10000	40010	120057	120057	120042	120054	120054
50024	120053	899	1	0	1	1	0	0	0	0	1	0	0	0	1	120038	119514	109466	25	60016	40014	10002	10000	30010	10000	10000	1079575	5736332	6133764	0	120029	120041	120053	113174	16	113695	50010	30020	10000	10000	60020	20106	10000	120446	120154	1	1	50021	10	9	10	40010	10000	10000	0	10	10023	1	1	10001	0	1	1	10000	1	1	1	1	1	0	0	3140	4	107	2	2	119668	40004	0	6	5	10000	40010	120057	120057	120060	120061	120057
50024	120041	899	1	0	0	0	0	0	0	0	2	0	0	0	0	120026	119499	109469	25	60016	40014	10002	10000	30010	10000	10000	1079602	5736476	6133216	0	120029	120053	120041	113171	3	113692	50010	30020	10000	10000	60020	20000	10000	120076	120053	1	1	50021	10	9	10	40010	10000	10000	0	10	10001	1	1	10002	1	0	1	10000	1	1	1	1	1	0	0	3140	2	107	1	1	119674	40004	0	6	5	10000	40010	120238	120054	120057	120054	120042
50024	120041	899	1	1	1	1	0	0	0	0	289	264	1	0	1	120038	119511	109466	25	60016	40012	10002	10000	30010	10000	10000	1079602	5736332	6133764	0	120029	120053	120053	113174	3	113695	50010	30020	10000	10000	60020	20000	10000	120102	120054	1	1	50021	10	9	10	40010	10000	10000	0	10	10002	1	1	10001	0	0	1	10000	1	1	1	1	0	0	0	3140	3	107	1	1	119668	40004	6	6	5	10000	40010	120057	120057	120057	120054	120140
50024	120053	899	1	0	1	1	0	0	0	1	2	0	1	0	0	120038	119514	109469	25	60016	40030	10002	10000	30010	10000	10000	1079575	5736332	6133764	0	120029	120053	120053	113159	3	113692	50010	30020	10000	10000	60020	20000	10000	120088	120053	1	1	50021	10	9	10	40010	10000	10000	0	10	10002	2	1	10001	0	0	1	10000	1	1	0	1	1	0	0	3140	4	107	2	1	119671	40004	9	6	0	10000	40010	120054	120054	120054	120054	120054
50024	120056	899	1	0	1	0	0	1	0	0	1	0	1	0	1	120041	119514	109466	25	60016	40014	10002	10000	30010	10000	10000	1079602	5735750	6133917	0	120032	120053	120053	113171	3	113695	50010	30020	10000	10000	60020	20000	10000	120074	120053	1	1	50021	10	9	10	40010	10000	10000	0	10	10003	2	1	10002	0	0	1	10000	0	1	1	1	2	0	0	3140	4	107	2	2	119668	40004	6	6	5	10000	40010	120054	120042	120054	120054	120057

Test 4: throughput

Count: 8

Code:

  ldr s0, [x6, w7, sxtw]
  ldr s0, [x6, w7, sxtw]
  ldr s0, [x6, w7, sxtw]
  ldr s0, [x6, w7, sxtw]
  ldr s0, [x6, w7, sxtw]
  ldr s0, [x6, w7, sxtw]
  ldr s0, [x6, w7, sxtw]
  ldr s0, [x6, w7, sxtw]

Initialization

  mov x7, 8

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.3340

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	09	0e	0f	1e	22	24	3a	3f	43	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	c2	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
80205	26723	200	0	0	1	63	1	0	1	26712	2	18	0	0	25	80100	100	80000	100	80015	500	1177116	1	26682	26828	26712	16756	6	16679	80114	200	80024	200	160048	26722	26722	1	1	80201	100	99	100	100	80000	80000	0	100	80000	39	80000	0	35	80035	6	1	35	43	0	1	1	1	5118	0	16	0	0	26724	6	0	4	80000	100	26728	26728	26728	26728	26728
80204	26707	200	0	0	0	60	0	0	1	26712	0	0	12	16	25	80100	100	80000	100	80015	500	1159814	1	26682	26859	26729	16662	6	16679	80115	200	80024	200	160048	26707	26722	1	1	80201	100	99	100	100	80000	80000	0	100	80000	0	80000	0	39	80000	6	0	35	43	0	1	1	1	5118	0	16	0	0	26724	0	0	2	80000	100	26877	26726	26728	26723	26728
80204	26727	200	0	0	0	93	0	0	1	26692	2	12	12	16	25	80100	100	80000	100	80015	500	1177116	1	26702	26812	26729	16662	6	16681	80116	200	80024	200	160048	26722	26722	1	1	80201	100	99	100	100	80000	80000	0	100	80000	39	80039	0	0	80035	6	0	35	43	0	1	1	1	5118	0	16	0	0	26719	10	6	2	80000	100	26733	26733	26723	26723	26723
80204	26710	200	0	0	0	60	1	0	0	26692	2	18	12	16	25	80100	100	80000	100	80014	500	1167875	1	26682	26722	26707	16650	6	16678	80115	200	80024	200	160048	26727	26722	1	1	80201	100	99	100	100	80000	80000	1	100	80000	0	80039	0	0	80000	6	1	35	0	0	1	1	1	5118	0	16	0	0	26704	6	6	4	80000	100	26723	26723	26728	26708	26728
80204	26727	200	0	0	0	0	1	0	2	26692	2	12	12	16	25	80100	100	80000	100	80015	500	1165856	1	26702	26744	26830	16657	6	16659	80114	200	80024	200	160048	26727	26707	1	1	80201	100	99	100	100	80000	80000	0	100	80000	39	80000	0	39	80035	6	1	0	43	0	1	1	1	5118	0	16	0	0	26704	10	0	4	80000	100	26728	26708	26723	26723	26728
80204	26707	200	0	0	0	51	0	0	2	26692	2	12	0	0	25	80100	100	80000	100	80015	500	1167303	1	26682	26838	26712	16661	6	16659	80115	200	80024	200	160048	26707	26722	1	1	80201	100	99	100	100	80000	80000	0	100	80000	39	80039	0	39	80000	6	1	39	39	0	1	1	1	5118	0	16	0	0	26724	10	10	4	80000	100	26741	26734	26723	26719	26728
80204	26722	200	0	0	0	101	0	0	2	26692	0	12	12	16	25	80100	100	80000	100	80200	500	1165856	1	26702	26799	26733	16641	6	16679	80115	200	80024	200	160048	26722	26707	1	1	80201	100	99	100	100	80000	80000	0	100	80000	39	80000	0	39	80039	0	0	39	43	0	1	1	1	5118	0	16	0	0	26719	10	10	2	80000	100	26708	26708	26723	26723	26728
80204	26727	200	0	0	0	96	1	0	0	26692	2	18	18	12	25	80100	100	80000	100	80015	500	1167875	1	26702	26801	26713	16641	6	16659	80114	200	80024	200	160048	26727	26707	1	1	80201	100	99	100	100	80000	80000	0	100	80000	39	80039	0	42	80039	0	0	0	43	0	1	1	1	5118	0	16	0	0	26724	6	6	2	80000	100	26728	26728	26708	26728	26708
80204	26727	200	0	0	0	63	1	0	2	26692	2	12	0	16	25	80100	100	80000	100	80015	500	1167303	1	26697	26847	26712	16658	6	16679	80114	200	80024	200	160048	26727	26707	1	1	80201	100	99	100	100	80000	80000	0	100	80000	39	80039	0	39	80040	6	1	0	43	0	1	1	1	5118	0	16	0	0	26704	10	10	4	80000	100	26832	26708	26729	26727	26735
80204	26727	200	0	0	1	54	0	0	2	26712	0	12	12	16	25	80100	100	80000	100	80015	500	1165856	1	26682	26805	26813	16661	6	16682	80114	200	80024	200	160048	26722	26722	1	1	80201	100	99	100	100	80000	80000	1	100	80000	39	80039	0	39	80039	6	1	35	43	0	1	1	1	5118	1	16	0	0	26719	10	0	4	80000	100	26728	26728	26723	26708	26728

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.3342

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	09	l2 tlb miss data (0b)	0e	0f	1e	22	24	3a	3f	43	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	92	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
80025	26737	200	1	1	0	0	0	0	238	0	0	3	26722	2	0	0	19	25	80010	10	80000	10	80000	50	1173975	26712	26736	26719	16689	3	16716	80010	20	80000	20	160000	26736	26737	1	1	80021	10	9	1	10	10	80000	80000	1	10	80021	20	43	80019	0	0	1	60	80040	6	1	19	43	19	1	0	5020	2	16	3	3	26734	13	13	0	80000	10	26737	26737	26715	26738	26716
80024	26715	200	1	1	1	1	0	0	81	0	0	1	26721	3	0	7	0	25	80010	10	80000	10	80000	50	1167219	26711	26836	26846	16688	3	16695	80010	20	80000	20	160000	26736	26736	1	1	80021	10	9	0	10	10	80000	80000	0	10	80020	20	0	80019	0	0	0	61	80040	0	1	19	43	19	2	0	5020	3	16	2	2	26712	0	13	5	80000	10	26716	26737	26737	26738	26737
80024	26714	200	1	0	0	1	0	0	66	1	0	3	26721	3	0	7	20	25	80010	10	80000	10	80000	50	1165304	26689	26827	26744	16984	3	16816	80010	20	80000	20	160000	26737	26736	1	1	80021	10	9	0	10	10	80000	80000	0	10	80019	20	0	80058	0	0	0	21	80040	6	1	58	0	19	1	0	5020	2	16	2	2	26733	13	0	5	80000	10	26737	26716	26737	26737	26738
80024	26737	200	1	0	1	1	0	0	67	1	0	2	26699	0	0	0	21	25	80010	10	80000	10	80000	50	1166960	26711	26843	26723	16690	3	16694	80010	20	80000	20	160000	26736	26737	1	1	80021	10	9	0	10	10	80000	80000	0	10	80019	20	44	80019	0	0	1	60	80041	6	1	59	0	19	1	0	5020	2	16	2	2	26712	13	0	5	80000	10	26738	26737	26737	26737	26738
80024	26736	200	1	1	0	1	0	0	67	1	0	3	26699	3	7	7	1	25	80010	10	80000	10	80000	50	1173975	26712	26852	26723	16695	3	16723	80010	20	80000	20	160000	26737	26736	1	1	80021	10	9	0	10	10	80000	80000	0	10	80020	19	43	80059	1	0	1	61	80000	6	1	59	43	19	1	0	5020	3	16	2	2	26711	13	0	0	80000	10	26737	26737	26715	26737	26738
80024	26736	200	1	1	1	0	0	0	67	1	0	0	26700	0	0	0	0	25	80010	10	80000	10	80000	50	1173975	26712	26853	26720	16688	3	16695	80010	20	80000	20	160000	26736	26736	1	1	80021	10	9	0	10	10	80000	80000	0	10	80019	19	43	80059	1	0	0	21	80039	6	1	59	43	19	1	0	5020	2	16	2	2	26711	13	13	5	80000	10	26715	26737	26740	26737	26738
80025	26715	200	1	1	1	1	0	0	21	1	0	2	26722	2	7	7	0	25	80010	10	80000	10	80000	50	1167219	26692	26734	26740	16681	3	16718	80010	20	80000	20	160000	26736	26715	1	1	80021	10	9	0	10	10	80000	80000	0	10	80019	19	43	80059	0	0	1	61	80040	0	0	59	43	19	1	0	5020	3	16	3	3	26734	13	0	0	80000	10	26738	26738	26738	26716	26737
80024	26736	200	1	0	1	0	0	0	21	0	0	1	26721	3	7	0	20	25	80010	10	80000	10	80000	50	1168583	26711	26846	26723	17081	3	16729	80010	20	80000	20	160000	26714	26715	1	1	80021	10	9	0	10	10	80000	80000	0	10	80020	20	0	80019	0	0	0	61	80039	6	0	59	0	19	3	0	5020	2	16	3	2	26734	0	13	5	80000	10	26738	26716	26737	26715	26737
80024	26715	200	1	0	0	0	0	0	21	1	0	1	26721	3	0	7	0	25	80010	10	80000	10	80000	50	1173975	26689	26876	26748	16690	3	16716	80010	20	80000	20	160000	26736	26736	1	1	80021	10	9	0	10	10	80000	80000	0	10	80019	21	43	80059	1	0	1	61	80039	6	1	19	0	18	0	0	5020	2	16	2	2	26712	0	13	0	80000	10	26738	26716	26738	26716	26737
80024	26736	200	1	0	1	0	0	0	66	0	0	2	26721	3	7	7	0	25	80010	10	80000	10	80000	50	1173975	26711	26744	26863	16707	3	16717	80010	20	80000	20	160000	26714	26736	1	1	80021	10	9	0	10	10	80000	80000	1	10	80020	19	43	80059	0	0	2	61	80000	6	0	19	43	19	0	0	5020	3	16	2	2	26712	0	13	0	80000	10	26716	26738	26738	26737	26737

LDR (register, sxtw, S)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->2 roundtrip

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: Latency 1->3 roundtrip

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 4: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations