Firestorm: LDR (register, uxtw, D) measurements

Code:

  ldr d0, [x6, w7, uxtw]

Initialization

  mov x7, #4
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 1.000

SIMD/FP unit issues: 0.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	09	l2 tlb miss data (0b)	0e	1e	22	3a	3f	43	46	49	4f	51	schedule uop (52)	schedule ldst uop (55)	dispatch ldst uop (58)	simd uops in schedulers (5a)	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map ldst uop (7d)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	92	inst simd load (98)	inst ldst (9b)	9d	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	ea	eb	ec	? ldst retires (ed)	f5	f6	f7	f8	fd
1005	403	2	1	0	1	1	0	66	0	2	388	3	7	7	19	25	1000	1000	1000	15508	378	403	404	225	3	261	1000	1000	2000	403	402	1	1	1001	1	1000	1000	1	1020	21	43	1059	0	0	0	61	1040	6	1	59	43	19	0	73	2	16	1	1	400	13	13	5	1000	404	403	404	416	404
1004	403	3	1	1	1	1	0	66	0	3	388	2	7	7	18	25	1000	1000	1000	15621	378	403	404	225	3	261	1000	1000	2000	403	403	1	1	1001	0	1000	1000	0	1020	20	43	1059	0	0	0	60	1040	6	1	58	43	19	1	73	1	16	1	1	399	13	13	5	1000	404	404	403	405	404
1004	403	3	1	1	1	1	0	66	1	3	387	3	7	7	19	25	1000	1000	1000	15555	378	404	403	225	3	261	1000	1000	2000	403	402	1	1	1001	1	1000	1000	0	1020	19	43	1059	1	0	1	21	1040	6	1	58	43	19	0	73	1	16	1	1	400	13	13	5	1000	407	404	404	404	403
1004	405	3	1	1	0	0	0	67	0	3	388	2	7	7	20	25	1000	1000	1000	15480	379	404	403	225	3	260	1000	1000	2000	403	403	1	1	1001	0	1000	1000	0	1019	19	43	1059	1	0	1	61	1040	6	1	58	43	19	0	73	1	16	1	1	399	13	13	5	1000	404	404	403	404	404
1004	404	3	1	1	0	0	0	67	0	3	388	2	7	7	19	25	1000	1000	1000	15524	378	403	403	225	3	261	1000	1000	2000	402	403	1	1	1001	0	1000	1000	0	1021	19	43	1058	1	0	1	61	1040	6	1	59	45	19	1	73	1	16	1	1	400	13	13	5	1000	404	404	404	403	404
1004	403	3	1	0	1	0	0	67	1	2	388	3	7	7	19	25	1000	1000	1000	15526	378	402	403	225	3	261	1000	1000	2000	403	403	1	1	1001	0	1000	1000	0	1019	20	43	1059	1	0	1	60	1040	6	1	58	43	19	1	73	1	16	1	1	400	13	13	5	1000	403	404	404	404	404
1004	402	2	1	1	1	1	0	67	0	2	388	3	7	7	20	25	1000	1000	1000	15480	378	405	404	225	3	261	1000	1000	2000	403	402	1	1	1001	1	1000	1000	1	1020	21	43	1059	1	0	2	61	1039	6	1	59	43	19	2	73	1	16	1	1	400	13	13	5	1000	403	404	404	404	404
1004	402	3	1	1	0	1	0	67	0	2	388	3	7	7	20	25	1000	1000	1000	15480	378	403	403	225	3	260	1000	1000	2000	403	403	1	1	1001	0	1000	1000	1	1019	19	43	1058	1	0	1	61	1040	6	1	59	43	19	1	73	1	16	1	1	399	13	13	5	1000	404	404	405	404	404
1004	403	2	1	1	0	1	0	67	0	3	388	3	7	7	20	25	1000	1000	1000	15480	378	403	403	226	3	260	1000	1000	2000	403	403	1	1	1001	0	1000	1000	0	1019	20	43	1059	0	0	1	60	1040	6	1	58	43	19	1	73	1	16	1	1	399	13	13	5	1000	404	403	403	404	404
1004	403	3	1	1	0	1	0	67	1	2	388	3	7	7	19	25	1000	1000	1000	15506	378	403	403	225	3	264	1000	1000	2000	403	403	1	1	1001	0	1000	1000	0	1020	21	43	1059	1	0	0	61	1042	6	1	59	43	19	2	73	1	16	1	1	400	13	13	5	1000	404	404	404	404	404

Test 2: Latency 1->2 roundtrip

Chain cycles: 3

Code:

  ldr d0, [x6, w7, uxtw]
  fmov x0, d0
  eor x8, x8, x0
  eor x8, x8, x0
  add x6, x6, x8

Initialization

  mov x7, #4
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 9.0050

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	l2 tlb miss data (0b)	0e	0f	1e	1f	22	24	3a	3f	4d	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	af	b5	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
50205	120053	899	0	0	0	0	0	37	0	1	0	0	120035	119519	109600	25	60100	40102	10001	10000	30100	10000	10000	1078862	5736188	6133818	1	120026	120050	120050	113145	3	113658	50100	30200	10000	10000	60200	20000	10000	120035	120035	1	1	50201	100	99	100	40100	10000	10000	1	100	10000	0	1	10010	0	0	0	10000	1	0	1	0	0	3210	1	107	1	1	119657	40000	9	0	8	10000	40100	120036	120036	120051	120051	120054
50204	120050	899	0	0	0	0	0	1	0	1	0	0	120023	119509	109463	25	60115	40136	10001	10000	30100	10000	10000	1078999	5736188	6136166	0	120026	120050	120035	113145	3	113636	50100	30200	10000	10000	60200	20000	10000	120047	120076	1	1	50201	100	99	100	40100	10000	10000	0	100	10000	0	1	10000	0	0	0	10000	1	0	1	0	0	3210	1	101	2	1	119660	40002	0	6	8	10000	40100	120051	120036	120036	120051	120036
50204	120050	899	0	0	0	1	0	1	0	1	0	0	120035	119509	109463	25	60103	40102	10000	10000	30100	10000	10000	1078999	5736044	6134461	0	120026	120050	120050	113145	3	113636	50100	30200	10000	10163	60584	20000	10000	120047	120047	1	1	50201	100	99	100	40100	10000	10000	0	100	10000	0	1	10000	0	0	0	10000	1	0	1	0	0	3210	1	101	1	1	119657	40002	0	6	0	10000	40100	120051	120036	120051	120036	120036
50204	120050	899	0	0	0	0	0	1	0	0	0	0	120035	119509	109463	25	60103	40102	10001	10000	30100	10000	10000	1078999	5736188	6136166	1	120026	120051	120053	113142	3	113667	50100	30397	10000	10000	60200	20000	10000	120050	120047	1	1	50201	100	99	100	40100	10000	10000	0	100	10000	0	1	10000	0	0	14147	10000	1	0	1	0	0	3210	1	107	1	4	119660	40002	9	6	8	10000	40100	120056	120051	120051	120051	120056
50204	120050	899	0	0	0	0	0	1	0	0	0	0	120020	119509	109449	25	60103	40102	10000	10000	30100	10000	10000	1078862	5736188	6133818	1	120026	120050	120050	113143	3	113667	50384	30200	10000	10000	60200	20000	10000	120050	120035	1	1	50201	100	99	100	40100	10000	10000	0	100	10000	0	1	10000	1	0	0	10000	1	0	1	0	0	3210	1	101	1	1	119660	40002	9	6	8	10000	40100	120036	120036	120051	120051	120036
50204	120047	899	0	0	0	0	1	0	0	0	0	0	120035	119519	109463	25	60103	40100	10001	10000	30100	10000	10000	1079200	5736188	6136166	1	120011	120050	120050	113145	3	113667	50100	30200	10000	10000	60200	20000	10000	120050	120035	1	1	50201	100	99	100	40100	10000	10000	0	100	10000	0	1	10000	0	0	0	10000	0	0	1	0	0	3210	1	134	1	1	119665	40033	9	0	8	10000	40100	120051	120051	120051	120051	120052
50204	120050	899	0	0	0	0	0	1	0	0	0	0	120040	119509	109463	25	60103	40100	10001	10000	30100	10000	10000	1078999	5736188	6136166	1	120026	120035	120050	113244	3	113667	50100	30200	10000	10000	60200	20000	10000	120047	120035	1	1	50201	100	99	100	40100	10000	10000	0	100	10000	0	1	10000	0	0	0	10000	1	0	1	0	0	3210	1	157	1	1	119657	40002	0	9	5	10000	40100	120052	120425	120051	120036	120048
50204	120035	899	0	0	0	0	0	1	0	0	0	0	120035	119509	109461	25	60103	40102	10000	10000	30100	10000	10000	1078862	5736188	6136166	1	120023	120050	120035	113145	3	113658	50100	30200	10000	10000	60200	20000	10000	120050	120055	1	1	50201	100	99	100	40100	10000	10000	0	100	10000	0	0	10000	0	0	0	10000	1	0	1	0	0	3210	1	107	1	1	119661	40002	9	6	8	10000	40100	120051	120036	120051	120036	120051
50204	120050	899	0	0	0	0	0	0	0	1	0	0	120035	119509	109468	25	60103	40102	10000	10000	30100	10000	10000	1078999	5736188	6133818	1	120068	120050	120050	113141	3	113667	50100	30200	10000	10000	60200	20000	10000	120050	120035	1	1	50201	100	99	100	40100	10000	10000	0	100	10000	0	1	10000	1	0	0	10000	1	0	1	0	0	3210	1	107	1	1	119657	40000	9	6	0	10000	40100	120036	120051	120048	120036	120036
50204	120035	899	0	0	0	0	0	1	0	1	0	0	120032	119509	109449	25	60103	40100	10001	10000	30100	10000	10000	1078999	5736188	6136166	0	120026	120050	120050	113145	3	113667	50100	30200	10000	10000	60200	20000	10000	120035	120035	1	1	50201	100	99	100	40100	10000	10000	1	100	10000	0	1	10000	0	0	6	10000	0	0	1	0	0	3210	1	107	3	1	119660	40002	6	6	5	10000	40100	120051	120036	120051	120048	120048

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 9.0057

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	l2 tlb miss data (0b)	0e	0f	18	19	1e	1f	22	23	3a	3f	4d	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	af	b5	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	branch cond mispred nonspec (c5)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
50025	120057	899	1	1	0	0	0	1	2	20	0	1	0	1	120042	119620	109512	25	60016	40014	10002	10000	30010	10052	10098	1079611	5736524	6133968	120033	120057	120057	113175	3	113700	50010	30020	10000	10000	60020	20000	10000	120057	120057	1	1	50021	10	9	10	40010	10000	10000	0	10	10001	3	1	10001	8	0	1	10000	1	1	1	1	0	0	3140	2	107	2	2	119656	40004	0	45	9	10000	40010	120058	120042	120058	120042	120059
50024	120057	900	1	0	2	0	1	2	2	179	176	0	0	1	120042	119515	109470	25	60016	40014	10002	10000	30010	10000	10000	1079611	5736524	6133968	120036	120057	120057	113159	3	113696	50010	30020	10000	10000	60020	20000	10000	120059	120057	1	1	50021	10	9	10	40010	10000	10000	0	10	10003	1	1	10002	1	2	1	10000	1	1	1	1	1	0	3140	3	107	2	2	119672	40004	10	28	9	10000	40010	120059	120063	120059	120058	120058
50024	120041	900	1	1	1	0	0	0	0	2	0	0	0	0	120042	119515	109470	25	60016	40014	10002	10000	30010	10000	10000	1079611	5736524	6133216	120033	120057	120057	113175	3	113680	50010	30020	10000	10000	60020	20000	10000	120057	120057	1	1	50021	10	9	10	40010	10000	10000	0	10	10002	2	1	10001	0	0	1	10000	1	1	1	1	1	0	3140	3	107	3	2	119672	40004	0	10	9	10000	40010	120058	120058	120058	120058	120058
50024	120041	899	1	1	1	0	0	0	0	1	0	0	0	1	120026	119515	109470	25	60016	40012	10002	10000	30010	10000	10000	1079463	5735750	6133216	120033	120057	120041	113159	3	113696	50010	30020	10000	10000	60020	20000	10000	120041	120041	1	1	50021	10	9	10	40010	10000	10000	1	10	10002	2	0	10001	0	0	1	10000	0	1	1	1	1	0	3140	2	107	2	2	119672	40002	0	10	9	10000	40010	120058	120058	120058	120058	120058
50024	120057	899	1	0	0	0	1	0	0	2	0	1	0	1	120026	119515	109470	25	60013	40014	10002	10000	30010	10000	10000	1079611	5736524	6133968	120017	120041	120041	113175	3	113680	50010	30020	10000	10000	60020	20000	10000	120057	120041	1	1	50021	10	9	10	40010	10000	10000	1	10	10002	1	1	10002	0	2	1	10000	1	1	1	1	1	0	3140	2	107	3	3	119656	40004	10	10	9	10000	40010	120058	120058	120058	120058	120042
50024	120057	899	1	0	1	0	0	0	0	1	0	0	0	1	120026	119515	109470	25	60016	40014	10002	10000	30010	10000	10000	1081848	5735750	6133968	120033	120057	120057	113159	3	113696	50010	30020	10000	10000	60020	20000	10000	120057	120041	2	1	50021	10	9	10	40010	10000	10000	0	10	10001	2	1	10001	0	0	1	10000	1	1	1	1	0	0	3140	2	107	2	2	119679	40004	10	10	9	10000	40010	120058	120042	120058	120507	120058
50024	120057	899	1	1	0	0	0	0	0	2	0	1	0	1	120042	119515	109455	25	60016	40014	10001	10000	30010	10000	10000	1079611	5736524	6133216	120033	120041	120041	113175	3	113696	50010	30020	10000	10000	60020	20128	10000	120057	120041	1	1	50021	10	9	10	40010	10000	10000	1	10	10001	1	1	10002	6	0	1	10000	1	1	1	1	0	0	3140	2	107	2	4	119672	40004	0	10	9	10000	40010	120058	120042	120058	120042	120042
50024	120057	899	1	1	0	0	0	0	0	2	0	1	0	1	120042	119499	109455	25	60016	40012	10002	10000	30010	10000	10000	1079463	5736524	6135065	120033	120057	120057	113159	3	113680	50281	30020	10000	10000	60020	20000	10000	120057	120057	1	1	50021	10	9	10	40010	10000	10000	0	10	10002	1	0	10002	0	0	1	10000	1	1	0	1	1	0	3140	2	107	2	2	119672	40004	10	10	0	10000	40010	120058	120058	120058	120058	120058
50024	120057	899	1	1	0	0	0	0	0	2	0	0	0	1	120026	119499	109470	25	60016	40014	10002	10000	30010	10000	10000	1079463	5736524	6133968	120033	120057	120057	113159	3	113696	50010	30020	10000	10000	60020	20000	10000	120057	120057	1	1	50021	10	9	10	40010	10000	10000	1	10	10003	1	1	10001	0	1	1	10000	0	1	0	1	1	0	3140	2	107	2	2	119656	40004	10	10	9	10000	40010	120058	120058	120058	120058	120105
50024	120057	899	1	0	1	1	1	0	0	2	0	1	0	1	120042	119515	109470	25	60016	40012	10001	10000	30010	10000	10000	1082725	5735750	6133968	120036	120057	120057	113175	3	113696	50010	30020	10000	10000	60020	20000	10000	120057	120057	1	1	50021	10	9	10	40010	10000	10000	1	10	10001	3	1	10002	1	1	1	10000	1	1	1	1	1	0	3140	2	107	2	2	119672	40004	10	22	9	10000	40010	120058	120058	120058	120058	120058

Test 3: Latency 1->3 roundtrip

Chain cycles: 3

Code:

  ldr d0, [x6, w7, uxtw]
  fmov x0, d0
  eor x8, x8, x0
  eor x8, x8, x0
  add x7, x7, x8

Initialization

  mov x7, #4
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 9.0054

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	0e	0f	18	19	1e	22	23	24	3a	3f	4d	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	69	6b	6d	6e	map stall dispatch (70)	int prf full (71)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	af	b5	l1d cache miss ld nonspec (bf)	c2	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
50205	120047	899	0	0	0	0	13	1	0	0	1	120041	119513	109466	25	60106	40104	10001	10000	30100	10000	10000	1079053	5736476	6133458	1	120036	0	120056	120117	113143	0	3	113673	50100	30200	10000	10000	60200	20000	10000	120056	120053	1	1	50201	100	99	100	40100	10000	10000	0	100	10001	1	0	10003	1	0	4	10000	1	1	0	0	3210	2	103	1	1	119661	40039	9	6	8	10000	40100	120039	120051	120036	120051	120051
50204	120047	899	0	0	0	0	1	0	0	0	0	120034	119509	109461	25	60103	40100	10001	10000	30100	10000	10000	1078999	5735455	6133818	1	120026	0	120050	120035	113158	0	3	113658	50100	30200	10000	10000	60200	20000	10000	120047	120047	1	1	50201	100	99	100	40100	10000	10000	1	100	10002	0	1	10000	14	0	3386	10000	0	1	0	0	3210	1	101	1	1	119647	40000	6	9	8	10000	40100	120051	120036	120036	120051	120051
50204	120035	899	0	0	0	0	1	0	1	0	0	120035	119509	109463	25	60100	40102	10000	10000	30100	10000	10000	1078862	5736188	6134461	1	120011	0	120050	120047	113144	0	3	113667	50100	30200	10000	10000	60200	20000	10000	120035	120047	1	1	50201	100	99	100	40100	10000	10000	0	100	10000	0	1	10000	0	0	0	10000	1	1	0	0	3210	1	107	1	1	119657	40002	9	6	8	10000	40100	120051	120036	120036	120051	120036
50204	120050	899	0	0	0	0	55	0	0	0	1	120038	119519	109461	25	60103	40100	10001	10000	30100	10000	10000	1079200	5736188	6133818	1	120023	0	120050	120105	113146	0	3	113667	50100	30200	10000	10000	60200	20000	10000	120050	120035	1	1	50201	100	99	100	40100	10000	10000	0	100	10000	0	1	10000	15	0	0	10000	1	0	0	0	3210	1	107	1	1	119646	40002	0	0	0	10000	40100	120051	120051	120051	120036	120051
50204	120035	899	1	1	0	0	1	0	0	0	0	120035	119493	109463	25	60103	40102	10001	10000	30100	10000	10000	1078862	5735455	6134461	1	120011	0	120047	120092	113143	0	3	113667	50100	30200	10000	10000	60200	20000	10000	120035	120035	1	1	50201	100	99	100	40100	10000	10000	0	100	10000	0	0	10000	0	0	0	10000	1	1	0	0	3210	1	101	1	1	119657	40002	9	0	8	10000	40100	120051	120052	120048	120036	120051
50204	120050	899	0	0	0	0	73	0	0	0	0	120035	119493	109463	25	60103	40100	10001	10000	30100	10000	10000	1078862	5735455	6136166	1	120026	0	120035	120047	113165	0	3	113667	50100	30200	10000	10000	60200	20000	10000	120050	120035	1	1	50201	100	99	100	40100	10000	10000	0	100	10000	0	1	10000	0	0	0	10000	1	0	0	0	3210	1	107	1	1	119657	40000	9	0	0	10000	40100	120036	120036	120051	120051	120051
50204	120050	899	0	0	0	0	1	0	0	0	0	120020	119509	109449	25	60100	40102	10001	10000	30100	10000	10000	1079200	5736188	6133818	1	120055	0	120035	120035	113182	0	3	113658	50100	30200	10000	10000	60200	20134	10000	120050	120048	1	1	50201	100	99	100	40100	10000	10000	0	100	10000	0	1	10000	9	1	0	10000	1	0	0	0	3247	1	101	1	1	119657	40002	0	0	8	10000	40100	120052	120410	120037	120083	120036
50205	120138	899	0	0	0	0	0	0	0	0	0	120020	119509	109463	25	60103	40100	10003	10000	30100	10000	10000	1079200	5735455	6158294	1	120250	0	120036	120050	113187	0	52	113668	50100	30200	10000	10000	60200	20640	10216	120035	120047	1	1	50201	100	99	100	40100	10000	10000	0	100	10000	0	1	10002	0	0	0	10002	1	0	2	0	3266	1	107	5	1	119657	40000	9	6	0	10000	40100	120051	120051	120051	120051	120157
50204	120050	900	0	0	4	0	6	0	1	0	0	120020	119519	109463	25	60103	40102	10001	10000	30100	10000	10000	1078999	5736188	6143493	1	120026	0	120050	120176	113184	0	3	113667	50100	30200	10054	10000	60200	20000	10000	120047	120091	1	1	50201	100	99	100	40100	10000	10000	0	100	10000	0	1	10000	0	0	3	10000	1	1	0	0	3210	1	101	1	1	119657	40000	0	6	8	10000	40100	120051	120036	120051	120051	120051
50204	120050	899	0	0	0	0	18	0	1	0	0	120035	119510	109461	25	60100	40102	10001	10000	30100	10000	10000	1079200	5735455	6133818	1	120026	0	120048	120035	113141	0	3	113658	50100	30200	10000	10066	60200	20106	10000	120062	120047	1	1	50201	100	99	100	40100	10000	10000	1	100	10000	0	1	10000	0	0	0	10000	1	0	0	0	3210	1	135	2	2	119661	40002	13	10	9	10000	40100	120058	120055	120105	120055	120052

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 9.0051

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	l2 tlb miss data (0b)	0e	0f	1e	22	23	3a	3f	4d	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	91	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	af	b5	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	l1i cache miss demand (d3)	d5	map dispatch bubble (d6)	db	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
50025	120057	899	1	1	1	0	2	1	0	0	120045	119612	109467	25	60010	40012	10000	10000	30010	10000	10000	1079557	5736236	6132757	0	120027	120035	120054	113172	3	113690	50010	30020	10000	10000	60020	20000	10000	120051	120057	1	1	50021	10	9	0	10	40010	10000	10000	1	10	10000	0	1	10000	0	0	0	10000	1	1	1	1	1	0	0	0	3140	0	20	107	0	5	17	119675	40002	13	0	9	10000	40010	120061	120042	120042	120058	120042
50024	120057	899	1	0	1	0	1	0	0	0	120026	119499	109455	25	60016	40014	10001	10000	30010	10000	10000	1079638	5736668	6133968	0	120036	120060	120057	113178	3	113696	50010	30020	10000	10000	60020	20000	10000	120041	120041	1	1	50021	10	9	0	10	40010	10000	10000	0	10	10000	0	1	10000	0	0	0	10000	1	0	1	0	0	0	0	0	3140	0	7	107	0	17	17	119666	40010	0	10	12	10000	40010	120036	120105	120091	120036	120055
50024	120054	899	0	0	0	0	1	1	0	0	120036	119512	109659	25	60013	40012	10001	10000	30010	10000	10055	1079584	5735455	6133662	0	120027	120035	120051	113169	3	113674	50010	30020	10000	10000	60020	20000	10000	120035	120119	1	1	50021	10	9	0	10	40010	10000	10000	0	10	10000	0	1	10000	0	0	0	10000	1	0	1	0	0	0	0	0	3140	0	17	107	0	17	6	119669	40002	10	10	9	10000	40010	120055	120055	120055	120055	120055
50024	120054	899	0	0	0	0	0	0	0	0	120039	119512	109467	25	60010	40020	10000	10000	30166	10000	10000	1079517	5736380	6134307	0	120030	120035	120035	113153	3	113690	50010	30020	10000	10000	60020	20000	10000	120054	120057	1	1	50021	10	9	0	10	40010	10000	10000	0	10	10000	0	1	10000	0	0	0	10000	0	0	1	0	0	0	0	0	3140	0	17	107	0	17	17	119666	40002	0	10	0	10000	40010	120036	120055	120055	120052	120055
50024	120035	899	0	0	1	0	0	1	0	0	120039	119512	109472	25	60013	40012	10000	10000	30010	10000	10000	1079584	5735455	6132757	0	120011	120059	120054	113172	3	113693	50010	30020	10000	10000	60020	20000	10000	120054	120096	1	1	50021	10	9	0	10	40010	10000	10000	0	10	10000	0	1	10000	0	0	0	10000	1	0	1	0	0	0	0	0	3140	0	17	107	0	7	17	119669	40002	13	13	12	10000	40010	120060	120036	120060	120055	120055
50024	120035	899	0	0	0	0	0	1	0	0	120039	119492	109467	25	60010	40010	10001	10000	30010	10000	10000	1079584	5735455	6133662	0	120030	120059	120054	113169	3	113674	50010	30020	10000	10000	60020	20000	10000	120054	120057	1	1	50021	10	9	0	10	40010	10000	10000	0	10	10000	0	1	10000	0	0	0	10000	1	0	1	0	0	0	0	0	3140	0	17	107	0	7	17	119650	40002	13	10	12	10000	40010	120055	120060	120055	120036	120055
50024	120035	899	0	0	0	0	0	0	0	0	120039	119512	109467	25	60010	40010	10001	10000	30010	10000	10000	1079557	5735455	6133815	0	120027	120054	120035	113172	3	113690	50010	30020	10000	10000	60020	20128	10000	120054	120164	1	1	50021	10	9	0	10	40010	10000	10000	0	10	10000	0	1	10000	0	0	0	10000	0	0	0	0	0	0	0	0	3140	0	17	107	0	8	17	119669	40002	0	10	12	10000	40010	120055	120055	120036	120055	120055
50024	120054	900	0	0	0	0	1	1	0	0	120039	119517	109464	25	60013	40012	10000	10000	30010	10000	10000	1079517	5736236	6133662	1	120027	120035	120035	113172	3	113690	50010	30020	10000	10000	60020	20000	10000	120035	120057	1	1	50021	10	9	0	10	40010	10000	10000	0	10	10000	0	1	10000	1	0	0	10000	0	0	1	0	0	0	0	0	3140	0	17	107	0	8	17	119666	40002	13	10	0	10000	40010	120036	120036	120055	120052	120052
50024	120051	899	0	0	0	0	1	0	0	0	120020	119512	109467	25	60010	40012	10001	10000	30010	10000	10000	1079584	5736380	6133662	0	120031	120054	120054	113172	3	113690	50010	30020	10000	10000	60020	20000	10000	120054	120130	1	1	50021	10	9	0	10	40010	10000	10000	0	10	10000	0	1	10000	0	0	0	10000	0	0	1	0	0	0	0	0	3140	0	17	107	0	17	17	119669	40002	13	10	9	10000	40010	120052	120052	120052	120052	120055
50024	120051	899	0	0	0	1	0	1	0	0	120039	119512	109449	25	60013	40010	10001	10000	30010	10000	10000	1079517	5736380	6133815	0	120011	120054	120054	113153	3	113693	50010	30020	10000	10000	60020	20000	10000	120054	120057	1	1	50021	10	9	0	10	40010	10000	10000	0	10	10000	0	1	10000	0	0	0	10000	1	0	0	0	0	0	0	0	3140	0	17	107	0	17	7	119650	40002	13	10	0	10000	40010	120055	120055	120036	120052	120055

Test 4: throughput

Count: 8

Code:

  ldr d0, [x6, w7, uxtw]
  ldr d0, [x6, w7, uxtw]
  ldr d0, [x6, w7, uxtw]
  ldr d0, [x6, w7, uxtw]
  ldr d0, [x6, w7, uxtw]
  ldr d0, [x6, w7, uxtw]
  ldr d0, [x6, w7, uxtw]
  ldr d0, [x6, w7, uxtw]

Initialization

  mov x7, 8

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.3340

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	09	l2 tlb miss data (0b)	0e	0f	18	19	1e	1f	22	23	3a	3f	43	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	61	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d0	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
80205	26723	200	1	0	0	1	0	0	69	0	1	0	1	26692	2	0	18	12	25	80100	100	80000	100	80015	500	1167875	1	0	26701	26731	26722	16650	6	16659	80114	200	80024	200	160048	26707	26722	1	1	80201	100	99	100	100	80000	80000	1	100	80000	0	39	80000	0	0	80035	6	1	0	39	1	1	1	5118	0	0	16	0	0	26719	0	6	6	0	80000	100	26708	26723	26723	26723	26723
80204	26722	200	0	0	1	1	0	0	0	0	0	0	1	26707	0	0	18	0	25	80100	100	80000	100	80015	500	1167875	1	0	26687	26723	26740	16650	6	16659	80115	200	80024	200	160048	26707	26722	1	1	80201	100	99	100	100	80000	80000	0	100	80000	0	39	80035	0	0	80000	0	1	36	0	1	1	1	5118	0	0	16	0	0	26719	0	6	6	0	80000	100	26723	26708	26723	26723	26728
80204	26722	200	0	0	0	1	0	0	0	0	1	0	1	26692	0	0	0	0	25	80100	100	80000	100	80015	500	1166596	0	0	26704	26722	26722	16635	6	16674	80114	200	80024	200	160048	26722	26707	1	1	80201	100	99	100	100	80000	80000	0	100	80000	0	39	80000	0	35	80035	6	0	35	39	1	1	1	5118	0	0	16	0	0	26719	0	6	6	0	80000	100	26723	26708	26708	26723	26723
80204	26722	200	0	0	0	1	0	0	41	0	0	0	0	26692	2	18	0	0	25	80100	100	80000	100	80014	500	1166596	0	0	26710	26707	26722	16650	6	16674	80115	200	80024	200	160048	26707	26707	1	1	80201	100	99	100	100	80000	80000	0	100	80000	0	39	80035	0	35	80035	0	1	35	0	1	1	1	5118	0	0	16	0	0	26704	0	0	6	2	80000	100	26723	26708	26708	26723	26723
80204	26722	200	0	0	0	1	0	0	0	0	0	1	1	26707	2	0	0	12	25	80100	100	80000	100	80014	500	1167875	0	0	26713	26707	26722	16635	6	16659	80115	200	80024	200	160048	26707	26722	1	1	80201	100	99	100	100	80000	80000	0	100	80000	0	39	80000	0	35	80035	6	0	35	39	1	1	1	5118	0	0	16	0	0	26724	0	6	6	2	80000	100	26723	26723	26708	26708	26723
80204	26722	200	0	0	0	1	0	0	41	0	0	1	1	26709	0	18	18	0	25	80100	100	80000	100	80015	500	1166596	0	0	26714	26729	26724	16650	6	16674	80115	200	80024	200	160048	26722	26707	1	1	80201	100	99	100	100	80000	80000	0	100	80000	0	39	80000	0	35	80035	6	1	35	39	1	1	1	5118	0	0	16	0	0	26719	0	0	6	0	80000	100	26708	26708	26708	26708	26723
80204	26722	200	0	0	0	1	0	0	41	0	0	1	1	26710	0	18	18	0	25	80100	100	80000	100	80015	500	1167875	0	0	26697	26729	26837	16658	6	16659	80114	200	80024	200	160048	26722	26722	1	1	80201	100	99	100	100	80000	80000	1	100	80000	0	39	80035	0	0	80035	0	1	35	39	1	1	1	5118	0	0	16	0	0	26704	0	6	6	0	80000	100	26723	26723	26723	26723	26723
80204	26707	200	0	0	0	1	0	0	41	0	0	0	0	26692	0	18	18	12	25	80100	100	80000	100	80015	500	1166596	1	0	26723	26709	26707	16635	6	16674	80115	200	80024	200	160048	26722	26707	1	1	80201	100	99	100	100	80000	80000	0	100	80000	0	0	80035	0	35	80035	6	0	35	39	1	1	1	5118	0	0	16	0	0	26704	0	0	6	0	80000	100	26708	26708	26708	26723	26723
80204	26722	200	0	0	0	1	0	0	41	0	0	1	0	26712	2	0	0	3	25	80100	100	80000	100	80014	500	1166596	0	0	26688	26707	26722	16650	6	16659	80115	200	80024	200	160048	26722	26707	1	1	80201	100	99	100	100	80000	80000	0	100	80000	0	39	80035	0	35	80000	6	0	35	0	1	1	1	5118	0	0	16	0	0	26704	0	0	0	2	80000	100	26723	26723	26723	26723	26708
80204	26725	200	0	0	0	1	0	0	41	0	0	1	1	26707	2	0	18	12	25	80100	100	80000	100	80014	500	1167875	0	0	26703	26722	26722	16635	6	16674	80115	200	80024	200	160048	26722	26722	1	1	80201	100	99	100	100	80000	80000	0	100	80000	0	0	80000	0	0	80000	6	1	0	39	1	1	1	5118	0	0	16	0	0	26704	0	6	6	0	80000	100	26708	26723	26708	26723	26708

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.3340

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	09	0e	0f	18	19	1e	22	3a	3f	43	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d cache miss ld (a3)	a5	ld unit uop (a6)	l1d cache writeback (a8)	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	cf	d0	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
80025	26722	200	1	0	0	0	0	71	1	0	26693	2	18	18	11	25	80010	10	80000	10	80000	50	1167605	1	26847	26730	26722	16671	3	16702	80010	20	80000	20	160000	26722	26722	1	1	80021	10	9	10	10	80000	80000	0	10	80000	39	0	80035	0	35	80035	6	1	0	39	5020	0	16	16	15	7	26719	6	6	2	80000	10	26723	26723	26723	26723	26723
80024	26722	200	0	0	0	0	0	41	1	1	26707	2	18	18	11	25	80010	10	80000	10	80000	50	1167605	0	26811	26738	26728	16667	3	16702	80010	20	80000	20	160000	26722	26708	1	1	80021	10	9	10	10	80000	80000	0	10	80000	39	0	80000	0	0	80035	0	1	35	39	5020	0	17	16	17	8	26705	6	6	2	80000	10	26723	26723	26723	26709	26723
80024	26722	201	0	0	0	0	0	41	0	1	26707	2	0	18	12	25	80010	10	80000	10	80000	50	1167605	0	26835	26737	26727	16667	3	16688	80010	20	80000	20	160000	26722	26722	1	1	80021	10	9	10	10	80000	80000	0	10	80000	39	0	80035	0	0	80000	0	1	0	39	5020	0	17	16	17	17	26719	0	6	2	80000	10	26723	26723	26709	26723	26709
80024	26722	200	0	0	0	0	0	0	1	1	26707	2	18	18	0	25	80010	10	80000	10	80000	50	1167605	0	26759	26728	26729	16681	3	16702	80010	20	80000	20	160000	26722	26708	1	1	80021	10	9	10	10	80000	80000	0	10	80000	39	0	80035	0	0	80035	0	1	36	39	5020	4	7	16	8	17	26727	6	6	2	80000	10	26709	26723	26723	26723	26723
80024	26722	200	0	0	0	0	0	41	1	1	26707	2	18	18	12	25	80010	10	80000	10	80000	50	1167605	0	26860	26773	26882	16654	3	16702	80010	20	80000	20	160000	26722	26722	1	1	80021	10	9	10	10	80000	80000	0	10	80000	39	0	80035	0	0	80035	6	1	35	39	5020	0	17	16	17	6	26719	0	6	0	80000	10	26726	26712	26723	26723	26723
80024	26726	200	0	0	0	0	0	65	1	1	26707	2	18	18	12	25	80010	10	80000	10	80000	50	1167605	0	26847	26716	26727	16667	3	16688	80010	20	80000	20	160000	26722	26722	1	1	80021	10	9	10	10	80000	80000	0	10	80000	0	0	80035	0	35	80035	0	1	35	39	5020	0	17	16	17	8	26719	0	6	2	80000	10	26709	26709	26723	26723	26723
80024	26722	200	0	0	0	0	0	86	1	1	26693	2	18	18	12	25	80010	10	80000	10	80000	50	1166750	0	26846	26732	26714	16652	3	16702	80010	20	80000	20	160000	26722	26722	1	1	80021	10	9	10	10	80000	80000	0	10	80000	39	0	80000	0	38	80035	6	1	35	39	5020	0	17	16	6	17	26719	0	6	2	80000	10	26723	26723	26709	26723	26723
80024	26722	200	0	1	1	0	0	6	1	0	26693	2	18	18	0	25	80010	10	80000	10	80000	50	1167605	1	26840	26732	26737	16652	3	16702	80010	20	80000	20	160000	26722	26722	1	1	80021	10	9	10	10	80000	80000	0	10	80000	39	0	80035	0	35	80035	6	1	35	39	5020	0	17	16	14	8	26719	6	6	2	80000	10	26709	26723	26723	26723	26723
80024	26722	200	0	0	0	0	0	41	1	1	26707	2	18	18	12	25	80010	10	80000	10	80000	50	1166750	1	26812	26734	26727	16667	3	16702	80010	20	80000	20	160000	26722	26722	1	1	80021	10	9	10	10	80000	80000	0	10	80000	39	0	80035	0	36	80035	6	1	35	39	5020	0	18	16	17	17	26719	6	0	2	80000	10	26709	26723	26723	26723	26723
80024	26722	200	0	0	0	4	0	50	1	0	26707	2	18	18	12	25	80010	10	80000	10	80000	50	1167605	0	26697	26790	26882	16808	3	16702	80010	20	80000	20	160000	26722	26722	1	1	80021	10	9	10	10	80000	80000	0	10	80000	43	0	80000	0	0	80035	6	0	35	39	5051	0	8	16	17	6	26719	6	0	2	80000	10	26709	26723	26723	26709	26709

LDR (register, uxtw, D)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->2 roundtrip

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: Latency 1->3 roundtrip

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 4: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations