Firestorm: LDR (register, uxtw, Q) measurements

Code:

  ldr q0, [x6, w7, uxtw]

Initialization

  mov x7, #4
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 1.000

SIMD/FP unit issues: 0.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	09	0e	0f	1e	22	3a	3f	43	46	49	4f	51	schedule uop (52)	schedule ldst uop (55)	dispatch ldst uop (58)	simd uops in schedulers (5a)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map ldst uop (7d)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst simd load (98)	inst ldst (9b)	9d	l1d tlb access (a0)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	ea	eb	ec	? ldst retires (ed)	f5	f6	f7	f8	fd
1005	402	2	1	1	0	61	1	1	368	17	4	19	20	25	1000	1000	1000	15411	0	376	382	402	225	3	240	1000	1000	2000	383	402	1	1	1001	1000	1000	0	1000	0	1055	0	55	1025	6	1	55	44	73	1	16	1	1	399	10	10	6	1000	383	403	384	403	403
1004	383	3	0	0	1	62	0	0	387	25	4	0	20	25	1000	1000	1000	14678	1	377	402	402	224	3	260	1000	1000	2000	402	402	1	1	1001	1000	1000	0	1000	59	1055	0	55	1055	6	1	55	44	73	1	16	1	1	400	10	10	6	1000	403	403	403	403	403
1004	402	3	0	0	1	61	0	0	387	18	4	0	20	25	1000	1000	1000	15404	0	377	402	402	224	3	260	1000	1000	2000	402	383	1	1	1001	1000	1000	0	1000	0	1055	0	55	1025	0	1	55	44	73	1	16	1	1	399	10	10	6	1000	404	403	403	403	403
1004	402	2	0	0	1	61	0	0	367	25	4	0	3	25	1000	1000	1000	15471	0	358	382	402	226	3	260	1000	1000	2000	383	402	1	1	1001	1000	1000	0	1000	59	1025	0	25	1055	6	0	55	0	73	1	16	1	1	399	0	10	0	1000	384	403	383	403	383
1004	402	2	0	0	0	60	0	0	367	25	4	0	20	25	1000	1000	1000	15471	1	377	402	405	225	3	260	1000	1000	2000	383	402	1	1	1001	1000	1000	1	1000	59	1055	0	25	1055	0	1	25	44	73	1	16	1	1	399	10	10	0	1000	403	383	403	403	403
1004	402	3	0	0	1	25	1	0	367	17	0	19	20	25	1000	1000	1000	14580	1	377	400	403	235	3	240	1000	1000	2000	402	382	1	1	1001	1000	1000	0	1000	0	1056	0	55	1025	0	1	25	0	73	1	16	1	1	399	0	10	0	1000	403	383	403	403	403
1004	402	2	0	0	1	25	1	0	367	25	0	0	21	25	1000	1000	1000	15471	1	377	402	423	225	3	260	1000	1000	2000	383	402	1	1	1001	1000	1000	0	1000	0	1055	0	55	1025	0	1	55	44	73	1	16	1	1	380	10	0	6	1000	385	403	383	403	383
1004	402	2	0	0	1	61	1	1	367	17	4	0	3	25	1000	1000	1000	15394	1	377	382	403	225	3	241	1000	1000	2000	403	382	1	1	1001	1000	1000	0	1000	0	1055	0	25	1055	6	0	55	44	73	1	16	1	1	380	0	10	0	1000	383	403	384	403	403
1004	383	3	0	0	0	61	0	0	387	25	4	0	20	25	1000	1000	1000	15411	1	377	403	405	228	3	240	1000	1000	2000	402	383	1	1	1001	1000	1000	0	1000	59	1025	0	55	1055	6	0	25	0	73	1	16	1	1	402	10	0	6	1000	403	384	403	384	403
1004	402	2	0	0	1	25	0	0	367	25	4	0	20	25	1000	1000	1000	15394	1	377	402	383	225	3	260	1000	1000	2000	402	390	1	1	1001	1000	1000	0	1000	0	1055	0	55	1025	6	0	56	44	73	1	16	1	1	379	0	10	6	1000	383	403	404	403	384

Test 2: Latency 1->2 roundtrip

Chain cycles: 3

Code:

  ldr q0, [x6, w7, uxtw]
  fmov x0, d0
  eor x8, x8, x0
  eor x8, x8, x0
  add x6, x6, x8

Initialization

  mov x7, #4
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 9.0047

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	0e	0f	18	1e	1f	22	23	3f	4d	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	69	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst ldst (9b)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	ac	af	b5	l1d cache miss ld nonspec (bf)	c2	branch mispred nonspec (cb)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
50205	120047	899	1	1	0	1	0	0	0	120020	119519	109461	25	60100	40100	10001	10000	30100	10000	10000	1079200	5736044	6133818	1	120011	0	120047	120047	113143	3	113667	50100	30200	10000	10000	60200	20000	10000	120047	120047	1	1	50201	100	99	100	40100	10000	10000	100	10000	0	1	10000	0	0	10000	1	1	0	0	3210	1	135	1	1	119646	40002	6	0	8	10000	40100	120051	120051	120048	120048	120036
50204	120047	899	0	0	0	1	0	1	0	120032	119493	109463	25	60100	40102	10001	10000	30100	10000	10000	1078999	5736044	6134461	1	120011	0	120047	120047	113143	3	113658	50100	30200	10000	10000	60200	20000	10000	120047	120047	1	1	50201	100	99	100	40100	10000	10000	100	10000	0	1	10000	0	0	10000	1	1	0	0	3210	1	107	1	1	119646	40002	6	6	5	10000	40100	120048	120048	120036	120048	120048
50204	120047	899	0	0	0	117	0	1	0	120035	119519	109462	25	60103	40102	10000	10000	30100	10000	10000	1079200	5736188	6133818	1	120028	3	120049	120049	113141	3	113640	50100	30200	10000	10000	60200	20000	10000	120035	120047	1	1	50201	100	99	100	40100	10000	10000	100	10000	0	1	10000	0	0	10000	1	1	0	0	3210	1	101	1	1	119660	40002	9	6	5	10000	40100	120036	120048	120048	120048	120051
50204	120050	899	0	0	0	0	0	0	0	120032	119509	109449	25	60103	40102	10001	10000	30100	10000	10000	1078862	5735455	6133818	1	120026	0	120035	120047	113143	3	113667	50100	30200	10000	10000	60200	20000	10000	120050	120035	1	1	50201	100	99	100	40100	10000	10000	100	10000	0	0	10000	0	0	10000	1	1	0	0	3210	1	101	2	2	119822	40002	6	6	8	10000	40100	120036	120036	120048	120048	120048
50204	120050	899	1	1	0	1	0	0	0	120020	119519	109512	25	60103	40100	10000	10000	30100	10000	10000	1078862	5736044	6134461	1	120026	0	120047	120047	113145	3	113658	50100	30200	10000	10000	60200	20000	10000	120035	120047	1	1	50201	100	99	100	40100	10000	10000	100	10000	0	1	10000	0	0	10000	1	0	0	0	3210	1	135	1	1	119646	40002	6	0	5	10000	40100	120036	120051	120051	120048	120048
50204	120047	899	0	0	0	6	0	1	0	120035	119493	109461	25	60103	40100	10001	10000	30100	10000	10000	1079200	5736044	6133818	1	120023	0	120035	120050	113143	3	113658	50100	30200	10000	10000	60200	20000	10000	120050	120047	1	1	50201	100	99	100	40100	10000	10000	100	10000	0	1	10000	1	0	10002	1	1	0	0	3210	1	135	1	1	119660	40000	0	0	0	10000	40100	120048	120036	120048	120036	120036
50204	120050	899	0	0	0	1	0	0	1	120032	119519	109461	25	60103	40102	10001	10000	30100	10000	10000	1078999	5736188	6134461	1	120011	0	120035	120047	113143	3	113636	50100	30200	10000	10000	60200	20000	10000	120047	120047	1	1	50202	100	99	100	40100	10000	10000	100	10000	0	1	10000	0	0	10000	1	1	0	0	3210	1	17	1	1	119660	40000	9	0	5	10000	40100	120048	120036	120051	120048	120036
50204	120047	900	0	0	0	1	0	0	1	120032	119519	109449	25	60103	40102	10000	10000	30100	10000	10000	1078862	5736044	6133818	1	120023	0	120047	120047	113143	3	113636	50100	30200	10000	10000	60200	20000	10000	120050	120047	1	1	50201	100	99	100	40100	10000	10000	100	10000	0	1	10000	0	0	10000	1	1	0	0	3210	1	135	1	1	119660	40002	0	0	0	10000	40100	120048	120036	120048	120048	120048
50204	120035	899	0	0	0	9	0	0	0	120032	119493	109449	25	60103	40102	10001	10000	30100	10000	10000	1079200	5735455	6133818	1	120011	0	120035	120047	113141	3	113636	50100	30200	10000	10000	60200	20000	10000	120035	120076	1	1	50201	100	99	100	40100	10000	10000	100	10000	0	0	10000	0	0	10000	1	1	0	0	3210	1	101	1	1	119646	40002	6	0	0	10000	40100	120052	120036	120098	120101	120036
50204	120047	899	1	1	0	0	0	0	0	120020	119493	109461	25	60100	40100	10001	10000	30100	10000	10000	1078862	5735455	6133818	1	120011	0	120047	120035	113141	3	113636	50100	30200	10000	10065	60200	20000	10000	120054	120047	1	1	50201	100	99	100	40100	10000	10000	100	10000	0	1	10000	0	0	10000	1	1	0	0	3210	1	107	1	1	119660	40002	6	6	0	10000	40100	120036	120036	120051	120048	120048

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 9.0051

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	0e	0f	1e	1f	22	24	3f	4d	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	61	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	ac	af	b5	l1d cache miss ld nonspec (bf)	c2	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
50025	120051	899	1	1	1	0	1	0	120036	119509	109464	25	60013	40012	10000	10000	30010	10000	10000	1079517	5736236	6133662	0	0	120027	120051	120035	113153	3	113690	50010	30020	10000	10000	60020	20000	10066	120035	120035	1	1	50021	10	9	10	40010	10000	10000	0	10	10000	0	10000	0	0	10000	1	1	0	0	0	3140	1	107	1	1	119666	40002	10	0	9	10000	40010	120052	120052	120052	120052	120052
50024	120051	899	0	1	0	0	0	0	120036	119509	109449	25	60010	40012	10001	10000	30010	10000	10000	1079517	5735455	6132757	1	0	120027	120051	120051	113169	3	113690	50010	30020	10000	10000	60020	20000	10000	120051	120051	1	1	50021	10	9	10	40010	10000	10000	0	10	10000	1	10000	0	0	10000	0	0	0	0	0	3140	1	107	1	1	119666	40002	10	10	9	10000	40010	120052	120052	120036	120052	120052
50024	120051	899	0	1	0	0	1	0	120036	119499	109464	46	60010	40012	10001	10000	30010	10000	10000	1079517	5736236	6133662	0	0	120011	120051	120051	113169	3	113690	50010	30020	10000	10000	60020	20000	10000	120051	120051	1	1	50021	10	9	10	40010	10000	10000	0	10	10000	1	10000	0	0	10000	1	1	0	0	0	3140	1	107	1	1	119650	40002	10	10	9	10000	40010	120052	120052	120052	120052	120052
50024	120051	899	0	0	1	0	1	0	120020	119509	109464	25	60010	40012	10001	10000	30010	10000	10000	1079557	5736236	6133662	0	0	120027	120051	120035	113169	3	113701	50010	30020	10000	10000	60020	20000	10000	120051	120051	1	1	50021	10	9	10	40010	10000	10000	0	10	10000	1	10000	0	0	10000	1	1	0	0	0	3140	1	107	1	1	119650	40000	0	10	9	10000	40010	120052	120052	120052	120052	120036
50024	120035	899	0	1	1	0	1	0	120036	119509	109449	25	60010	40012	10001	10000	30010	10000	10000	1079517	5736236	6133662	0	0	120011	120054	120035	113153	3	113690	50010	30020	10000	10000	60020	20000	10000	120035	120051	1	1	50021	10	9	10	40010	10000	10000	0	10	10000	1	10000	1	0	10000	1	1	2	0	0	3140	1	107	1	1	119666	40000	0	0	9	10000	40010	120052	120052	120036	120036	120036
50024	120035	899	0	1	1	0	0	0	120036	119565	109449	25	60013	40012	10001	10000	30010	10000	10000	1079557	5736236	6133662	0	0	120027	120051	120035	113153	3	113690	50010	30020	10000	10000	60020	20000	10000	120037	120054	1	1	50021	10	9	10	40010	10000	10000	0	10	10000	1	10000	0	0	10000	1	1	0	0	0	3140	1	107	1	1	119666	40002	0	0	0	10000	40010	120052	120052	120052	120036	120036
50024	120035	899	0	1	0	0	0	0	120036	119492	109467	25	60013	40010	10001	10000	30010	10000	10000	1079517	5736236	6133662	0	0	120011	120051	120051	113169	3	113690	50010	30020	10000	10000	60020	20000	10000	120051	120051	1	1	50021	10	9	10	40010	10000	10000	0	10	10000	1	10000	0	0	10000	1	0	0	0	0	3140	1	107	1	1	119650	40000	10	10	0	10000	40010	120052	120036	120052	120052	120036
50024	120051	899	0	1	1	0	0	0	120020	119492	109464	25	60010	40010	10001	10000	30010	10000	10000	1079584	5736236	6132757	0	0	120011	120035	120076	113169	3	113674	50010	30020	10000	10000	60020	20000	10000	120051	120051	1	1	50021	10	9	10	40010	10000	10000	0	10	10000	0	10000	0	0	10000	1	0	0	0	0	3140	1	107	1	1	119650	40002	0	10	9	10000	40010	120036	120052	120036	120052	120052
50024	120051	899	0	1	0	0	1	0	120036	119509	109449	25	60013	40012	10001	10000	30010	10000	10000	1079557	5736236	6133662	0	0	120011	120051	120051	113169	3	113674	50010	30020	10000	10000	60020	20000	10000	120051	120051	1	1	50021	10	9	10	40010	10000	10000	0	10	10000	1	10000	0	0	10000	1	0	0	0	0	3140	1	107	1	1	119650	40000	10	10	9	10000	40010	120052	120052	120052	120052	120036
50024	120035	899	0	1	1	0	0	0	120036	119509	109464	25	60013	40010	10001	10000	30010	10000	10000	1079557	5736236	6133662	0	0	120027	120051	120035	113169	3	113690	50010	30020	10000	10000	60020	20000	10000	120051	120035	1	1	50021	10	9	10	40010	10000	10000	0	10	10000	0	10000	0	0	10000	1	1	0	0	0	3140	1	107	1	1	119666	40002	0	10	0	10000	40010	120036	120054	120036	120054	120052

Test 3: Latency 1->3 roundtrip

Chain cycles: 3

Code:

  ldr q0, [x6, w7, uxtw]
  fmov x0, d0
  eor x8, x8, x0
  eor x8, x8, x0
  add x7, x7, x8

Initialization

  mov x7, #4
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 9.0050

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	09	0e	0f	1e	1f	22	23	3a	3f	4d	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	int prf full (71)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	af	b5	l1d cache miss ld nonspec (bf)	c2	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
50205	120050	899	0	0	0	1	0	1	0	0	120035	119520	109468	25	60103	40100	10000	10000	30100	10000	10000	1078999	5736188	6133818	1	120011	120050	120050	113145	0	3	113658	50100	30200	10000	10000	60200	20000	10000	120050	120047	1	1	50201	100	99	100	40100	10000	10000	0	100	10000	0	1	10000	0	0	0	10000	1	1	0	0	2	0	3210	1	107	1	1	119657	40000	9	6	8	10000	40100	120048	120111	120059	120049	120051
50204	120035	899	0	0	0	0	0	0	0	0	120035	119520	109463	25	60103	40100	10001	10000	30100	10000	10000	1078999	5736188	6133818	0	120023	120050	120050	113145	0	3	113667	50100	30200	10000	10000	60200	20000	10000	120050	120047	1	1	50201	100	99	100	40100	10000	10000	0	100	10000	0	1	10000	0	0	0	10000	1	1	0	0	0	0	3210	1	101	1	1	119657	40002	9	9	0	10000	40100	120048	120036	120048	120036	120051
50204	120047	899	0	0	0	1	0	0	0	0	120035	119547	109449	25	60100	40102	10000	10000	30100	10000	10000	1079200	5735455	6133818	0	120026	120035	120035	113145	0	3	113667	50100	30200	10000	10000	60200	20000	10000	120035	120047	1	1	50201	100	99	100	40100	10000	10000	0	100	10000	0	0	10000	0	0	0	10000	1	1	0	0	0	0	3210	1	107	1	1	119657	40002	9	6	8	10000	40100	120048	120106	120052	120049	120051
50204	120050	899	0	0	0	0	0	0	0	0	120032	119524	109463	25	60103	40102	10001	10000	30100	10000	10000	1078999	5736044	6133818	1	120011	120035	120035	113145	0	3	113667	50100	30200	10000	10000	60200	20000	10000	120035	120047	1	1	50201	100	99	100	40100	10000	10000	0	100	10000	0	1	10000	0	0	0	10000	1	1	0	0	0	0	3210	1	107	1	1	119646	40000	9	9	0	10000	40100	120048	120083	120071	120037	120096
50204	120050	899	0	0	0	1	0	0	0	0	120020	119521	109463	25	60103	40100	10001	10000	30100	10000	10000	1078999	5736188	6136166	0	120026	120035	120035	113145	0	3	113667	50100	30200	10000	10000	60200	20000	10000	120047	120035	1	1	50201	100	99	100	40100	10000	10000	0	100	10000	0	0	10000	1	0	0	10000	1	1	4	0	0	0	3210	1	101	1	1	119660	40000	6	6	5	10000	40100	120080	120080	120048	120048	120039
50204	120038	899	0	0	0	10	0	0	1	0	120035	119520	109463	25	60103	40102	10000	10000	30100	10000	10000	1078862	5736044	6133818	0	120011	120047	120035	113141	0	3	113667	50100	30200	10000	10000	60200	20000	10000	120047	120047	1	1	50201	100	99	100	40100	10000	10000	0	100	10000	0	1	10000	0	0	0	10000	1	1	0	0	0	0	3210	1	107	1	1	119660	40002	9	6	5	10000	40100	120048	120126	120082	120056	120048
50204	120050	899	0	0	0	1	0	0	0	0	120035	119537	109463	25	60103	40125	10000	10000	30100	10000	10000	1078862	5736188	6133818	0	120011	120050	120050	113145	0	3	113667	50100	30200	10000	10000	60200	20000	10000	120047	120047	1	1	50201	100	99	100	40100	10000	10000	0	100	10000	0	0	10000	0	0	0	10000	0	1	0	0	0	0	3210	1	101	1	1	119646	40002	9	0	5	10000	40100	120048	120102	120103	120063	120051
50204	120035	899	0	0	0	1	0	0	1	0	120035	119531	109461	25	60100	40102	10001	10000	30100	10000	10000	1081736	5738540	6133870	0	120011	120050	120035	113141	0	3	113658	50100	30200	10000	10000	60200	20000	10000	120035	120047	1	1	50201	100	99	100	40100	10000	10000	0	100	10000	0	1	10000	0	0	0	10000	1	1	0	0	0	0	3210	1	107	2	1	119646	40002	9	9	8	10000	40100	120048	120094	120075	120053	120051
50204	120047	899	0	0	0	1	0	0	1	2	122284	120728	110288	710	60439	40335	10050	10050	33521	11319	11232	1135017	5795615	6194956	0	121858	122475	122376	113883	0	310	114934	56423	34239	11333	11399	61814	22568	11352	122346	122399	26	1	50201	100	99	100	40100	10000	10000	0	100	10003	3	0	10001	1	2	78235	10023	1	1	4	0	0	0	3836	13	282	12	15	121448	40228	9	6	8	10000	40100	123597	123305	123815	123190	122992
50204	123460	957	0	1	1	3172	1584	0	1	2	123356	121396	110548	1066	60514	40448	10057	10074	34510	11523	11827	1160337	5804691	6218443	0	122567	123013	123619	113143	0	140	115020	57636	35802	11799	11940	69908	20000	10300	120872	120414	41	1	50201	100	99	100	40100	10000	10000	0	100	10000	0	0	10000	1	0	3	10000	1	1	0	0	0	1	3210	2	107	1	1	119832	40002	0	9	8	10000	40100	120048	120126	120050	120048	120051

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 9.0047

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	l2 tlb miss data (0b)	0e	0f	18	19	1e	22	23	3a	3f	4d	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	61	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	b5	l1d cache miss ld nonspec (bf)	branch cond mispred nonspec (c5)	cf	d0	d5	map dispatch bubble (d6)	dd	fetch restart (de)	df	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
50025	120053	899	0	0	0	1	0	0	1	1	0	1	120032	119505	109461	25	60013	40012	10001	10008	30010	10000	10000	1079523	5736044	6133499	0	0	120023	120047	120035	113165	24	113686	50010	30020	10000	10000	60020	20000	10000	120047	120047	1	1	50021	10	9	10	40010	10000	10000	0	10	10000	0	1	10001	0	55	0	0	10000	1	1	0	3148	6	1	107	1	1	8	119663	40002	6	6	5	10000	40010	120048	120048	120048	120048	120060
50024	120035	899	0	0	1	0	0	0	0	0	0	1	120032	119505	109461	25	60010	40012	10001	10000	30010	10000	10000	1079523	5736044	6132757	0	0	120023	120035	120047	113166	3	113686	50010	30667	10000	10000	60020	20000	10000	120047	120035	1	1	50021	10	9	10	40010	10000	10000	0	10	10000	0	1	10000	0	43	0	3	10000	0	0	0	3148	6	2	107	1	1	8	119662	40034	6	6	5	10000	40010	120048	120048	120036	120036	120154
50024	120052	899	0	0	0	0	0	0	1	1	0	1	120032	119492	109461	25	60010	40012	10001	10000	30010	10211	10000	1079523	5735455	6133499	0	0	120023	120047	120047	113153	3	113887	50010	30020	10000	10000	60020	20000	10000	120048	120047	1	1	50021	10	9	10	40010	10000	10000	0	10	10000	0	1	10000	0	36	0	12	10000	1	1	0	3148	6	1	107	1	1	8	119666	40002	6	6	5	10000	40010	120049	120048	120051	120048	120059
50024	120035	899	0	0	0	0	0	0	28	0	0	1	120032	119604	109492	80	60013	40012	10011	10004	30010	10368	10000	1080937	5740711	6136538	0	0	120023	120035	120047	113153	3	113686	50010	30020	10000	10000	60020	20000	10000	120050	120419	1	1	50021	10	9	10	40010	10000	10000	0	10	10000	0	1	10000	0	8	0	0	10000	1	1	0	3148	6	1	107	1	1	8	119650	40002	0	6	5	10000	40010	120048	120429	120036	120048	120050
50024	120047	899	0	1	0	0	4	0	13	0	0	1	120415	119551	109464	25	60013	40012	10001	10000	30010	10052	10049	1081696	5737596	6133499	0	0	120173	120047	120047	113165	3	113686	50010	30020	10000	10000	60020	20000	10000	120047	120047	1	1	50021	10	9	10	40010	10000	10000	0	10	10000	0	0	10000	0	39	0	0	10000	1	1	0	3148	6	1	107	1	1	8	119663	40002	6	6	5	10000	40010	120048	120048	120048	120048	120054
50024	120047	899	0	0	0	0	0	0	13	0	0	1	120020	119505	109463	25	60013	40012	10001	10000	30010	10000	10197	1079523	5736044	6139825	0	0	120023	120047	120047	113153	3	113686	50010	30020	10000	10000	60020	20000	10000	120297	120035	1	1	50021	10	9	10	40010	10000	10000	0	10	10000	0	1	10000	0	3	0	0	10000	1	0	0	3148	6	1	107	1	1	8	119662	40000	6	6	5	10000	40010	120048	120048	120048	120048	120070
50024	120050	899	0	0	0	0	0	0	0	1	0	1	120032	119505	109461	25	60013	40012	10000	10000	30010	10000	10000	1079523	5736113	6133756	0	0	120023	120047	120035	113153	3	113686	50010	30020	10000	10000	60020	20000	10000	120047	120047	1	1	50021	10	9	10	40010	10000	10000	0	10	10000	0	0	10000	0	66	0	0	10000	1	0	0	3148	6	1	107	1	1	8	119662	40002	6	0	5	10000	40010	120048	120048	120036	120048	120076
50024	120047	899	0	0	0	0	0	0	1	1	0	1	120032	119492	109461	25	60013	40012	10001	10000	30163	10000	10049	1079568	5741234	6133499	0	0	120023	120047	120035	113165	3	113686	50010	30020	10000	10000	60020	20000	10000	120047	120050	5	1	50021	10	9	10	40010	10000	10000	0	10	10000	0	1	10000	0	39	0	0	10000	1	1	0	3148	6	1	107	1	1	8	119650	40002	6	6	0	10000	40010	120048	120036	120036	120048	120095
50024	120047	902	0	0	0	0	0	0	1	1	0	1	120032	119505	109452	25	60024	40010	10001	10000	30010	10000	10000	1088727	5736188	6133499	0	0	120023	120035	120047	113287	3	113686	50010	30020	10000	10000	60020	20000	10000	120047	120047	1	1	50021	10	9	10	40010	10000	10000	0	10	10000	2	1	10000	1	19	0	14326	10000	1	1	0	3148	6	1	107	1	1	8	119664	40002	6	6	5	10000	40010	120048	120048	120049	120058	120075
50024	120047	899	0	0	0	0	0	4	1	0	0	2	120032	119552	109461	25	60013	40012	10001	10000	30010	10000	10000	1079523	5736044	6133499	0	0	120023	120036	120047	113153	3	113686	50010	30020	10000	10000	60020	20000	10000	120035	120047	5	1	50021	10	9	10	40010	10000	10000	1	10	10000	4	0	10000	0	0	0	0	10000	1	1	0	3148	6	1	107	1	1	8	119664	40002	0	6	0	10000	40010	120048	120048	120036	120048	120096

Test 4: throughput

Count: 8

Code:

  ldr q0, [x6, w7, uxtw]
  ldr q0, [x6, w7, uxtw]
  ldr q0, [x6, w7, uxtw]
  ldr q0, [x6, w7, uxtw]
  ldr q0, [x6, w7, uxtw]
  ldr q0, [x6, w7, uxtw]
  ldr q0, [x6, w7, uxtw]
  ldr q0, [x6, w7, uxtw]

Initialization

  mov x7, 8

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.3340

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	09	0e	0f	18	1e	1f	22	23	3a	3f	43	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
80205	26723	200	0	1	1	1	0	0	0	1	0	2	26727	2	18	12	16	25	80100	100	80000	100	80015	500	1167875	1	26682	26727	26727	16650	6	16674	80114	200	80024	200	160048	26722	26707	1	1	80201	100	99	100	100	80000	80000	1	100	80000	39	80000	0	39	80000	6	1	0	39	1	1	1	5118	16	1	0	26734	0	10	6	4	80000	100	26728	26708	26728	26708	26728
80204	26727	200	0	0	0	0	0	0	0	0	0	1	26707	2	12	12	16	25	80100	100	80000	100	80015	500	1167547	1	26701	26727	26727	16674	6	16659	80115	200	80024	200	160048	26727	26722	1	1	80201	100	99	100	100	80000	80000	1	100	80000	43	80035	1	42	80039	6	1	0	0	1	1	1	5118	16	0	0	26704	0	0	10	4	80000	100	26731	26732	26708	26708	26728
80204	26728	200	1	0	0	0	0	198	0	1	0	2	26726	2	18	12	16	25	80230	100	80000	100	80020	500	1167203	1	26682	26727	26727	16655	6	16679	80115	200	80024	200	160048	26707	26707	1	1	80201	100	99	100	100	80000	80000	0	100	80000	0	80039	2	0	80000	6	0	0	0	1	1	1	5118	16	0	0	26725	0	10	6	4	80000	100	26718	26723	26708	26732	26723
80204	27032	201	0	0	0	0	1	41	0	0	0	1	26710	2	18	0	16	25	80100	100	80000	100	80016	500	1167075	1	26702	26707	26727	16659	6	16659	80114	200	80024	200	160048	26722	26711	1	1	80201	100	99	100	100	80000	80000	0	100	80000	39	80000	0	39	80039	0	1	0	39	1	1	1	5118	16	0	0	26724	0	0	10	4	80000	100	26728	26728	26736	26731	26728
80204	26707	214	0	0	1	0	0	57	0	0	0	2	26716	0	18	12	0	25	80100	100	80000	100	80014	500	1166596	1	26702	26727	26722	16635	6	16659	80115	200	80024	200	160048	26726	26726	1	1	80201	100	99	100	100	80000	80000	0	100	80000	0	80035	0	0	80039	6	0	0	43	1	1	1	5118	16	1	0	26764	0	10	0	2	80000	100	26712	27006	27330	26708	27027
80204	26707	202	0	0	1	1	1	0	192	0	0	2	26692	2	0	0	16	25	80100	100	80000	100	80016	500	1167303	1	26686	26707	26727	16655	6	16683	80116	200	80024	200	160048	26727	26722	1	1	80201	100	99	100	100	80000	80000	0	100	80000	39	80035	1	42	80000	6	1	35	0	1	1	1	5118	16	1	0	26788	0	4	10	2	80000	100	26708	26708	26728	26708	26728
80204	26731	200	0	0	0	0	0	45	0	1	0	2	26723	2	0	0	2	25	80100	100	80000	100	80015	500	1167303	1	26702	26707	26707	16655	6	16659	80115	200	80024	200	160048	26727	26707	1	1	80201	100	99	100	100	80000	80000	0	100	80000	39	80000	0	39	80000	0	0	0	43	1	1	1	5118	16	0	0	26872	0	0	10	4	80000	100	26723	26732	26727	26712	26714
80204	26739	200	0	0	0	0	0	0	0	0	0	2	26716	0	12	18	12	25	80100	100	80000	100	80015	500	1167303	1	26702	26722	26722	16655	6	16674	80115	200	80024	200	160048	26727	26722	1	1	80201	100	99	100	100	80000	80000	0	100	80000	39	80035	0	35	80039	0	1	35	39	1	1	1	5118	16	0	0	26933	0	0	10	2	80000	100	26708	26708	26728	26723	26732
80204	26722	200	0	0	0	0	0	45	0	0	0	1	26707	0	0	12	0	25	80100	100	80000	100	80015	500	1166888	1	26702	26727	26727	16635	6	16659	80114	200	80024	200	160048	26727	26722	1	1	80201	100	99	100	100	80000	80000	0	100	80000	39	80000	0	35	80035	0	1	35	0	1	1	1	5118	16	0	0	26748	0	0	10	4	80000	100	26728	26708	26728	26728	26728
80204	26727	200	0	1	0	0	0	0	0	0	0	0	26707	2	12	12	16	25	80100	100	80000	100	80015	500	1167875	1	26702	26727	26727	16635	6	16674	80116	200	80024	200	160048	26727	26722	1	1	80201	100	99	100	100	80000	80000	0	100	80000	0	80040	0	35	80039	6	1	0	43	1	1	1	5118	16	0	0	26830	0	6	6	4	80000	100	26728	26708	26723	26728	26708

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.3341

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	0e	0f	1e	22	23	3a	3f	43	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d cache miss ld (a3)	a5	ld unit uop (a6)	l1d cache writeback (a8)	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	branch cond mispred nonspec (c5)	cf	d5	map dispatch bubble (d6)	db	dd	fetch restart (de)	e0	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
80025	26727	200	1	0	0	1	0	1	26712	2	1	12	16	25	80010	10	80000	10	80000	50	1166750	0	26683	26708	26728	16676	3	16711	80010	20	80000	20	160000	26731	26708	1	1	80021	10	9	10	10	80000	80000	0	10	80000	43	0	80039	0	38	80038	6	1	39	44	0	5020	9	16	0	26	7	26790	0	10	7	80000	10	26709	26732	26732	26732	26732
80024	26731	200	0	0	44	1	0	1	26716	0	1	1	19	25	80010	10	80000	10	80000	50	1167501	0	26706	26731	26708	16676	3	16711	80010	20	80000	20	160000	26731	26708	1	1	80021	10	9	10	10	80000	80000	0	10	80000	43	0	80038	0	38	80000	6	0	39	0	0	5020	7	16	0	21	7	26728	14	0	7	80000	10	26729	26709	26729	26728	26732
80024	26727	200	0	0	0	1	0	1	26716	2	0	0	0	25	80010	10	80000	10	80000	50	1167124	0	26683	26731	26708	16678	3	16707	80010	20	80000	20	160000	26728	26728	1	1	80021	10	9	10	10	80000	80000	1	10	80000	43	0	80039	0	39	80000	6	1	0	0	0	5020	11	16	0	9	11	26743	14	10	7	80000	10	26732	26732	26709	26732	26732
80024	26731	200	0	0	44	0	0	1	26716	3	0	1	16	25	80010	10	80000	10	80000	50	1166750	0	26706	26708	26708	16652	3	16688	80010	20	80000	20	160000	26727	26731	1	1	80021	10	9	10	10	80000	80000	0	10	80000	43	0	80039	0	218	80039	6	1	39	0	0	5020	11	16	0	10	11	26728	14	10	7	80000	10	26732	26709	26728	26732	26732
80024	26731	200	0	0	44	1	0	1	26716	0	0	0	0	25	80010	10	80000	10	80000	50	1166750	0	26683	26731	26731	16676	3	16711	80010	20	80000	20	160000	26731	26708	1	1	80021	10	9	10	10	80000	80000	0	10	80000	43	0	80038	0	38	80039	6	0	39	0	0	5020	11	16	0	11	11	26835	0	14	0	80000	10	26732	26732	26709	26728	26728
80024	26731	200	0	0	0	0	0	0	26693	0	1	0	19	25	80010	10	80000	10	80000	50	1167124	0	26706	26728	26728	16672	3	16711	80010	20	80000	20	160000	26731	26728	1	1	80021	10	9	10	10	80000	80000	0	10	80000	0	0	80000	0	39	80038	6	1	39	0	0	5020	11	16	0	24	7	26894	14	14	7	80000	10	26732	26732	26709	26732	26732
80024	26708	200	0	0	44	0	0	1	26716	0	12	0	0	25	80010	10	80000	10	80000	50	1167124	0	26706	26708	26731	16652	3	16711	80010	20	80000	20	160000	26806	26768	1	1	80021	10	9	10	10	80000	80000	0	10	80000	0	0	80038	0	0	80000	6	1	39	44	0	5020	7	16	0	25	11	26846	0	0	7	80000	10	26729	26732	26732	26709	26728
80024	26731	200	0	0	45	1	0	1	26716	0	1	1	19	25	80010	10	80000	10	80000	50	1167201	0	26706	26708	26731	16676	3	16711	80010	20	80000	20	160000	26731	26728	1	1	80021	10	9	10	10	80000	80000	0	10	80000	0	0	80038	0	0	80039	6	1	39	0	0	5020	11	16	0	17	11	26737	14	14	7	80000	10	26732	26728	26732	26709	26709
80024	26727	200	0	0	44	0	0	1	26716	0	0	1	0	25	80010	10	80000	10	80000	50	1168843	0	26683	26708	26731	16652	3	16711	80010	20	80000	20	160000	26731	26708	1	1	80021	10	9	10	10	80000	80000	0	10	80000	43	0	80000	16	0	80000	6	1	0	0	0	5020	7	16	0	21	11	26712	14	10	7	80000	10	26728	26709	26709	26732	26732
80025	26731	200	1	1	45	1	0	1	26712	0	1	12	16	25	80010	10	80000	10	80000	50	1167117	0	26706	26708	26727	16676	3	16688	80010	20	80000	20	160000	26731	26727	1	1	80021	10	9	10	10	80000	80000	0	10	80000	43	0	80038	0	38	80038	0	0	39	44	0	5020	7	16	0	19	6	26842	10	10	4	80000	10	26728	26729	26709	26729	26709

LDR (register, uxtw, Q)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->2 roundtrip

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: Latency 1->3 roundtrip

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 4: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations