Firestorm: LDR (register, uxtw, S) measurements

Code:

  ldr s0, [x6, w7, uxtw]

Initialization

  mov x7, #4
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 1.000

SIMD/FP unit issues: 0.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk instruction (07)	mmu table walk data (08)	09	l2 tlb miss data (0b)	0e	0f	1e	22	3a	3f	43	46	49	4f	51	schedule uop (52)	schedule ldst uop (55)	dispatch ldst uop (58)	simd uops in schedulers (5a)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map ldst uop (7d)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst simd load (98)	inst ldst (9b)	9d	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	st unit uop (a7)	a9	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	ea	eb	ec	? ldst retires (ed)	f5	f6	f7	f8	fd
1005	399	3	1	0	1	0	1	0	1	66	1	2	379	2	12	18	12	25	1000	1000	1000	14989	1	364	394	394	217	3	252	1000	1000	2000	394	389	1	1	1001	1000	1000	0	1000	0	39	1035	0	0	35	1035	6	1	35	39	0	0	75	1	16	1	1	391	10	7	4	1000	392	392	392	395	392
1004	394	3	0	1	0	0	0	0	0	45	0	0	379	2	12	18	16	25	1000	1000	1000	14989	0	369	389	394	212	3	252	1000	1000	2000	399	399	1	1	1001	1000	1000	0	1020	19	42	1058	1	1	59	1038	6	1	57	42	19	0	73	1	16	1	1	391	10	6	4	1000	395	398	395	395	395
1004	394	3	0	0	0	0	0	0	0	45	0	2	379	2	12	18	16	25	1000	1000	1000	15018	1	364	389	394	212	3	252	1000	1000	2000	394	389	1	1	1001	1000	1000	0	1000	0	39	1035	0	0	35	1039	6	1	35	39	0	0	75	1	16	1	1	391	10	6	4	1000	395	395	395	395	395
1004	394	2	0	0	0	0	0	0	0	45	0	2	379	3	12	12	16	25	1000	1000	1000	14838	0	364	394	394	217	3	252	1000	1000	2000	399	398	1	1	1001	1000	1000	1	1021	20	42	1058	0	1	59	1038	6	1	57	42	19	0	75	1	16	1	1	391	10	6	4	1000	395	395	395	395	390
1004	394	2	0	0	0	0	0	0	0	45	0	2	384	2	18	18	15	25	1000	1000	1000	15434	1	374	399	398	222	3	257	1000	1000	2000	394	389	1	1	1001	1000	1000	0	1000	0	39	1039	0	0	39	1039	6	1	35	43	0	0	75	1	16	1	1	391	10	6	7	1000	395	395	390	392	395
1004	394	3	0	1	0	0	0	0	0	41	1	2	379	3	18	18	16	25	1000	1000	1000	15054	1	364	389	394	217	3	252	1000	1000	2000	399	398	1	1	1001	1000	1000	0	1019	19	42	1062	0	1	71	1037	6	1	57	42	19	0	75	1	16	1	1	386	10	6	4	1000	395	395	390	395	395
1004	394	3	0	1	0	0	0	0	0	45	0	3	383	2	18	18	16	25	1000	1000	1000	15362	1	373	399	398	221	3	257	1000	1000	2000	394	389	1	1	1001	1000	1000	0	1000	0	39	1035	0	0	35	1039	6	1	35	43	0	0	75	1	16	1	1	396	9	9	2	1000	400	399	400	399	400
1004	399	3	1	0	0	1	0	0	0	65	0	2	384	2	18	18	17	25	1000	1000	1000	15334	0	374	399	399	222	3	256	1000	1000	2000	394	389	1	1	1001	1000	1000	0	1000	0	39	1038	0	0	39	1035	6	1	35	43	0	0	73	1	16	1	1	386	10	7	4	1000	390	395	395	395	390
1004	394	2	0	0	0	0	0	0	0	45	0	2	379	2	12	12	16	25	1000	1000	1000	14989	0	369	394	394	216	3	247	1000	1000	2000	399	399	1	1	1001	1000	1000	0	1019	19	42	1058	0	1	59	1038	6	1	57	42	19	0	75	1	16	1	1	388	10	6	4	1000	395	390	390	390	395
1004	394	3	0	0	0	0	0	0	0	45	0	2	379	2	12	12	11	25	1000	1000	1000	14989	0	369	394	394	217	3	247	1000	1000	2000	391	389	1	1	1001	1000	1000	0	1000	0	39	1039	0	0	39	1039	6	1	35	39	0	0	75	1	16	1	1	396	9	9	2	1000	400	400	400	400	401

Test 2: Latency 1->2 roundtrip

Chain cycles: 3

Code:

  ldr s0, [x6, w7, uxtw]
  fmov x0, d0
  eor x8, x8, x0
  eor x8, x8, x0
  add x6, x6, x8

Initialization

  mov x7, #4
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 9.0050

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	09	0e	0f	1e	22	23	3f	4d	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	69	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	af	b5	bb	l1d cache miss ld nonspec (bf)	branch mispred nonspec (cb)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
50205	120047	899	1	1	1	7	1	0	120083	119509	109527	25	60100	40102	10001	10000	30100	10000	10000	1079200	5736188	6136166	0	120034	0	120050	120047	113145	3	113658	50100	30200	10000	10000	60200	20000	10000	120055	120047	1	1	50201	100	99	100	40100	10000	10000	0	100	10000	1	10000	0	0	0	10000	1	0	1	0	3210	3	107	1	2	119660	40000	9	6	8	10000	40100	120036	120051	120036	120051	120036
50204	120050	899	0	0	0	1	0	0	120032	119493	109449	25	60103	40102	10001	10000	30100	10000	10000	1078999	5736044	6133818	0	120023	0	120047	120047	113145	3	113636	50100	30200	10000	10000	60200	20000	10000	120050	120047	1	1	50201	100	99	100	40100	10000	10000	0	100	10000	1	10000	0	0	0	10000	0	0	1	0	3210	2	101	1	2	119657	40000	0	6	8	10000	40100	120051	120051	120036	120051	120051
50204	120050	899	0	0	0	1	0	0	120035	119509	109463	25	60103	40102	10001	10000	30100	10000	10000	1078999	5736188	6133818	0	120043	0	120047	120035	113150	3	113658	50100	30200	10000	10000	60200	20000	10000	120050	120047	1	1	50201	100	99	100	40100	10000	10000	0	100	10000	0	10000	0	0	15	10000	1	0	1	0	3210	2	135	1	2	119657	40002	0	6	5	10000	40100	120048	120036	120051	120051	120036
50204	120050	899	0	0	0	0	0	0	120020	119493	109463	25	60103	40102	10001	10000	30100	10000	10000	1078862	5736188	6133818	0	120012	0	120047	120035	113183	3	113658	50100	30200	10000	10000	60200	20000	10000	120050	120047	1	1	50201	100	99	100	40100	10000	10000	0	100	10000	1	10000	0	0	0	10000	1	0	0	0	3210	2	101	1	2	119660	40002	6	6	0	10000	40100	120051	120036	120051	120051	120051
50204	120050	899	0	0	0	1	1	0	120032	119509	109463	25	60103	40102	10001	10000	30100	10000	10000	1078862	5735455	6133818	0	120298	0	120050	120035	113141	3	113658	50100	30200	10000	10000	60200	20000	10000	120050	120035	1	1	50201	100	99	100	40100	10000	10000	0	100	10000	1	10000	0	0	0	10000	1	0	1	0	3210	1	135	1	2	119657	40004	9	0	8	10000	40100	120051	120036	120036	120036	120051
50204	120050	899	0	0	0	12	0	0	120020	119493	109449	25	60103	40102	10000	10000	30100	10062	10000	1079209	5736044	6134461	1	120036	0	120050	120035	113141	3	113667	50100	30200	10000	10000	60200	20000	10000	120047	120035	1	1	50201	100	99	100	40100	10000	10000	0	100	10000	1	10000	0	0	0	10000	0	0	1	0	3210	2	107	1	2	119657	40002	0	6	8	10000	40100	120051	120051	120036	120036	120051
50204	120050	899	0	0	0	1	1	0	120035	119493	109449	25	60100	40102	10001	10000	30100	10000	10000	1078862	5736188	6133818	0	120071	0	120050	120047	113145	3	113658	50100	30200	10000	10000	60200	20000	10000	120050	120047	1	1	50201	100	99	100	40100	10000	10000	0	100	10001	1	10000	0	0	0	10000	1	0	1	0	3210	2	107	1	2	119646	40002	6	6	0	10000	40100	120036	120036	120036	120051	120036
50204	120050	899	0	0	0	0	1	0	120035	119519	109449	25	60100	40102	10000	10000	30100	10000	10000	1079200	5735455	6136166	0	120052	0	120050	120035	113145	3	113636	50100	30200	10000	10000	60200	20000	10000	120050	120047	1	1	50201	100	99	100	40100	10000	10000	1	100	10000	1	10000	1	0	0	10000	1	0	1	0	3210	2	107	1	2	119657	40002	6	6	5	10000	40100	120051	120051	120048	120051	120036
50204	120050	900	0	0	0	60	0	0	120032	119509	109468	25	60103	40102	10001	10000	30100	10000	10000	1078999	5735455	6133818	0	120046	0	120035	120050	113141	3	113667	50100	30200	10000	10000	60200	20000	10000	120050	120047	1	1	50201	100	99	100	40100	10000	10000	0	100	10000	1	10000	0	0	0	10000	1	0	1	0	3210	3	107	1	2	119657	40002	9	6	8	10000	40100	120051	120051	120051	120051	120036
50204	120050	899	0	0	0	1	1	0	120035	119509	109449	25	60100	40102	10001	10000	30100	10000	10000	1078862	5736188	6133818	0	120331	0	120047	120035	113141	3	113636	50100	30200	10000	10000	60200	20000	10000	120050	120047	1	1	50201	100	99	100	40100	10000	10000	0	100	10000	0	10000	0	0	0	10000	0	0	0	0	3210	2	107	1	2	119660	40000	0	0	8	10000	40100	120048	120141	120040	120039	120051

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 9.0047

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk instruction (07)	09	0e	0f	19	1e	22	24	3f	4d	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	69	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	ac	af	b5	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
50025	120050	899	0	1	2	1	0	1	1	0	120032	119505	109463	25	60013	40012	10001	10000	30010	10000	10000	1079517	5736844	6133966	0	120011	0	120047	120050	113165	3	113693	50010	30020	10000	10000	60020	20000	10000	120047	120047	1	1	50021	10	9	10	40010	10000	10000	1	10	10000	0	1	10000	0	0	10000	1	1	0	0	3140	1	107	1	1	119650	40000	9	6	5	10000	40010	120098	120088	120077	120051	120049
50024	120035	899	1	0	0	0	0	1	1	0	120033	119505	109461	25	60013	40012	10004	10000	30010	10000	10000	1079523	5736044	6133499	0	120023	0	120048	120047	113165	3	113686	50010	30020	10000	10000	60020	20128	10000	120049	120048	1	1	50021	10	9	10	40010	10000	10000	0	10	10000	0	0	10000	0	0	10000	1	1	0	0	3140	1	107	1	1	119662	40002	6	6	5	10000	40010	120048	120048	120048	120051	120049
50024	120054	899	0	0	0	0	0	1	1	0	120032	119505	109541	25	60013	40010	10001	10000	30010	10000	10000	1079523	5736044	6133499	0	120023	0	120057	120047	113165	3	113686	50010	30020	10000	10000	60020	20000	10000	120035	120047	1	1	50021	10	9	10	40010	10000	10000	0	10	10000	0	1	10000	0	3	10000	1	1	0	0	3142	1	107	1	1	119664	40002	6	6	9	10000	40010	120048	120036	120049	120049	120048
50024	120047	899	0	0	0	0	0	1	1	0	120020	119492	109449	25	60013	40012	10001	10000	30010	10000	10000	1079523	5735455	6133499	0	120026	0	120413	120131	113171	3	113689	50010	30020	10000	10000	60020	20000	10000	120050	120290	2	1	50021	10	9	10	40010	10000	10000	0	10	10000	0	0	10000	0	0	10000	1	1	0	0	3140	1	107	1	1	119662	40000	6	6	5	10000	40010	120048	120048	120048	120048	120048
50024	120035	899	0	0	0	0	0	1	1	0	120035	119508	109461	25	60010	40012	10001	10000	30010	10000	10000	1079548	5736188	6133499	0	120026	0	120051	120049	113168	3	113687	50012	30020	10000	10000	60020	20000	10000	120048	120047	1	1	50021	10	9	10	40010	10000	10000	0	10	10000	0	1	10000	0	0	10000	1	1	0	0	3140	1	107	1	1	119662	40000	0	9	5	10000	40010	120051	120036	120036	120051	120051
50024	120050	899	0	0	0	0	0	1	0	0	120032	119505	109461	25	60013	40012	10001	10000	30010	10000	10000	1079523	5736044	6133499	0	120023	0	120093	120048	113168	3	113689	50010	30020	10000	10000	60020	20000	10000	120035	120047	1	1	50021	10	9	10	40010	10000	10000	0	10	10000	0	1	10000	0	0	10000	1	1	0	0	3140	1	107	1	1	119665	40002	6	6	5	10000	40010	120036	120048	120036	120048	120036
50024	120047	900	1	0	0	0	0	6	0	0	120032	119495	109461	25	60012	40014	10000	10000	30012	10000	10000	1079523	5736087	6134262	0	120024	0	120069	120047	113165	3	113686	50275	30020	10000	10000	60020	20000	10000	120048	120047	1	1	50021	10	9	10	40010	10000	10000	0	10	10000	0	1	10000	0	0	10000	0	1	0	0	3140	1	107	1	1	119662	40002	6	6	5	10000	40010	120048	120048	120584	120156	120108
50024	120488	899	0	0	0	0	1	1	1	0	120035	119508	109463	25	60013	40012	10001	10000	30010	10000	10000	1079548	5736044	6133499	0	120023	0	120056	120047	113153	3	113686	50010	30020	10000	10000	60020	20000	10000	120047	120047	1	1	50021	10	9	10	40010	10000	10000	0	10	10000	0	1	10000	0	0	10000	0	0	0	0	3140	1	107	1	1	119665	40002	6	6	5	10000	40010	120048	120051	120036	120051	120048
50024	120047	899	0	0	0	0	0	1	0	0	120020	119505	109463	25	60010	40012	10001	10000	30010	10000	10000	1079523	5736044	6133499	0	120026	0	120417	120071	113165	3	113690	50010	30020	10000	10000	60020	20000	10000	120047	120047	2	1	50021	10	9	10	40010	10000	10000	0	10	10000	0	1	10000	0	0	10000	1	1	0	0	3140	1	107	1	1	119662	40002	6	0	5	10000	40010	120048	120048	120049	120048	120048
50024	120047	899	0	0	1	0	0	1	0	0	120032	119505	109461	25	60013	40010	10000	10000	30010	10000	10000	1079517	5736044	6133499	0	120025	0	120066	120049	113165	3	113686	50010	30020	10000	10000	60020	20000	10000	120047	120047	1	1	50021	10	9	10	40010	10000	10000	0	10	10000	0	1	10000	0	0	10000	0	1	0	0	3140	1	107	1	4	119667	40002	10	9	5	10000	40010	120048	120048	120036	120048	120048

Test 3: Latency 1->3 roundtrip

Chain cycles: 3

Code:

  ldr s0, [x6, w7, uxtw]
  fmov x0, d0
  eor x8, x8, x0
  eor x8, x8, x0
  add x7, x7, x8

Initialization

  mov x7, #4
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 9.0051

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	09	l2 tlb miss data (0b)	0e	0f	18	19	1e	1f	22	23	24	3a	3f	4d	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	69	6b	6d	6e	map stall dispatch (70)	int prf full (71)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	ac	af	b5	l1d cache miss ld nonspec (bf)	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
50205	120047	899	0	0	0	0	0	0	0	6	0	0	0	0	0	120035	119563	109473	25	60103	40102	10000	10000	30100	10000	10000	1078862	5736188	6133818	0	120026	0	120035	120047	113141	0	3	113667	50389	30200	10000	10000	60200	20000	10000	120047	120047	1	1	50201	100	99	100	40100	10000	10000	0	100	10000	1	10000	0	0	10000	1	1	0	3211	2	101	3	3	119660	40002	9	6	5	10000	40100	120042	120106	120087	120060	120051
50204	120047	899	0	0	0	0	0	0	0	1	0	1	0	0	0	120035	119714	109460	25	60103	40102	10001	10000	30100	10000	10000	1078999	5736188	6133818	1	120026	0	120035	120035	113141	0	3	113667	50100	30200	10000	10000	60200	20000	10000	120050	120035	1	1	50201	100	99	100	40100	10000	10000	0	100	10000	1	10000	0	0	10000	1	1	0	3211	3	107	4	3	119662	40000	6	6	8	10000	40100	120048	120093	120074	120053	120051
50204	120035	899	0	0	0	0	0	0	0	0	0	0	0	0	0	120035	119531	109449	25	60103	40102	10001	10000	30100	10000	10000	1078999	5736044	6134461	1	120011	0	120050	120050	113143	0	27	113640	50100	30200	10000	10000	60200	20000	10000	120050	120047	2	1	50202	100	99	100	40100	10000	10000	0	100	10000	1	10000	0	0	10000	1	1	0	3211	3	107	2	3	119646	40002	6	6	8	10000	40100	120051	120096	120075	120051	120051
50204	120056	899	0	0	0	0	0	0	0	0	0	1	0	0	0	120035	119510	109449	25	60103	40102	10001	10000	30100	10000	10000	1078862	5736188	6133818	1	120026	0	120050	120050	113145	0	3	113667	50100	30200	10000	10000	60200	20000	10000	120035	120035	1	1	50201	100	99	100	40100	10000	10000	0	100	10000	1	10000	0	0	10000	0	0	0	3211	3	107	2	3	119657	40002	0	9	8	10000	40100	120108	120088	120049	120036	120048
50204	120047	899	0	0	0	0	0	0	0	1	0	1	0	0	0	120020	119534	109461	25	60112	40102	10001	10000	30100	10000	10000	1078862	5736044	6134461	0	120026	0	120047	120050	113141	0	3	113636	50100	30200	10000	10000	60200	20000	10000	120050	120035	2	1	50201	100	99	100	40100	10000	10000	0	100	10000	1	10000	0	0	10000	1	0	0	3211	2	107	3	2	119657	40002	9	0	8	10000	40100	120048	120088	120064	120052	120051
50204	120050	899	0	0	0	0	0	0	0	0	0	0	0	0	0	120020	119543	109463	25	60103	40100	10000	10000	30100	10000	10000	1078999	5736044	6134461	0	120026	0	120035	120047	113145	0	3	113658	50100	30200	10000	10000	60592	20000	10000	120050	120035	1	1	50201	100	99	100	40100	10000	10000	0	100	10000	1	10000	0	0	10000	0	0	0	3211	3	107	3	2	119657	40000	9	6	0	10000	40100	120048	120093	120082	120051	120051
50204	120050	899	0	0	0	0	0	0	0	1	0	1	0	0	0	120020	119493	109463	25	60103	40102	10001	10000	30100	10000	10000	1078999	5736188	6136166	1	120026	0	120050	120035	113145	0	3	113636	50100	30200	10000	10000	60200	20000	10000	120035	120047	1	1	50201	100	99	100	40100	10000	10000	0	100	10000	1	10000	0	3	10000	0	0	0	3211	3	101	3	3	119660	40002	9	0	8	10000	40100	120051	120107	120089	120052	120051
50204	120100	899	0	0	0	0	0	0	0	0	0	0	0	0	0	120032	119530	109463	25	60103	40100	10001	10000	30100	10000	10000	1078862	5736188	6133818	1	120026	0	120035	120050	113141	0	3	113753	50100	30200	10000	10000	60200	20000	10000	120035	120035	1	1	50201	100	99	100	40100	10000	10000	0	100	10000	1	10000	0	0	10000	1	1	0	3211	3	107	3	3	119646	40002	0	0	0	10000	40100	120051	120118	120077	120049	120036
50204	120035	899	0	0	0	0	0	0	0	1	0	0	0	0	0	120020	119528	109449	25	60100	40102	10000	10000	30100	10000	10000	1078999	5735455	6133818	0	120026	0	120050	120050	113145	0	3	113636	50100	30200	10000	10000	60200	20000	10000	120035	120047	1	1	50201	100	99	100	40100	10000	10000	0	100	10000	0	10000	0	0	10000	1	1	0	3211	3	101	3	2	120242	40002	9	9	0	10000	40100	122694	122394	122467	122570	122474
50204	122878	917	1	1	1	1	1	28	31	3471	2288	0	0	0	0	123093	121078	110334	745	60487	40338	10055	10036	30251	10000	10000	1078862	5736044	6152155	1	120026	3	120128	120488	113144	0	17	114035	50100	30200	10266	10000	60200	20000	10107	120047	120035	3	1	50201	100	99	100	40100	10000	10000	1	100	10000	0	10000	1	6	10000	0	1	2	3211	2	107	2	4	119879	40002	9	6	8	10000	40100	120110	120052	120056	120048	120052

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 9.0050

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	09	l2 tlb miss data (0b)	0e	0f	1e	22	24	3f	4d	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	69	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	ac	af	b5	l1d cache miss ld nonspec (bf)	branch mispred nonspec (cb)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
50025	120035	900	0	1	0	1	0	0	1	0	120035	119505	109463	25	60013	40018	10003	10000	30010	10000	10000	1079548	5736188	6133499	1	120130	0	120050	120050	113168	3	113686	50010	30020	10000	10000	60020	20000	10000	120035	120047	1	1	50021	10	9	10	40010	10000	10000	1	10	10000	0	10000	0	0	10000	1	0	0	3140	6	107	5	4	119662	40002	6	0	8	10000	40010	120051	120089	120058	120052	120036
50024	120047	899	0	0	0	0	0	1	0	0	120035	119492	109463	25	60013	40012	10001	10000	30010	10000	10000	1079548	5735455	6133499	1	120026	3	120047	120047	113165	3	113686	50010	30020	10000	10000	60020	20000	10000	120035	120047	1	1	50021	10	9	10	40010	10000	10000	1	10	10000	1	10000	0	3	10000	1	1	0	3140	4	107	4	5	119650	40000	9	9	8	10000	40010	120051	120051	120036	120051	120048
50024	120047	899	0	0	0	0	0	1	0	0	120020	119508	109463	25	60010	40012	10001	10000	30010	10000	10000	1079548	5735455	6133499	1	120011	0	120050	120050	113153	3	113674	50277	30020	10000	10000	60020	20000	10000	120050	120035	1	1	50021	10	9	10	40010	10000	10000	0	10	10000	0	10000	4	3	10000	1	0	0	3140	4	107	4	5	119665	40002	9	6	8	10000	40010	120048	120036	120036	120051	120051
50024	120047	899	0	0	1	0	0	1	0	0	120032	119492	109461	25	60010	40012	10000	10000	30010	10000	10000	1079548	5736188	6133499	1	120026	0	120035	120050	113153	3	113689	50010	30020	10000	10000	60020	20000	10000	120035	120047	1	1	50021	10	9	10	40010	10000	10000	0	10	10000	1	10000	0	0	10000	1	0	0	3140	5	107	5	4	119662	40002	9	0	8	10000	40010	120051	120036	120036	120052	120054
50024	120035	899	0	0	0	0	0	1	0	0	120036	119508	109461	25	60013	40012	10001	10000	30010	10000	10000	1079517	5736188	6133499	1	120023	0	120050	120035	113153	3	113689	50010	30020	10000	10000	60020	20000	10000	120050	120047	1	1	50021	10	9	10	40010	10000	10000	0	10	10000	1	10000	0	0	10000	0	0	0	3140	5	107	4	4	119662	40002	0	6	8	10000	40010	120051	120051	120036	120051	120050
50024	120050	899	0	0	0	0	0	1	0	0	120020	119508	109463	25	60062	40012	10001	10000	30010	10000	10000	1079517	5737024	6132757	1	120023	0	120050	120035	113168	3	113674	50010	30020	10000	10000	60020	20000	10000	120035	120047	1	1	50021	10	9	10	40010	10000	10000	0	10	10000	1	10000	0	0	10000	0	1	0	3140	5	107	6	5	119665	40002	9	0	8	10000	40010	120036	120051	120051	120051	120051
50024	120035	899	0	0	0	1	0	3	1	0	120035	119493	109465	25	60013	40012	10001	10001	30010	10000	10000	1079548	5736044	6132757	1	120011	0	120035	120050	113153	3	113674	50010	30020	10000	10000	60020	20000	10000	120053	120035	1	1	50021	10	9	10	40010	10000	10000	0	10	10000	0	10000	2	3	10000	0	1	0	3140	6	107	4	4	119665	40000	9	9	0	10000	40010	120051	120036	120051	120051	120051
50024	120047	900	0	0	0	0	0	1	1	0	120032	119492	109463	40	60013	40012	10001	10000	30010	10000	10000	1079517	5736188	6133499	1	120023	0	120035	120047	113168	3	113689	50010	30180	10000	10069	60020	20000	10000	120050	120048	1	1	50021	10	9	10	40010	10000	10000	0	10	10000	1	10000	0	0	10000	1	0	0	3140	4	107	4	5	119665	40002	0	0	8	10000	40010	120036	120048	120036	120051	120036
50024	120051	899	1	0	0	0	0	1	1	0	120035	119517	109449	25	60013	40012	10001	10000	30010	10000	10000	1079548	5736188	6133499	1	120011	0	120050	120050	113165	3	113689	50010	30020	10000	10000	60020	20000	10000	120050	120047	1	1	50021	10	9	10	40010	10000	10000	0	10	10000	1	10000	5	0	10000	1	1	0	3140	6	107	5	5	119650	40002	9	6	0	10000	40010	120048	120036	120051	120048	120051
50024	120047	899	0	0	0	0	1	1	0	0	120035	119508	109463	25	60013	40012	10001	10000	30010	10000	10000	1079548	5735455	6133551	1	120026	0	120050	120050	113168	3	113689	50010	30020	10000	10000	60020	20000	10000	120050	120047	1	1	50021	10	9	10	40010	10000	10000	0	10	10000	0	10000	0	0	10000	1	1	0	3140	4	107	4	5	119665	40000	0	9	0	10000	40010	120036	120051	120051	120051	120048

Test 4: throughput

Count: 8

Code:

  ldr s0, [x6, w7, uxtw]
  ldr s0, [x6, w7, uxtw]
  ldr s0, [x6, w7, uxtw]
  ldr s0, [x6, w7, uxtw]
  ldr s0, [x6, w7, uxtw]
  ldr s0, [x6, w7, uxtw]
  ldr s0, [x6, w7, uxtw]
  ldr s0, [x6, w7, uxtw]

Initialization

  mov x7, 8

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.3341

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	09	0e	0f	19	1e	22	24	3a	3f	43	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d cache miss ld (a3)	a5	ld unit uop (a6)	l1d cache writeback (a8)	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	c2	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
80205	26728	200	1	1	0	0	44	0	0	0	26692	2	1	12	21	25	80100	100	80000	100	80014	500	1167198	1	26682	26731	26707	16635	6	16683	80115	200	80024	200	160048	26731	26727	1	1	80201	100	99	100	100	80000	80000	1	100	80000	43	0	80038	0	38	80000	6	1	38	44	0	1	1	1	5118	2	16	1	2	26724	14	10	0	80000	100	26741	26735	26732	26780	26733
80204	26731	200	0	0	1	0	44	0	0	1	26716	2	1	12	19	25	80100	100	80000	100	80013	500	1167198	0	26706	26731	26731	16659	6	16683	80115	200	80024	200	160048	26731	26727	1	1	80201	100	99	100	100	80000	80000	1	100	80000	0	0	80039	0	0	80038	0	1	39	44	0	1	1	1	5118	2	16	1	2	26728	10	10	7	80000	100	26716	26729	26733	26732	26732
80204	26731	200	0	0	0	0	44	0	0	1	26693	2	0	0	0	25	80100	112	80000	100	80013	500	1166923	1	26706	26731	26731	16659	6	16683	80114	200	80024	200	160048	26731	26707	1	1	80201	100	99	100	100	80000	80000	1	100	80000	43	0	80000	2	42	80038	6	1	0	44	0	1	1	1	5118	2	16	2	1	26728	14	14	4	80000	100	26732	26732	26708	26732	26708
80204	26731	201	0	0	0	0	0	0	0	1	26712	2	0	12	27	25	80100	100	80000	100	80015	500	1168380	1	26706	26707	26731	16659	6	16684	80115	200	80024	200	160830	26731	26727	1	1	80201	100	99	100	100	80000	80000	1	100	80000	43	0	80038	0	38	80038	6	1	39	44	0	1	1	1	5118	1	16	1	2	26728	10	0	7	80000	100	26708	26708	26730	26732	26732
80204	26707	200	0	0	0	0	44	0	0	1	26712	0	0	12	19	25	80100	100	80000	100	80015	500	1168380	1	26682	26731	26731	16635	6	16683	80115	200	80024	200	160048	26707	26727	1	1	80201	100	99	100	100	80000	80000	0	100	80000	0	0	80000	0	0	80000	6	0	38	44	0	1	1	1	5118	2	16	1	2	26704	0	14	0	80000	100	26743	26730	26746	26708	26732
80204	26707	200	0	0	0	0	44	0	0	0	26716	0	12	1	19	25	80100	100	80000	100	80015	500	1168380	1	26706	26731	26732	16659	6	16659	80113	200	80024	200	160048	26731	26707	1	1	80201	100	99	100	100	80000	80000	0	100	80000	0	0	80000	0	39	80038	6	1	38	44	0	1	1	1	5118	2	16	1	2	26724	10	14	7	80000	100	26742	26731	26737	26833	26732
80204	26731	200	0	0	1	0	44	0	0	1	26716	2	1	1	19	25	80100	100	80000	100	80015	500	1167327	1	26682	26731	26727	16655	6	16683	80115	200	80024	200	160048	26731	26727	1	1	80201	100	99	100	100	80000	80000	1	100	80000	0	0	80000	0	0	80000	0	0	39	44	0	1	1	1	5118	1	16	2	2	26730	0	10	7	80000	100	26741	26728	26741	26732	26732
80204	26731	200	0	0	0	0	45	0	0	0	26712	2	12	0	0	25	80100	100	80000	100	80014	500	1167303	0	26702	26727	26707	16655	6	16661	80113	200	80024	200	160048	26731	26727	1	1	80201	100	99	100	100	80000	80000	0	100	80000	43	0	80038	0	0	80000	6	1	0	43	0	1	1	1	5118	2	16	2	1	26728	14	10	7	80000	100	26892	26815	26736	26879	26732
80204	26707	200	0	1	0	0	44	0	0	1	26716	2	12	0	21	25	80100	100	80000	100	80016	500	1168380	0	26682	26727	26707	16655	6	16683	80115	202	80604	200	160048	26735	26727	1	1	80201	100	99	100	100	80000	80000	0	100	80000	43	0	80039	3	38	80000	6	0	39	0	0	1	1	1	5118	2	16	2	1	26729	14	14	7	80000	100	26728	26733	26736	26722	26732
80204	26727	200	0	1	1	0	0	0	0	1	26712	0	12	12	16	25	80100	100	80000	100	80015	500	1168380	0	26706	26707	26727	16635	6	16683	80115	200	80024	200	160048	26731	26727	1	1	80201	100	99	100	100	80000	80000	0	100	80000	43	0	80000	0	54	80000	6	1	0	0	0	1	1	1	5118	2	16	2	2	26728	14	14	7	80000	100	26742	26732	26721	26708	26732

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.3341

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	l2 tlb miss data (0b)	0e	0f	1e	22	24	3a	3f	43	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	5f	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	92	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
80025	26737	200	0	0	0	1	0	54	1	0	1	26716	0	7	0	22	25	80010	10	80000	10	80000	50	1167791	0	1	26690	26736	26736	16681	3	16716	80010	20	80000	20	160000	26736	26715	1	1	80021	10	9	0	10	10	80000	80000	0	10	80000	0	43	80038	0	0	0	0	80038	6	1	39	44	0	0	5020	4	16	2	4	26724	14	0	7	80000	10	26736	26750	26709	26732	26732
80024	26731	200	0	0	0	1	0	44	1	0	1	26716	2	7	7	19	25	80010	10	80000	10	80000	50	1169451	0	1	26689	26736	26737	16681	3	16716	80010	20	80000	20	160000	26736	26737	1	1	80021	10	9	0	10	10	80000	80000	0	10	80000	0	43	80038	0	0	0	39	80038	6	1	39	43	0	0	5020	6	16	3	4	26705	0	0	0	80000	10	26733	26734	26734	26732	26709
80024	26731	199	0	0	0	0	1	0	1	0	0	26716	2	0	7	7	25	80010	10	80000	10	80000	50	1173975	0	1	26689	26737	26737	16681	3	16721	80010	20	80000	20	160386	26737	26736	1	1	80021	10	9	0	10	10	80000	80000	1	10	80130	0	44	80039	0	0	0	38	80038	6	0	38	44	0	0	5020	4	16	4	2	26728	10	10	4	80000	10	26742	26739	26738	26738	26738
80024	26736	200	1	1	1	0	0	67	1	0	2	26722	3	0	12	19	25	80010	10	80000	10	80000	50	1166886	0	1	26706	26731	26731	16676	3	16711	80010	20	80000	20	160000	26708	26708	1	1	80021	10	9	0	10	10	80000	80000	0	10	80000	0	43	80000	0	0	0	0	80038	0	1	39	43	0	0	5020	4	16	6	4	26724	0	10	0	80000	10	26737	26732	26732	26709	26732
80024	26708	200	0	0	0	0	1	0	0	0	0	26716	0	0	12	16	25	80010	10	80000	10	80000	50	1167501	0	0	26683	26727	26708	16672	3	16711	80010	20	80000	20	160000	26708	26727	1	1	80021	10	9	0	10	10	80000	80000	0	10	80020	19	43	80019	1	0	1	21	80040	0	1	59	45	19	0	5020	4	16	4	2	26734	13	0	5	80000	10	26738	26736	26721	26732	26732
80024	26731	200	0	0	0	0	0	44	0	0	0	26716	2	0	0	18	25	80010	10	80000	10	80000	50	1167298	0	1	26690	26714	26736	16660	3	16717	80010	20	80000	20	160000	26736	26736	1	1	80021	10	9	0	10	10	80000	80000	0	10	80000	0	43	80038	0	0	0	38	80038	0	1	0	44	0	0	5020	3	16	5	6	26724	14	0	7	80000	10	26914	26751	26738	26711	26732
80024	26731	200	0	0	0	0	0	45	0	0	1	26712	2	1	0	0	25	80010	10	80000	10	80000	50	1167124	0	0	26685	26731	26736	16676	3	16711	80010	20	80000	20	160000	26748	26728	1	1	80021	10	9	0	10	10	80000	80000	1	10	80000	0	0	80000	0	0	0	41	80000	6	0	0	44	0	0	5020	4	16	4	2	26725	0	10	7	80000	10	26734	26729	26732	26709	26732
80024	26731	200	0	0	0	0	0	0	1	0	1	26716	2	0	0	102	25	80010	10	80000	10	80000	50	1167124	0	0	26702	26728	26731	16652	3	16708	80010	20	80000	20	160000	26731	26708	1	1	80021	10	9	0	10	10	80000	80000	0	10	80000	0	0	80038	0	0	0	38	80038	6	1	39	44	0	0	5020	2	16	4	4	26724	0	10	7	80000	10	26735	26748	26732	26709	26732
80024	26731	200	0	0	0	0	0	44	0	0	1	26716	2	7	7	19	25	80010	10	80000	10	80000	50	1173975	0	1	26711	26736	26736	16681	3	16716	80010	20	80000	20	160000	26736	26715	1	1	80021	10	9	1	10	10	80000	80000	0	10	80000	0	0	80038	0	0	0	38	80000	0	1	39	43	0	0	5020	2	16	4	2	26728	14	14	0	80000	10	26746	26737	26738	26737	26716
80024	26736	200	1	1	0	1	0	66	1	0	0	26721	0	12	1	19	25	80010	10	80000	10	80000	50	1167501	0	1	26706	26731	26731	16676	3	16688	80010	20	80000	20	160000	26731	26708	1	1	80021	10	9	0	10	10	80000	80000	0	10	80020	20	43	80019	0	1	0	79	80040	0	1	58	43	19	0	5020	4	16	4	4	26735	13	13	0	80000	10	26748	26709	26709	26709	26728

LDR (register, uxtw, S)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->2 roundtrip

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: Latency 1->3 roundtrip

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 4: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations