Firestorm: LDR (unsigned offset, D) measurements

Code:

  ldr d0, [x6, #8]

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 1.000

SIMD/FP unit issues: 0.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	0e	1e	22	23	3a	3f	43	46	49	4f	51	schedule uop (52)	schedule ldst uop (55)	dispatch ldst uop (58)	simd uops in schedulers (5a)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map ldst uop (7d)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst simd load (98)	inst ldst (9b)	9d	l1d tlb access (a0)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	ea	eb	ec	? ldst retires (ed)	f5	f6	f7	f8	fd
1005	394	3	0	45	0	0	1	379	2	12	12	0	25	1000	1000	1000	15184	1	369	394	394	197	3	252	1000	1000	1000	394	394	1	1	1001	1000	1000	1	1000	43	1039	0	39	1039	6	1	39	43	73	1	16	1	1	391	0	10	4	1000	395	395	395	395	395
1004	394	3	0	45	1	0	1	379	2	12	12	16	25	1000	1000	1000	14989	0	369	394	394	217	3	252	1000	1000	1000	394	394	1	1	1001	1000	1000	0	1000	43	1039	0	42	1039	0	1	39	43	73	1	16	1	1	391	10	10	4	1000	395	399	395	412	395
1004	394	3	0	45	1	0	1	379	2	12	12	20	25	1000	1000	1000	14989	0	370	374	394	197	3	252	1000	1000	1000	394	394	1	1	1001	1000	1000	0	1000	0	1039	0	39	1039	6	1	39	43	73	1	16	1	1	391	10	10	4	1000	395	395	375	395	395
1004	394	3	0	45	1	0	1	379	2	12	12	16	25	1000	1000	1000	14060	1	369	374	394	217	3	252	1000	1000	1000	394	394	1	1	1001	1000	1000	0	1000	0	1039	0	39	1039	6	1	39	43	73	1	16	1	1	391	10	0	4	1000	395	395	395	375	395
1004	394	2	0	45	1	0	1	379	2	12	12	0	25	1000	1000	1000	15018	0	369	394	394	216	3	252	1000	1000	1000	394	394	1	1	1001	1000	1000	0	1000	43	1039	0	39	1039	6	1	39	43	73	1	16	1	1	391	10	10	4	1000	395	375	395	395	395
1004	394	3	0	45	1	0	1	379	2	12	12	16	25	1000	1000	1000	14989	1	349	374	394	217	3	252	1000	1000	1000	374	394	1	1	1001	1000	1000	0	1000	43	1039	0	39	1039	6	1	40	43	73	1	16	1	1	391	10	10	4	1000	395	395	395	395	375
1004	394	3	0	45	1	0	0	379	2	12	12	16	25	1000	1000	1000	14989	0	369	374	374	197	3	252	1000	1000	1000	394	394	1	1	1001	1000	1000	0	1000	43	1039	0	39	1039	6	1	39	43	73	1	16	1	1	391	10	10	4	1000	399	396	375	404	395
1004	394	3	0	45	1	0	1	379	0	12	12	16	25	1000	1000	1000	15018	1	369	394	394	217	3	252	1000	1000	1000	394	394	1	1	1001	1000	1000	0	1000	43	1039	0	45	1039	6	1	39	43	73	1	16	1	1	394	10	10	4	1000	395	395	395	395	395
1004	394	3	0	0	1	0	1	379	2	12	12	16	25	1000	1000	1000	15018	1	369	394	394	217	3	252	1000	1000	1000	394	394	1	1	1001	1000	1000	0	1000	0	1039	0	0	1039	0	1	39	43	73	1	16	1	1	391	10	10	4	1000	395	395	395	395	395
1004	394	2	0	45	1	0	0	379	2	0	0	16	25	1000	1000	1000	15018	0	369	394	394	216	3	252	1000	1000	1000	394	394	1	1	1001	1000	1000	0	1000	43	1039	0	39	1039	6	1	39	43	73	1	16	1	1	371	10	10	4	1000	395	395	395	395	395

Test 2: Latency 1->2 roundtrip

Chain cycles: 3

Code:

  ldr d0, [x6, #8]
  fmov x0, d0
  eor x8, x8, x0
  eor x8, x8, x0
  add x6, x6, x8

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 9.0054

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	l2 tlb miss data (0b)	0e	0f	18	19	1e	1f	22	23	3f	4d	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	69	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	af	b5	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
50205	120047	899	0	0	0	0	1	0	0	1	0	0	0	120020	119493	109504	25	60103	40100	10001	10000	30100	10000	10000	1078999	5736044	6133818	1	120023	0	120050	120035	113143	3	113667	50100	30200	10000	10000	60200	10000	10000	120050	120035	1	1	50201	100	99	100	40100	10000	10000	0	100	10000	0	1	10000	1	0	0	10000	1	0	0	0	0	0	3210	2	101	1	1	119660	40002	6	6	8	10000	40100	120051	120051	120036	120054	120051
50204	120047	899	0	0	0	0	0	0	0	18	0	0	0	120035	119509	109461	25	60103	40102	10000	10000	30100	10000	10000	1078999	5736044	6134461	1	120011	0	120035	120035	113141	3	113658	50100	30200	10000	10000	60200	10000	10000	120035	120047	1	1	50201	100	99	100	40100	10000	10000	0	100	10000	0	1	10000	0	0	0	10000	1	0	1	0	0	0	3210	1	107	1	1	119657	40002	9	6	5	10000	40100	120051	120051	120053	120109	120051
50204	120047	899	0	0	0	0	0	0	0	1	0	0	0	120035	119519	109512	25	60103	40102	10001	10000	30100	10000	10000	1078862	5735455	6136749	1	120023	0	120050	120047	113141	3	113636	50100	30200	10000	10000	60200	10000	10000	120047	120047	1	1	50201	100	99	100	40100	10000	10000	0	100	10000	0	1	10000	5	0	0	10000	1	0	0	0	0	0	3210	1	135	1	1	119657	40002	9	0	8	10000	40100	120036	120051	120051	120115	120048
50205	120035	899	0	0	0	0	0	0	0	2	0	0	0	120035	119519	109465	25	60103	40102	10001	10000	30100	10000	10000	1078862	5736188	6133818	1	120011	0	120050	120050	113145	3	113745	50100	30200	10000	10000	60200	10000	10000	120035	120047	1	1	50201	100	99	100	40100	10000	10000	0	100	10000	0	1	10000	0	0	3	10000	1	0	1	0	0	0	3210	1	135	1	1	119657	40002	9	0	0	10000	40100	120051	120036	120036	120042	120036
50204	120102	899	0	0	0	0	0	0	0	1	0	1	0	120032	119519	109521	25	60103	40100	10002	10000	30100	10000	10000	1078999	5736188	6134461	1	120011	0	120047	120035	113145	3	113636	50100	30200	10000	10000	60200	10000	10000	120050	120047	1	1	50201	100	99	100	40100	10000	10000	0	100	10000	0	1	10000	0	0	0	10000	0	0	0	0	0	0	3210	1	135	1	1	119657	40002	9	6	8	10000	40100	120036	120036	120077	120054	120051
50204	120050	899	0	0	0	0	0	0	0	0	0	1	0	120035	119509	109522	25	60103	40102	10002	10000	30100	10000	10000	1079053	5735750	6133458	1	120017	0	120041	120041	113137	3	113630	50100	30200	10000	10000	60200	10000	10000	120041	120053	1	1	50201	100	99	100	40100	10000	10000	0	100	10002	1	1	10002	0	2	1	10000	1	1	1	0	0	0	3210	1	135	1	1	119657	40000	0	6	8	10000	40100	120051	120048	120051	120054	120036
50204	120047	899	0	0	0	0	0	0	0	0	0	0	0	120035	119509	109478	25	60106	40104	10002	10000	30100	10000	10000	1079053	5735750	6136419	1	120017	0	120056	120056	113151	3	113630	50100	30200	10000	10000	60200	10000	10000	120041	120041	1	1	50201	100	99	100	40100	10000	10000	0	100	10001	2	0	10002	0	1	1	10000	0	1	0	1	1	0	3210	1	107	1	1	119663	40002	9	0	8	10000	40100	120042	120057	120057	120042	120042
50204	120041	899	1	0	1	0	0	0	0	1	0	1	0	120041	119512	109507	25	60106	40104	10001	10000	30100	10000	10000	1079053	5736476	6136419	1	120017	0	120056	120056	113151	3	113630	50100	30200	10000	10000	60200	10000	10000	120056	120041	1	1	50201	100	99	100	40100	10000	10000	0	100	10039	1	0	10042	2	3	84949	10030	0	1	1	1	0	0	3933	1	318	1	1	121673	40212	9	6	8	10000	40100	120147	120055	120060	120058	120237
50204	120056	899	1	1	0	0	0	20	25	3314	1760	0	0	122463	120869	110573	746	60471	40363	10050	10060	34354	11311	11433	1147242	5793998	6203248	1	122327	0	120056	120041	113137	3	113630	53752	34071	10937	11184	66668	11232	11179	121904	122456	23	1	50201	100	99	100	40100	10000	10000	0	100	10026	4	1	10036	0	6	77596	10000	0	1	0	1	0	0	3210	1	135	1	1	119654	40002	9	0	5	10000	40100	120055	120052	120058	120114	120079
50204	120054	899	0	0	0	1	1	0	0	6	0	0	0	120039	119513	109482	25	60103	40102	10001	10000	30100	10000	10000	1078862	5736236	6134461	0	120030	0	120051	120054	113141	3	113658	50100	30200	10000	10000	60200	10000	10000	120035	120035	1	1	50201	100	99	100	40100	10000	10000	0	100	10000	0	1	10000	0	0	0	10000	0	0	0	0	0	0	3210	1	107	1	1	119818	40002	10	0	0	10000	40100	120055	120055	120058	120133	120052

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 9.0054

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	09	l2 tlb miss data (0b)	0e	0f	1e	22	23	3a	3f	4d	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	69	6b	6d	6e	map stall dispatch (70)	int prf full (71)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	af	b5	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	branch mispred nonspec (cb)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
50025	120051	899	0	0	1	0	1	0	1	0	0	0	120020	119512	109449	25	60016	40014	10000	10000	30010	10000	10000	1079517	5736380	6133662	0	120027	0	120054	120056	113177	0	3	113690	50010	30020	10000	10000	60020	10054	10000	120417	120052	1	1	50021	10	9	10	40010	10000	10000	1	10	10006	0	1	10001	9	0	21	10000	1	0	1	0	0	0	3140	2	107	1	1	119675	40002	13	10	12	10000	40010	120042	120042	120061	120061	120110
50024	120041	899	1	1	0	1	0	0	14	0	0	0	120416	119530	109455	25	60016	40014	10006	10004	30010	10104	10050	1095296	5736716	6137588	0	120036	0	120268	120139	113302	0	27	113699	50253	30020	10000	10000	60020	10213	10000	120063	120059	1	1	50021	10	9	10	40010	10000	10000	0	10	10001	1	1	10002	82	1	7	10000	1	1	1	1	1	0	3140	1	107	1	1	119672	40004	13	13	12	10000	40010	120062	120061	120061	120064	120110
50024	120062	899	1	1	0	0	0	0	16	1	0	0	120045	119518	109455	25	60016	40014	10010	10000	30010	10000	10049	1079629	5736524	6133968	0	120017	0	120064	120253	113175	0	3	113699	50010	30020	10000	10000	60020	10000	10000	120434	120041	1	1	50021	10	9	10	40010	10000	10000	0	10	10002	7	0	10002	97	1	14326	10000	1	1	0	1	1	0	3140	2	107	1	1	119729	40004	0	13	12	10000	40010	120042	120042	120061	120042	120496
50024	120057	900	1	1	0	1	0	1	2	0	0	0	120045	119518	109473	25	60016	40012	10002	10000	30010	10000	10000	1079638	5736668	6133216	0	120036	0	120041	120060	113178	0	3	113699	50010	30020	10000	10000	60020	10000	10000	120060	120057	1	1	50021	10	9	10	40010	10000	10000	0	10	10001	2	0	10002	71	0	1	10000	1	1	1	1	0	0	3140	1	107	1	1	119656	40004	13	13	0	10000	40010	120058	120042	120058	120061	120087
50024	120057	899	1	1	0	1	0	0	1	0	0	0	120425	119518	109455	25	60016	40014	10001	10000	30010	10000	10000	1079611	5736524	6133216	0	120033	0	120057	120060	113178	0	3	113699	50010	30020	10000	10000	60020	10000	10000	120041	120057	1	1	50021	10	9	10	40010	10000	10000	0	10	10003	1	1	10002	75	3	1	10000	0	1	1	1	0	0	3140	1	107	1	1	119656	40002	0	10	12	10000	40010	120042	120061	120042	120058	120110
50024	120041	900	1	1	0	0	0	0	2	0	0	0	120045	119518	109455	25	60016	40014	10001	10000	30010	10000	10000	1079611	5736524	6134121	0	120036	0	120060	120063	113159	0	3	113700	50010	30020	10000	10000	60020	10000	10000	120041	120147	1	1	50021	10	9	10	40010	10000	10000	0	10	10001	1	0	10003	72	0	4	10000	0	1	1	1	0	0	3140	1	107	1	1	119675	40004	0	0	12	10000	40010	120042	120042	120061	120042	120088
50024	120060	899	1	1	0	0	0	0	1	0	0	0	120026	119499	109473	25	60013	40014	10002	10000	30010	10000	10000	1079611	5736668	6133216	0	120036	0	120057	120060	113159	0	3	113680	50010	30020	10000	10000	60020	10000	10000	120060	120057	1	1	50021	10	9	10	40010	10000	10000	0	10	10003	3	1	10003	62	3	169	10000	0	1	1	1	2	0	3140	1	107	1	1	119656	40004	13	10	0	10000	40010	120061	120061	120042	120061	120116
50024	120060	899	1	0	0	1	0	1	2	0	0	1	120045	119518	109455	25	60016	40014	10002	10000	30010	10000	10000	1079611	5736668	6133968	0	120036	0	120060	120057	113178	0	3	113696	50010	30020	10000	10000	60020	10000	10000	120057	120060	1	1	50021	10	9	10	40010	10000	10000	0	10	10003	2	1	10002	77	1	1	10000	1	1	1	1	1	0	3140	1	107	1	1	119675	40004	13	10	9	10000	40010	120061	120061	120042	120043	120117
50024	120180	899	1	1	0	1	0	0	1	0	0	0	120045	119515	109455	25	60016	40012	10000	10000	30010	10000	10000	1079557	5736380	6132757	0	120011	0	120054	120054	113172	0	3	113690	50010	30020	10000	10000	60020	10000	10000	120054	120096	1	1	50021	10	9	10	40010	10000	10000	0	10	10000	0	1	10000	74	0	0	10000	1	0	1	0	0	0	3140	1	107	1	1	119650	40002	10	0	12	10000	40010	120036	120055	120055	120036	120094
50024	120054	900	0	0	0	0	0	0	16	0	0	0	120036	119512	109449	25	60016	40012	10000	10000	30010	10000	10000	1079517	5735455	6133662	0	120030	0	120054	120054	113172	0	3	113693	50010	30020	10000	10000	60398	10000	10000	120054	120035	1	1	50021	10	9	10	40010	10000	10000	0	10	10000	0	1	10000	113	0	0	10000	0	0	0	0	0	0	3140	1	107	1	1	119669	40002	10	13	12	10000	40010	120100	120058	120061	120058	120113

Test 3: throughput

Count: 8

Code:

  ldr d0, [x6, #8]
  ldr d0, [x6, #8]
  ldr d0, [x6, #8]
  ldr d0, [x6, #8]
  ldr d0, [x6, #8]
  ldr d0, [x6, #8]
  ldr d0, [x6, #8]
  ldr d0, [x6, #8]

Initialization

  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.3341

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	09	0e	0f	18	1e	22	24	3a	3f	43	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
80205	26728	200	0	0	1	0	63	1	0	1	26863	2	12	1	103	49	80100	100	80000	100	80015	511	1166596	0	26687	26886	26876	16635	6	16659	80300	200	80024	200	80024	26712	26728	1	1	80201	100	99	100	100	80000	80000	0	100	80000	43	80038	0	41	80000	6	0	39	44	1	1	1	5118	3	16	0	0	26724	0	14	10	4	80000	100	26728	26728	26732	26732	26728
80204	26707	200	0	0	0	0	45	0	0	1	26712	0	0	1	0	25	80100	100	80000	100	80015	500	1166596	0	26706	26707	26727	16635	6	16679	80115	200	80024	200	80024	26741	26720	1	1	80201	100	99	100	100	80000	80000	1	100	80000	0	80000	0	38	80039	6	0	0	43	1	1	1	5164	0	16	0	0	26728	1	14	0	0	80000	100	26735	26737	26732	26708	26708
80204	26992	201	0	1	1	1	44	0	0	1	26870	2	1	1	0	25	80100	100	80000	100	80015	500	1166596	0	26710	26711	26716	16659	6	16683	80116	200	80024	200	80024	26863	26837	1	1	80201	100	99	100	100	80000	80000	0	100	80000	43	80038	1	44	80168	6	1	39	43	1	1	1	5118	0	16	0	0	26728	0	14	10	4	80000	100	26732	26728	26708	26730	26728
80204	26727	200	0	0	0	0	0	1	0	1	26712	0	12	1	16	25	80100	100	80000	100	80014	500	1166596	1	26706	26736	26735	16663	6	16687	80114	200	80024	200	80024	26866	26763	1	1	80201	100	99	100	100	80000	80000	0	100	80000	43	80039	0	39	80000	6	1	39	0	1	1	1	5118	0	16	0	0	26704	0	14	10	7	80000	100	26737	26736	26732	26708	26708
80204	26707	200	0	0	0	0	57	1	0	1	26716	2	1	0	0	25	80100	100	80000	100	80015	500	1165620	0	26706	26731	26731	16630	3	16693	80100	200	80000	200	80000	26732	26737	1	1	80201	100	99	100	100	80000	80000	0	100	80000	0	80039	0	41	80000	6	1	39	43	0	0	0	5110	1	16	1	1	26713	0	14	14	0	80000	100	26732	26735	26732	26708	26728
80204	26732	200	0	0	0	0	57	0	0	1	26718	2	0	1	19	25	80230	100	80000	100	80000	500	1173129	1	26702	26731	26731	16755	3	16786	80100	200	80000	200	80193	27035	26727	1	1	80201	100	99	100	100	80000	80000	0	100	80000	43	80038	1	38	80000	0	1	39	44	0	0	0	5110	1	16	1	1	26728	0	0	0	4	80000	100	26708	26728	26732	26728	26713
80204	26727	200	1	0	0	0	44	1	0	1	26692	2	1	0	19	25	80100	100	80000	100	80000	500	1166525	0	26706	26727	26707	16634	3	16694	80100	200	80000	200	80000	26954	26740	1	1	80201	100	99	100	100	80000	80000	0	100	80000	0	80038	0	38	80038	0	0	39	0	0	0	0	5110	1	16	1	1	26728	0	0	14	0	80000	100	26732	26732	26732	26728	26728
80204	26731	200	0	0	0	0	12	0	0	0	26716	0	1	0	19	25	80100	100	80000	100	80000	500	1167127	0	26683	26731	26707	16650	3	16689	80100	200	80000	200	80000	26916	26730	1	1	80201	100	99	100	100	80000	80000	0	100	80000	43	80038	0	38	80038	6	1	39	43	0	0	0	5110	1	25	1	1	26731	0	10	14	4	80000	100	26708	26732	26708	26732	26728
80204	26727	200	0	0	0	0	44	0	0	1	26716	2	1	0	0	25	80100	100	80000	100	80000	500	1167231	1	26682	26707	26731	16654	3	16689	80100	200	80000	200	80000	26912	26750	1	1	80201	100	99	100	100	80000	80000	0	100	80000	0	80038	0	0	80000	6	0	39	44	0	0	0	5110	1	16	1	1	26728	0	10	10	7	80000	100	26731	26708	26708	26868	26733
80204	26733	200	0	0	0	0	0	1	0	1	26692	2	1	1	19	25	80100	100	80000	100	80000	500	1165556	0	26706	26707	26731	16630	3	16685	80100	200	80000	200	80000	26736	26727	1	1	80201	100	99	100	100	80000	80000	0	100	80000	0	80038	0	38	80038	0	1	39	44	0	0	0	5110	1	41	1	1	26728	0	14	10	7	80000	100	26732	26732	26708	26708	26732

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.3342

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	l2 tlb miss data (0b)	0e	0f	1e	22	23	3a	3f	43	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	69	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	a5	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	cf	d2	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
80025	26733	200	1	1	1	1	0	65	1	0	3	26717	2	18	0	16	25	80010	10	80000	10	80000	50	1169411	26689	0	26735	26732	16659	3	16694	80010	20	80000	20	80000	26832	26740	1	1	80021	10	9	10	10	80000	80000	1	10	80019	20	42	0	80057	1	0	2	21	80038	6	0	57	42	19	1	5020	0	19	16	17	16	26712	9	9	0	80000	10	26733	26733	26733	26734	26733
80024	26732	201	1	0	0	1	0	21	1	0	3	26700	2	18	18	15	25	80010	10	80000	10	80000	50	1167599	26690	0	26735	26715	16678	3	16713	80010	20	80000	20	80000	26842	26743	1	1	80021	10	9	10	10	80000	80000	0	10	80020	20	42	0	80057	1	0	0	59	80038	6	1	19	42	19	1	5020	0	14	16	17	14	26729	0	9	2	80000	10	26733	26733	26733	26733	26733
80024	26732	200	1	1	1	1	1	65	0	0	2	26717	2	0	0	15	25	80010	10	80000	10	80000	50	1166960	26707	0	26714	26732	16678	3	16713	80010	20	80000	20	80000	26842	26737	1	1	80021	10	9	10	10	80000	80000	0	10	80020	19	42	0	80019	1	0	1	59	80038	6	1	57	0	19	0	5020	0	29	16	17	11	26729	9	9	2	80000	10	26734	26734	26734	26734	26716
80024	26733	200	1	1	1	0	0	65	1	0	2	26717	2	18	18	16	25	80010	10	80000	10	80000	50	1165822	26708	0	26732	26732	16677	3	16712	80010	20	80000	20	80000	26740	26746	1	1	80021	10	9	10	10	80000	80000	1	10	80019	20	42	0	80057	1	0	1	59	80000	6	1	57	42	19	1	5020	0	35	16	18	16	26736	9	9	2	80000	10	26734	26734	26733	26733	26733
80024	26715	200	1	1	0	0	0	65	0	0	3	26700	2	18	18	16	25	80010	10	80000	10	80000	50	1167298	26690	0	26777	26738	16660	3	16712	80010	20	80000	20	80000	26717	26732	1	1	80021	10	9	10	10	80000	80000	0	10	80019	19	42	0	80057	1	0	0	62	80038	6	1	57	42	19	1	5020	0	24	16	14	16	26729	9	9	0	80000	10	26715	26733	26733	26733	26734
80024	26733	200	1	1	0	0	0	65	1	0	2	26699	0	18	18	16	25	80010	10	80000	10	80000	50	1167599	26707	0	26714	26732	16677	3	16712	80010	20	80000	20	80000	26832	26719	1	1	80021	10	9	10	10	80000	80000	0	10	80021	21	42	0	80057	0	0	2	59	80038	0	1	57	0	19	0	5020	0	22	16	18	18	26743	0	9	2	80000	10	26715	26715	26733	26733	26734
80024	26715	200	1	0	0	0	0	66	1	0	3	26718	2	18	18	15	25	80010	10	80000	10	80000	50	1167599	26708	0	26732	26732	16678	3	16713	80010	20	80000	20	80000	26856	26737	1	1	80021	10	9	10	10	80000	80000	0	10	80020	19	42	0	80057	1	1	1	59	80038	6	0	57	42	19	0	5020	0	25	16	8	16	26732	9	9	2	80000	10	26733	26716	26734	26734	26736
80024	26715	200	1	0	1	0	0	65	1	0	3	26717	0	18	18	16	25	80010	10	80000	10	80000	50	1167660	26689	0	26733	26714	16677	3	16712	80010	20	80000	20	80000	26837	26720	1	1	80021	10	9	10	10	80000	80000	0	10	80019	19	42	0	80019	1	0	0	59	80038	0	1	57	42	19	0	5020	0	24	16	17	14	26712	9	9	2	80000	10	26734	26733	26733	26733	26733
80024	26732	200	1	1	0	0	0	65	0	0	3	26718	0	18	18	0	25	80010	10	80000	10	80000	50	1167660	26707	0	26732	26732	16684	3	16712	80010	20	80000	20	80000	26744	26835	1	1	80021	10	9	10	10	80000	80000	0	10	80019	19	42	0	80057	0	0	0	21	80038	6	0	19	42	19	2	5020	0	21	16	17	12	26865	9	9	2	80000	10	26733	26733	26733	26733	26734
80024	26732	201	1	0	0	0	0	21	1	0	0	26719	2	18	18	16	25	80010	10	80000	10	80000	50	1170204	26707	0	26732	26733	16677	3	16694	80010	20	80000	20	80000	26841	26739	2	1	80021	10	9	10	10	80000	80000	0	10	80019	20	42	29	80018	0	0	0	21	80038	0	1	19	0	19	0	5020	0	25	16	16	9	26730	9	9	2	80000	10	26733	26733	26716	26716	26716

LDR (unsigned offset, D)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->2 roundtrip

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations