Firestorm: LDR (unsigned offset, Q) measurements

Code:

  ldr q0, [x6, #8]

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 1.000

SIMD/FP unit issues: 0.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	09	0e	0f	1e	22	3a	3f	43	46	49	4f	51	schedule uop (52)	schedule ldst uop (55)	dispatch ldst uop (58)	simd uops in schedulers (5a)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map ldst uop (7d)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst simd load (98)	inst ldst (9b)	9d	l1d tlb access (a0)	l1d cache miss ld (a3)	ld unit uop (a6)	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	ea	eb	ec	? ldst retires (ed)	f5	f6	f7	f8	fd
1005	389	3	0	0	0	41	1	1	374	2	18	18	12	25	1000	1000	1000	14838	1	364	389	389	212	3	247	1000	1000	1000	389	389	1	1	1001	1000	1000	0	1000	42	1035	35	1035	6	1	35	39	73	2	16	2	2	386	6	6	2	1000	390	390	390	392	390
1004	389	3	0	0	0	59	1	1	374	2	18	18	12	25	1000	1000	1000	14838	1	366	389	391	212	3	247	1000	1000	1000	389	389	1	1	1001	1000	1000	0	1000	39	1035	35	1035	6	1	35	39	73	2	16	2	2	386	6	6	2	1000	390	390	390	390	390
1004	389	3	0	0	0	41	0	1	374	2	18	18	12	25	1000	1000	1000	14774	1	364	391	389	212	3	247	1000	1000	1000	389	389	1	1	1001	1000	1000	1	1000	39	1035	35	1035	6	1	35	39	73	2	16	2	2	386	6	6	2	1000	390	390	390	390	390
1004	389	3	0	0	0	42	1	1	374	2	18	18	12	25	1000	1000	1000	14838	1	364	389	389	212	3	252	1000	1000	1000	423	389	1	1	1001	1000	1000	0	1000	39	1035	35	1035	6	1	35	39	73	2	16	2	2	386	6	6	2	1000	390	390	390	390	394
1004	389	3	0	0	0	41	0	1	374	2	18	18	12	25	1000	1000	1000	14838	1	364	389	389	212	3	247	1000	1000	1000	389	389	1	1	1001	1000	1000	0	1000	39	1035	35	1035	6	1	35	39	73	2	16	2	2	386	6	6	2	1000	390	390	392	390	390
1004	389	2	0	0	0	41	1	1	374	2	18	18	12	25	1000	1000	1000	15037	1	369	389	389	212	3	252	1000	1000	1000	389	389	1	1	1001	1000	1000	0	1000	39	1035	39	1035	6	1	35	39	73	2	16	2	2	386	6	6	2	1000	390	390	392	390	390
1004	389	3	0	0	0	48	1	1	374	2	18	18	12	25	1000	1000	1000	14838	1	364	389	389	212	3	247	1000	1000	1000	389	389	1	1	1001	1000	1000	0	1000	39	1035	35	1039	6	1	35	39	73	2	16	2	2	386	6	6	2	1000	390	395	390	390	390
1004	389	3	0	0	0	41	1	2	374	2	12	18	12	25	1000	1000	1000	14838	1	364	389	389	212	3	247	1000	1000	1000	389	389	1	1	1001	1000	1000	0	1000	39	1039	36	1035	6	1	35	39	73	2	16	2	2	386	6	6	2	1000	390	394	390	395	390
1004	392	3	0	0	0	41	0	1	374	2	18	18	11	25	1000	1000	1000	14838	1	366	389	391	212	3	252	1000	1000	1000	394	391	1	1	1001	1000	1000	0	1000	39	1035	35	1035	6	1	35	39	73	2	16	2	2	386	10	6	2	1000	390	390	390	390	390
1004	389	3	0	1	1	41	0	1	374	2	18	18	12	25	1000	1000	1000	14838	1	364	394	391	212	3	259	1000	1000	1000	389	389	1	1	1001	1000	1000	1	1000	39	1035	35	1035	6	1	35	39	73	2	16	2	2	386	6	6	2	1000	390	390	395	390	390

Test 2: Latency 1->2 roundtrip

Chain cycles: 3

Code:

  ldr q0, [x6, #8]
  fmov x0, d0
  eor x8, x8, x0
  eor x8, x8, x0
  add x6, x6, x8

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 9.0051

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	09	l2 tlb miss data (0b)	0e	0f	18	19	1e	1f	22	23	24	3a	3f	4d	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	69	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	af	b5	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
50205	120053	900	0	0	0	0	0	0	0	0	1	0	1	0	0	0	120083	119519	109449	25	60103	40102	10001	10000	30100	10000	10000	1079209	5735455	6133818	0	120023	0	120047	120047	113143	3	113636	50100	30200	10000	10000	60200	10000	10000	120047	120053	1	1	50201	100	99	100	40100	10000	10000	0	100	10000	0	1	10000	0	1	0	10000	1	0	1	0	0	0	0	3210	2	135	1	1	119660	40002	6	6	5	10000	40100	120048	120036	120051	120036	120037
50204	120047	899	0	0	0	0	0	0	0	0	1	0	1	0	0	0	120065	119519	109461	25	60103	40102	10001	10000	30100	10000	10000	1079200	5736044	6133818	0	120023	0	120047	120035	113143	3	113636	50100	30200	10000	10000	60200	10000	10000	120035	120047	1	1	50201	100	99	100	40100	10000	10000	0	100	10000	0	1	10000	0	0	0	10000	0	0	0	0	0	0	0	3210	1	135	1	1	119660	40002	6	6	5	10000	40100	120050	120433	120051	120150	120048
50204	120047	900	0	0	0	0	0	0	0	0	28	88	1	0	0	0	120109	119519	109461	25	60103	40102	10001	10000	30100	10000	10000	1078862	5736044	6133818	0	120011	0	120047	120047	113143	3	113636	50100	30200	10000	10000	60200	10000	10000	120047	120047	1	1	50201	100	99	100	40100	10000	10000	0	100	10000	0	1	10000	0	0	0	10000	1	0	1	0	0	0	0	3210	1	135	0	1	119813	40016	6	6	5	10000	40100	120131	120243	120265	120048	120148
50204	120232	899	0	0	0	0	0	0	0	0	1	0	0	0	0	0	120066	119519	109449	25	60103	40100	10001	10000	30100	10000	10000	1079209	5736044	6134513	0	120023	0	120047	120047	113143	3	113636	50100	30200	10000	10000	60200	10000	10000	120047	120047	1	1	50201	100	99	100	40100	10000	10000	0	100	10000	0	1	10000	0	0	6	10000	1	0	1	0	0	0	0	3210	1	135	1	1	119646	40000	6	6	5	10000	40100	120048	120048	120048	120048	120048
50204	120047	899	0	0	0	0	0	0	0	0	1	0	1	0	0	0	120072	119519	109461	25	60103	40102	10001	10000	30100	10000	10000	1079200	5736044	6133818	0	120011	0	120047	120047	113143	3	113636	50100	30200	10000	10000	60200	10000	10000	120047	120047	1	1	50201	100	99	100	40100	10000	10000	0	100	10000	0	1	10000	0	0	0	10000	1	0	1	0	0	0	0	3210	2	135	1	1	119660	40002	6	6	5	10000	40100	120048	120048	120048	120048	120036
50204	120047	899	0	0	0	0	0	0	0	0	0	0	1	0	0	0	120081	119519	109461	25	60103	40102	10000	10000	30100	10000	10000	1078862	5736044	6133818	0	120023	0	120047	120047	113143	3	113636	50100	30200	10000	10000	60200	10000	10000	120047	120035	1	1	50201	100	99	100	40100	10000	10000	0	100	10000	0	1	10000	0	0	3	10000	0	0	1	0	0	0	0	3250	1	135	1	1	119660	40000	6	6	5	10000	40100	120048	120048	120048	120048	120048
50204	120047	899	0	0	0	0	0	0	0	0	6	0	1	0	0	0	120083	119493	109461	25	60103	40102	10001	10000	30100	10000	10000	1079200	5735455	6133818	0	120023	0	120035	120047	113143	3	113659	50100	30200	10000	10000	60200	10000	10000	120035	120047	1	1	50201	100	99	100	40100	10000	10000	0	100	10000	0	1	10000	0	0	0	10000	1	0	1	0	0	1	0	3210	1	101	1	1	119646	40002	6	6	5	10000	40100	120036	120048	120036	120048	120051
50204	120047	899	0	0	0	0	1	0	0	0	1	0	1	0	0	0	120094	119519	109461	25	60103	40102	10001	10000	30100	10000	10000	1079200	5736044	6133818	1	120011	0	120047	120047	113143	3	113636	50100	30200	10000	10000	60200	10000	10000	120047	120047	1	1	50201	100	99	100	40100	10000	10000	0	100	10000	0	0	10000	0	0	42563	10030	1	0	1	0	2	0	0	3932	1	305	1	3	121679	40201	6	6	5	10000	40100	122437	122433	122508	122421	122632
50204	122509	917	0	1	1	0	0	0	0	0	0	0	1	0	0	1	122117	120503	110339	762	60447	40318	10045	10054	33928	11103	11378	1142171	5798562	6196750	0	122731	0	123356	123336	114223	460	115477	58865	35068	11981	11771	71672	11922	11637	123444	123412	35	1	50201	100	99	100	40100	10000	10000	0	100	10034	1	1	10048	0	0	92578	10028	1	0	1	0	2	0	0	3987	2	314	1	1	119660	40062	6	6	5	10000	40100	122105	122224	122637	122075	122127
50204	120035	963	0	1	0	0	0	0	20	25	3304	1848	1	0	0	0	120043	119510	109464	25	60103	40102	10001	10000	30100	10000	10000	1079008	5735455	6138362	0	120027	0	120041	120051	113141	3	113668	50100	30200	10000	10000	60200	10000	10000	120051	120035	1	1	50201	100	99	100	40100	10000	10000	0	100	10000	0	1	10001	0	0	1	10000	1	0	1	0	0	0	0	3210	1	135	1	1	119658	40002	10	10	9	10000	40100	120036	120052	120052	120036	120036

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 9.0050

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	09	0e	0f	18	1e	22	23	3f	4d	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	int prf full (71)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	ac	af	b5	l1d cache miss ld nonspec (bf)	c2	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
50025	120047	899	0	0	0	1	0	0	0	0	120035	119505	109505	25	60013	40012	10001	10000	30010	10000	10000	1079548	5736188	6133499	0	120011	120050	120050	113165	0	3	113674	50010	30020	10000	10000	60020	10000	10000	120047	120035	1	1	50022	10	9	10	40010	10000	10000	1	10	10000	0	10000	0	6	10000	1	1	0	0	3140	2	107	3	2	119662	40000	9	6	8	10000	40010	120051	120036	120048	120048	120049
50024	120050	899	0	0	0	0	0	1	0	0	120035	119505	109465	25	60013	40012	10001	10000	30010	10000	10000	1079548	5735455	6133499	1	120026	120035	120050	113153	0	3	113689	50010	30020	10000	10000	60020	10000	10000	120050	120035	1	1	50021	10	9	10	40010	10000	10000	0	10	10000	0	10000	0	0	10000	1	1	0	0	3140	1	107	1	1	119665	40002	0	9	8	10000	40010	120048	120048	120048	120091	120051
50024	120035	899	0	0	0	0	0	1	0	0	120035	119505	109478	25	60010	40012	10001	10000	30010	10000	10000	1079523	5736188	6132757	0	120023	120035	120047	113165	0	3	113686	50010	30020	10000	10000	60020	10000	10000	120050	120091	1	1	50021	10	9	10	40010	10000	10000	0	10	10000	1	10000	0	0	10000	1	0	0	0	3140	1	107	2	1	119665	40000	0	6	8	10000	40010	120036	120051	120048	120076	120051
50024	120052	899	0	1	0	0	0	0	0	0	120035	119585	109449	25	60013	40012	10001	10000	30010	10000	10000	1079548	5736188	6133499	1	120011	120047	120050	113168	0	3	113689	50010	30020	10000	10000	60398	10000	10000	120050	120035	1	1	50021	10	9	10	40010	10000	10000	1	10	10000	1	10000	0	0	10000	1	1	2	0	3140	1	107	1	1	119650	40002	9	0	0	10000	40010	120036	120036	120048	120103	120036
50024	120050	899	0	0	0	0	0	37	0	0	120020	119505	109461	25	60013	40010	10001	10000	30010	10000	10000	1079517	5736188	6133499	0	120026	120050	120050	113153	0	3	113674	50010	30020	10000	10000	60020	10000	10000	120035	120035	1	1	50021	10	9	10	40010	10000	10000	0	10	10000	1	10000	0	0	10000	1	1	0	0	3140	1	107	1	1	119665	40002	6	0	8	10000	40010	120051	120036	120102	120060	120037
50024	120050	899	0	0	0	0	0	1	0	0	120032	119505	109492	25	60010	40010	10001	10000	30010	10000	10000	1079523	5736044	6133652	1	120011	120035	120047	113168	0	3	113666	50010	30204	10000	10000	60020	10000	10000	120056	120053	1	1	50021	10	9	10	40010	10000	10000	0	10	10000	1	10000	0	0	10000	0	1	0	0	3140	1	107	1	1	119665	40002	6	6	0	10000	40010	120048	120051	120048	120097	120051
50024	120047	899	0	0	0	0	0	10	0	0	120035	119505	109479	25	60013	40012	10000	10000	30010	10000	10000	1079523	5736044	6132757	0	120011	120047	120050	113168	0	3	113689	50010	30020	10000	10000	60020	10000	10000	120035	120047	1	1	50021	10	9	10	40010	10000	10000	0	10	10000	1	10000	0	0	10000	1	0	0	0	3140	1	107	1	1	119665	40002	9	0	8	10000	40010	120036	120051	120048	120100	120036
50024	120097	899	0	0	0	0	4	1	0	0	120035	119505	109481	25	60013	40010	10001	10000	30010	10000	10000	1079523	5736870	6134165	0	120026	120047	120035	113168	0	3	113689	50010	30020	10000	10000	60020	10000	10000	120050	120035	1	1	50021	10	9	10	40010	10000	10000	0	10	10000	1	10000	4	0	10000	1	1	0	0	3140	1	107	1	1	119650	40002	6	6	8	10000	40010	120051	120048	120048	120107	120036
50024	120035	899	0	0	0	0	0	0	1	0	120035	119541	109461	25	60013	40012	10001	10000	30010	10000	10000	1079523	5735455	6133499	0	120026	120047	120047	113153	0	3	113674	50010	30020	10000	10000	60020	10000	10000	120035	120047	1	1	50021	10	9	10	40010	10000	10000	0	10	10000	0	10000	0	3	10000	0	1	0	0	3140	1	107	1	1	119662	40002	0	6	5	10000	40010	120036	120036	120142	120073	120048
50024	120035	899	0	0	0	1	0	1	0	0	120035	119505	109477	25	60013	40012	10001	10000	30010	10000	10000	1079523	5735455	6133551	1	120011	120050	120050	113153	0	3	113689	50010	30020	10000	10000	60020	10000	10000	120035	120047	1	1	50021	10	9	10	40010	10000	10000	0	10	10000	0	10000	0	0	10000	1	1	0	0	3140	1	107	1	1	119662	40000	9	0	0	10000	40010	120050	120048	120124	120052	120051

Test 3: throughput

Count: 8

Code:

  ldr q0, [x6, #8]
  ldr q0, [x6, #8]
  ldr q0, [x6, #8]
  ldr q0, [x6, #8]
  ldr q0, [x6, #8]
  ldr q0, [x6, #8]
  ldr q0, [x6, #8]
  ldr q0, [x6, #8]

Initialization

  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.3342

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	09	l2 tlb miss data (0b)	0e	0f	1e	22	23	3a	3f	43	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	67	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
80205	26734	200	1	1	1	0	1	1	113	1	0	3	26699	0	18	18	0	25	80100	100	80000	100	80000	500	1167016	0	26862	26802	26734	16665	3	16690	80100	200	80000	200	80000	26733	26732	1	1	80201	100	99	100	100	80000	80000	0	100	80020	19	42	80057	1	0	2	59	80168	6	1	57	0	19	0	5110	1	16	1	1	26729	0	9	2	80000	100	26733	26733	26715	26734	26715
80204	26733	200	1	1	1	0	1	0	65	0	0	2	26699	2	18	18	0	25	80100	100	80000	100	80000	500	1167943	0	26707	26733	26732	16637	3	16690	80100	200	80000	200	80000	26733	26714	1	1	80201	100	99	100	100	80000	80000	0	100	80020	19	0	80057	1	0	1	59	80038	6	1	58	40	19	1	5110	1	16	1	1	26729	9	9	2	80000	100	26715	26733	26733	26715	26715
80204	26732	200	1	1	0	0	1	1	65	1	0	2	26699	2	18	18	16	25	80100	100	80000	100	80000	500	1167264	0	26689	26733	26716	16655	3	16690	80100	200	80000	200	80000	26733	26732	1	1	80201	100	99	100	100	80000	80000	0	100	80019	19	42	80056	1	0	2	59	80038	6	1	57	42	19	1	5110	1	16	1	1	26729	9	9	0	80000	100	26734	26734	26715	26733	26733
80204	26732	201	1	1	0	0	1	1	65	0	0	2	26718	0	0	18	15	25	80100	100	80000	100	80000	500	1169676	0	26716	26714	26734	16655	3	16690	80100	200	80000	200	80000	26732	26732	1	1	80201	100	99	100	100	80000	80000	0	100	80020	19	42	80057	1	0	1	59	80038	6	1	19	42	19	0	5110	1	16	1	1	26729	9	9	2	80000	100	26734	26733	26733	26733	26733
80204	26732	201	1	0	0	1	1	0	65	1	0	2	26718	2	18	18	17	25	80100	100	80000	100	80000	500	1166758	0	26739	26746	26736	16662	3	16691	80100	200	80000	200	80000	26732	26714	1	1	80201	100	99	100	100	80000	80000	0	100	80019	19	0	80057	0	0	0	21	80038	6	1	57	42	19	1	5110	1	16	1	1	26729	9	9	2	80000	100	26734	26734	26733	26733	26733
80204	26714	200	1	1	0	1	1	0	65	0	0	2	26718	2	18	18	1	25	80100	100	80000	100	80000	500	1167685	0	26707	26733	26732	16655	3	16690	80100	200	80000	200	80000	26733	26732	1	1	80201	100	99	100	100	80000	80000	0	100	80020	20	42	80057	1	0	0	98	80000	6	0	57	42	19	0	5110	1	16	1	1	26711	9	9	2	80000	100	26733	26715	26715	26715	26733
80204	26714	200	1	1	1	1	1	0	65	1	0	1	26717	3	0	0	16	25	80100	100	80000	100	80000	500	1159120	0	26707	26732	26732	16655	3	16691	80100	200	80000	200	80000	26714	26714	1	1	80201	100	99	100	100	80000	80000	0	100	80020	19	42	80057	0	0	0	59	80039	0	1	57	42	19	1	5110	1	16	1	1	26729	9	0	0	80000	100	26733	26733	26733	26733	26733
80204	26732	200	1	1	0	1	1	0	21	1	0	1	26717	0	0	0	16	25	80100	100	80000	100	80000	500	1159120	0	26708	26733	26732	16655	3	16690	80100	200	80000	200	80000	26732	26714	1	1	80201	100	99	100	100	80000	80000	0	100	80020	19	0	80057	1	0	1	21	80038	6	1	19	0	19	0	5110	1	16	1	1	26729	0	9	2	80000	100	26733	26715	26733	26733	26734
80204	26733	200	1	0	0	1	1	0	65	1	0	2	26717	2	0	18	16	25	80100	100	80000	100	80000	500	1169676	0	26710	26732	26732	16637	3	16690	80100	200	80000	200	80000	26732	26732	1	1	80201	100	99	100	100	80000	80000	0	100	80019	20	42	80057	1	0	0	59	80038	6	1	19	42	19	0	5110	1	16	1	1	26730	9	9	2	80000	100	26733	26733	26733	26733	26715
80204	26733	200	1	0	1	1	1	0	65	1	0	2	26717	0	18	18	1	25	80100	100	80000	100	80000	500	1166519	0	26723	26741	26732	16655	3	16690	80100	200	80000	200	80000	26732	26732	1	1	80201	100	99	100	100	80000	80000	0	100	80021	20	0	80019	1	0	0	59	80038	6	1	57	42	19	1	5110	1	16	1	1	26729	9	9	2	80000	100	26737	26734	26734	26733	26733

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.3342

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	09	l2 tlb miss data (0b)	0e	0f	1e	22	23	3a	3f	43	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
80025	26732	200	1	1	1	0	1	0	64	1	0	3	26700	2	18	18	17	25	80010	10	80000	10	80000	50	1167599	26709	26732	26732	16677	3	16712	80010	20	80000	20	80000	26732	26732	1	1	80021	10	9	10	10	80000	80000	0	10	80020	20	42	80058	1	0	1	21	80036	6	1	56	42	19	1	5020	7	16	6	4	26729	9	9	2	80000	10	26733	26853	26770	26717	26737
80024	26733	200	1	0	0	0	1	0	21	0	0	2	26717	2	18	18	16	25	80010	10	80000	10	80000	50	1173074	26716	26733	26732	16659	3	16712	80010	20	80000	20	80000	26733	26732	1	1	80021	10	9	10	10	80000	80000	0	10	80020	20	42	80056	0	0	0	59	80038	6	0	19	0	19	0	5020	6	16	6	6	26712	0	0	2	80000	10	26733	26733	26716	26733	26734
80024	26715	200	1	1	0	0	1	1	65	1	0	3	26717	2	18	0	16	25	80010	10	80000	10	80000	50	1167298	26716	26732	26732	16678	3	16713	80010	20	80000	20	80000	26732	26732	1	1	80021	10	9	10	10	80000	80000	0	10	80020	19	0	80057	0	0	0	59	80038	6	0	57	0	19	0	5020	4	16	7	6	26729	0	9	0	80000	10	26733	26733	26733	26733	26733
80024	26732	200	1	1	1	1	1	0	65	0	0	2	26717	2	18	0	15	25	80010	10	80000	10	80000	50	1167599	26722	26732	26733	16677	3	16695	80010	20	80000	20	80000	26733	26733	1	1	80021	10	9	10	10	80000	80000	0	10	80018	19	42	80057	0	0	0	59	80038	6	0	57	0	19	0	5020	6	16	6	4	26729	9	0	2	80000	10	26733	26716	26734	26734	26733
80024	26732	200	1	0	1	0	1	0	21	1	0	3	26699	2	0	18	15	25	80010	10	80000	10	80000	50	1167599	26708	26715	26732	16677	3	16712	80010	20	80000	20	80000	26732	26733	1	1	80021	10	9	10	10	80000	80000	0	10	80019	18	42	80057	0	0	3	59	80037	6	1	57	42	19	2	5020	4	16	7	5	26730	9	0	2	80000	10	26716	26734	26733	26733	26716
80024	26715	200	1	1	0	0	1	0	65	0	0	1	26700	0	0	18	16	25	80010	10	80000	10	80000	50	1169557	26707	26733	26732	16659	3	16712	80010	20	80000	20	80000	26733	26732	1	1	80021	10	9	10	10	80000	80000	0	10	80021	20	42	80057	1	0	2	59	80000	0	0	56	42	19	1	5020	6	16	4	6	26729	9	9	2	80000	10	26733	26733	26733	26733	26733
80024	26714	200	1	1	1	0	1	1	65	0	0	2	26700	2	18	18	16	25	80010	10	80000	10	80000	50	1167660	26718	26714	26732	16677	3	16712	80010	20	80000	20	80000	26732	26732	1	1	80021	10	9	10	10	80000	80000	0	10	80019	19	42	80057	1	0	0	21	80000	6	1	57	42	19	0	5020	6	16	6	4	26729	9	9	2	80000	10	26734	26734	26716	26736	26733
80024	26732	200	1	0	0	1	1	0	65	0	0	2	26717	2	18	0	16	25	80010	10	80000	10	80000	50	1167660	26891	26740	26737	16678	3	16713	80010	20	80000	20	80000	26732	26732	1	1	80021	10	9	10	10	80000	80000	0	10	80022	20	0	80057	0	0	2	59	80038	6	0	19	42	19	1	5020	6	16	6	5	26732	9	0	2	80000	10	26736	26715	26715	26716	26734
80024	26715	200	1	1	1	1	1	0	68	1	0	0	26717	0	18	18	15	25	80010	10	80000	10	80000	50	1167599	26711	26732	26732	16677	3	16712	80010	20	80000	20	80000	26732	26715	1	1	80021	10	9	10	10	80000	80000	0	10	80019	21	42	80057	0	0	0	58	80038	6	1	57	42	19	0	5020	5	16	4	6	26729	9	9	0	80000	10	26733	26733	26733	26733	26715
80024	26732	200	1	1	1	1	1	1	65	1	0	2	26717	0	18	18	16	25	80010	10	80000	10	80000	50	1167599	26708	26732	26715	16677	3	16712	80010	20	80000	20	80000	26732	26715	1	1	80021	10	9	10	10	80000	80000	1	10	80020	20	42	80057	2	0	1	59	80000	0	1	57	42	19	0	5020	4	16	4	6	26730	0	0	0	80000	10	26733	26733	26716	26733	26733

LDR (unsigned offset, Q)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->2 roundtrip

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations