Apple Microarchitecture Research by Dougall Johnson M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions M1/A14 E-core (Icestorm): Overview | Base Instructions | SIMD and FP Instructions
Code:
ldr s0, [x6, #8]
mov x0, 1 mov x1, 2 mov x8, 0
(no loop instructions)
Retires: 1.000
Issues: 1.000
Integer unit issues: 0.000
Load/store unit issues: 1.000
SIMD/FP unit issues: 0.000
| retire uop (01) | cycle (02) | 03 | l1d tlb fill (05) | mmu table walk data (08) | 09 | l2 tlb miss data (0b) | 0e | 0f | 1e | 22 | 24 | 3a | 3f | 43 | 46 | 49 | 4f | 51 | schedule uop (52) | schedule ldst uop (55) | dispatch ldst uop (58) | simd uops in schedulers (5a) | 60 | 69 | 6d | 6e | map stall dispatch (70) | map rewind (75) | map stall (76) | dispatch uop (78) | map ldst uop (7d) | map ldst uop inputs (80) | 82 | 83 | flush restart other nonspec (84) | 85 | inst all (8c) | 92 | inst simd load (98) | inst ldst (9b) | 9d | l1d tlb access (a0) | l1d tlb miss (a1) | l1d cache miss ld (a3) | ld unit uop (a6) | st unit uop (a7) | l1d cache writeback (a8) | a9 | ac | af | b5 | b6 | bb | l1d cache miss ld nonspec (bf) | l1d tlb miss nonspec (c1) | c2 | cf | d5 | map dispatch bubble (d6) | dd | fetch restart (de) | e0 | ea | eb | ec | ? ldst retires (ed) | f5 | f6 | f7 | f8 | fd |
| 1005 | 403 | 3 | 1 | 1 | 0 | 0 | 0 | 0 | 45 | 1 | 0 | 1 | 388 | 0 | 12 | 12 | 16 | 25 | 1000 | 1000 | 1000 | 14989 | 0 | 369 | 374 | 394 | 217 | 3 | 252 | 1000 | 1000 | 1000 | 394 | 374 | 1 | 1 | 1001 | 0 | 1000 | 1000 | 0 | 1019 | 19 | 43 | 1019 | 1 | 0 | 0 | 0 | 1000 | 6 | 1 | 39 | 0 | 0 | 0 | 73 | 2 | 16 | 2 | 2 | 371 | 0 | 14 | 5 | 1000 | 399 | 401 | 375 | 399 | 375 |
| 1004 | 374 | 3 | 0 | 0 | 0 | 0 | 0 | 0 | 44 | 1 | 0 | 1 | 390 | 0 | 12 | 1 | 16 | 25 | 1000 | 1000 | 1000 | 15267 | 0 | 374 | 398 | 398 | 224 | 3 | 256 | 1000 | 1000 | 1000 | 394 | 374 | 1 | 1 | 1001 | 0 | 1000 | 1000 | 0 | 1019 | 19 | 0 | 1073 | 0 | 0 | 0 | 21 | 1040 | 6 | 0 | 59 | 45 | 19 | 1 | 73 | 2 | 16 | 2 | 2 | 395 | 0 | 0 | 5 | 1000 | 404 | 404 | 383 | 409 | 404 |
| 1004 | 381 | 3 | 1 | 0 | 0 | 0 | 0 | 0 | 67 | 0 | 0 | 1 | 388 | 0 | 0 | 1 | 20 | 25 | 1000 | 1000 | 1000 | 14060 | 1 | 374 | 398 | 394 | 221 | 3 | 232 | 1000 | 1000 | 1000 | 394 | 374 | 1 | 1 | 1001 | 6 | 1000 | 1000 | 1 | 1000 | 0 | 43 | 1000 | 0 | 0 | 0 | 38 | 1038 | 0 | 0 | 0 | 44 | 0 | 0 | 73 | 2 | 16 | 2 | 2 | 395 | 10 | 11 | 0 | 1000 | 399 | 375 | 405 | 399 | 399 |
| 1004 | 374 | 3 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 1 | 388 | 0 | 0 | 0 | 19 | 25 | 1000 | 1000 | 1000 | 15267 | 0 | 349 | 398 | 394 | 221 | 3 | 232 | 1000 | 1000 | 1000 | 394 | 394 | 1 | 1 | 1001 | 0 | 1000 | 1000 | 0 | 1019 | 20 | 0 | 1060 | 0 | 0 | 1 | 61 | 1040 | 6 | 1 | 58 | 0 | 19 | 1 | 73 | 2 | 16 | 2 | 2 | 400 | 13 | 0 | 0 | 1000 | 404 | 404 | 382 | 403 | 404 |
| 1004 | 405 | 3 | 1 | 1 | 0 | 0 | 0 | 0 | 45 | 1 | 0 | 1 | 390 | 3 | 0 | 1 | 20 | 25 | 1000 | 1000 | 1000 | 15274 | 0 | 373 | 398 | 398 | 221 | 3 | 232 | 1000 | 1000 | 1000 | 396 | 394 | 1 | 1 | 1001 | 0 | 1000 | 1000 | 0 | 1000 | 0 | 43 | 1039 | 0 | 0 | 0 | 38 | 1039 | 6 | 1 | 39 | 0 | 0 | 0 | 73 | 2 | 16 | 2 | 2 | 391 | 0 | 0 | 4 | 1000 | 400 | 375 | 400 | 399 | 399 |
| 1004 | 377 | 3 | 0 | 0 | 0 | 0 | 0 | 0 | 53 | 1 | 0 | 1 | 388 | 2 | 0 | 0 | 19 | 25 | 1000 | 1000 | 1000 | 16088 | 0 | 373 | 398 | 374 | 217 | 3 | 256 | 1000 | 1000 | 1000 | 398 | 394 | 1 | 1 | 1001 | 0 | 1000 | 1000 | 0 | 1020 | 20 | 43 | 1058 | 1 | 0 | 0 | 21 | 1037 | 6 | 1 | 0 | 43 | 0 | 0 | 73 | 2 | 16 | 2 | 2 | 391 | 0 | 13 | 5 | 1000 | 404 | 404 | 404 | 383 | 383 |
| 1004 | 381 | 3 | 1 | 1 | 0 | 1 | 1 | 1 | 0 | 0 | 0 | 1 | 398 | 0 | 7 | 7 | 1 | 25 | 1000 | 1000 | 1000 | 15274 | 0 | 349 | 374 | 374 | 197 | 3 | 256 | 1000 | 1000 | 1000 | 398 | 394 | 1 | 1 | 1001 | 0 | 1000 | 1000 | 1 | 1000 | 0 | 43 | 1038 | 0 | 0 | 0 | 38 | 1000 | 0 | 1 | 38 | 44 | 0 | 0 | 73 | 2 | 16 | 2 | 2 | 395 | 0 | 13 | 5 | 1000 | 375 | 376 | 399 | 375 | 375 |
| 1004 | 374 | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 46 | 1 | 0 | 0 | 387 | 2 | 7 | 7 | 19 | 25 | 1000 | 1000 | 1000 | 15508 | 0 | 356 | 403 | 402 | 225 | 3 | 260 | 1000 | 1000 | 1000 | 398 | 394 | 1 | 1 | 1001 | 0 | 1000 | 1000 | 0 | 1000 | 0 | 43 | 1038 | 0 | 0 | 0 | 0 | 1000 | 6 | 1 | 39 | 0 | 0 | 0 | 73 | 2 | 16 | 2 | 2 | 371 | 0 | 0 | 7 | 1000 | 399 | 399 | 375 | 399 | 399 |
| 1004 | 398 | 3 | 0 | 0 | 0 | 0 | 0 | 0 | 44 | 1 | 0 | 0 | 387 | 2 | 7 | 7 | 19 | 25 | 1000 | 1000 | 1000 | 15315 | 0 | 349 | 374 | 374 | 221 | 3 | 232 | 1000 | 1000 | 1000 | 398 | 394 | 1 | 1 | 1001 | 0 | 1000 | 1000 | 0 | 1020 | 19 | 0 | 1059 | 1 | 0 | 1 | 61 | 1041 | 6 | 0 | 39 | 0 | 0 | 0 | 73 | 2 | 16 | 2 | 2 | 371 | 0 | 0 | 4 | 1000 | 375 | 375 | 375 | 375 | 399 |
| 1004 | 398 | 3 | 0 | 0 | 0 | 0 | 0 | 0 | 44 | 1 | 0 | 1 | 388 | 0 | 1 | 1 | 16 | 25 | 1000 | 1000 | 1000 | 14989 | 0 | 349 | 374 | 374 | 221 | 3 | 256 | 1000 | 1000 | 1000 | 398 | 394 | 1 | 1 | 1001 | 0 | 1000 | 1000 | 0 | 1020 | 19 | 44 | 1059 | 1 | 0 | 1 | 61 | 1040 | 6 | 0 | 19 | 43 | 19 | 1 | 73 | 2 | 16 | 2 | 2 | 400 | 13 | 0 | 5 | 1000 | 404 | 403 | 404 | 382 | 404 |
Chain cycles: 3
Code:
ldr s0, [x6, #8] fmov x0, d0 eor x8, x8, x0 eor x8, x8, x0 add x6, x6, x8
mov x0, 1 mov x1, 2 mov x8, 0
(fused SUBS/B.cc loop)
Result (median cycles for code, minus 3 chain cycles): 9.0074
| retire uop (01) | cycle (02) | 03 | l1d tlb fill (05) | mmu table walk data (08) | 0e | 0f | 18 | 19 | 1e | 22 | 23 | 24 | 3a | 3f | 4d | 4f | 51 | schedule uop (52) | schedule int uop (53) | schedule simd uop (54) | schedule ldst uop (55) | dispatch int uop (56) | dispatch simd uop (57) | dispatch ldst uop (58) | int uops in schedulers (59) | simd uops in schedulers (5a) | ldst uops in schedulers (5b) | 60 | 69 | 6d | 6e | map stall dispatch (70) | map rewind (75) | map stall (76) | dispatch uop (78) | map int uop (7c) | map ldst uop (7d) | map simd uop (7e) | map int uop inputs (7f) | map ldst uop inputs (80) | map simd uop inputs (81) | 82 | 83 | flush restart other nonspec (84) | 85 | inst all (8c) | inst branch (8d) | inst branch taken (90) | inst branch cond (94) | inst int alu (97) | inst simd load (98) | inst ldst (9b) | 9d | 9f | l1d tlb access (a0) | l1d tlb miss (a1) | l1d cache miss ld (a3) | ld unit uop (a6) | l1d cache writeback (a8) | a9 | ac | af | b5 | bb | l1d cache miss ld nonspec (bf) | l1d tlb miss nonspec (c1) | c2 | branch cond mispred nonspec (c5) | branch mispred nonspec (cb) | cf | d5 | map dispatch bubble (d6) | dd | fetch restart (de) | e0 | ? int output thing (e9) | ea | eb | ec | ? ldst retires (ed) | ? int retires (ef) | f5 | f6 | f7 | f8 | fd |
| 50205 | 120057 | 899 | 0 | 0 | 0 | 1 | 0 | 0 | 6 | 1 | 0 | 0 | 0 | 120020 | 119493 | 109467 | 25 | 60103 | 40102 | 10000 | 10000 | 30100 | 10000 | 10000 | 1078862 | 5736380 | 6136317 | 1 | 120011 | 120077 | 120071 | 113146 | 3 | 113668 | 50100 | 30200 | 10000 | 10000 | 60200 | 10000 | 10000 | 120051 | 120054 | 1 | 1 | 50201 | 100 | 99 | 100 | 40100 | 10000 | 10000 | 1 | 100 | 10000 | 0 | 0 | 10000 | 0 | 0 | 0 | 10000 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 3210 | 1 | 107 | 1 | 1 | 119658 | 40002 | 13 | 10 | 12 | 10000 | 40100 | 120055 | 120055 | 120055 | 120055 | 120055 |
| 50204 | 120051 | 899 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 120039 | 119513 | 109467 | 25 | 60103 | 40102 | 10001 | 10000 | 30100 | 10000 | 10000 | 1079035 | 5735455 | 6136317 | 0 | 120011 | 120094 | 120053 | 113149 | 3 | 113671 | 50100 | 30200 | 10000 | 10000 | 60200 | 10000 | 10000 | 120035 | 120035 | 1 | 1 | 50201 | 100 | 99 | 100 | 40100 | 10000 | 10000 | 0 | 100 | 10000 | 0 | 1 | 10000 | 0 | 0 | 3 | 10000 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 3210 | 1 | 107 | 1 | 1 | 119646 | 40000 | 13 | 10 | 9 | 10000 | 40100 | 120036 | 120036 | 120055 | 120052 | 120055 |
| 50204 | 120054 | 899 | 0 | 0 | 0 | 0 | 0 | 0 | 6 | 0 | 0 | 0 | 0 | 120020 | 119510 | 109449 | 25 | 60103 | 40100 | 10001 | 10000 | 30100 | 10000 | 10000 | 1078862 | 5736236 | 6136317 | 1 | 120030 | 120090 | 120096 | 113141 | 3 | 113671 | 50100 | 30200 | 10000 | 10000 | 60200 | 10000 | 10000 | 120054 | 120054 | 1 | 1 | 50201 | 100 | 99 | 100 | 40100 | 10000 | 10000 | 0 | 100 | 10000 | 0 | 0 | 10000 | 0 | 0 | 0 | 10000 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 3210 | 1 | 107 | 1 | 1 | 119661 | 40000 | 0 | 13 | 0 | 10000 | 40100 | 120055 | 120055 | 120036 | 120052 | 120055 |
| 50204 | 120051 | 899 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 120020 | 119513 | 109467 | 25 | 60100 | 40100 | 10001 | 10000 | 30100 | 10000 | 10000 | 1079035 | 5736380 | 6134461 | 0 | 120030 | 120121 | 120084 | 113141 | 3 | 113671 | 50100 | 30200 | 10000 | 10000 | 60200 | 10000 | 10000 | 120051 | 120035 | 1 | 1 | 50201 | 100 | 99 | 100 | 40100 | 10000 | 10000 | 0 | 100 | 10000 | 0 | 1 | 10000 | 0 | 0 | 0 | 10000 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 3210 | 1 | 107 | 1 | 1 | 119646 | 40000 | 0 | 13 | 12 | 10000 | 40100 | 120055 | 120060 | 120055 | 120055 | 120036 |
| 50204 | 120054 | 899 | 0 | 0 | 0 | 0 | 0 | 0 | 10 | 0 | 0 | 0 | 0 | 120039 | 119513 | 109467 | 25 | 60103 | 40100 | 10000 | 10000 | 30100 | 10000 | 10000 | 1079035 | 5736380 | 6136317 | 1 | 120030 | 120109 | 120053 | 113146 | 3 | 113658 | 50100 | 30200 | 10000 | 10000 | 60200 | 10000 | 10000 | 120054 | 120051 | 1 | 1 | 50201 | 100 | 99 | 100 | 40100 | 10000 | 10000 | 0 | 100 | 10000 | 0 | 0 | 10000 | 0 | 0 | 0 | 10000 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 3210 | 1 | 107 | 1 | 1 | 119658 | 40000 | 0 | 13 | 9 | 10000 | 40100 | 120052 | 120036 | 120052 | 120052 | 120052 |
| 50204 | 120054 | 899 | 0 | 0 | 0 | 0 | 0 | 0 | 6 | 0 | 0 | 0 | 0 | 120036 | 119510 | 109464 | 25 | 60103 | 40100 | 10001 | 10000 | 30100 | 10000 | 10000 | 1079008 | 5737101 | 6138392 | 0 | 120030 | 120108 | 120069 | 113149 | 3 | 113756 | 50100 | 30200 | 10000 | 10000 | 60200 | 10000 | 10000 | 120035 | 120035 | 1 | 1 | 50201 | 100 | 99 | 100 | 40100 | 10000 | 10000 | 0 | 100 | 10000 | 0 | 0 | 10000 | 0 | 0 | 0 | 10000 | 1 | 0 | 1 | 0 | 4 | 0 | 0 | 3210 | 1 | 107 | 1 | 1 | 119662 | 40002 | 0 | 10 | 0 | 10000 | 40100 | 120036 | 120052 | 120036 | 120052 | 120055 |
| 50204 | 120051 | 899 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 120022 | 119513 | 109449 | 25 | 60103 | 40102 | 10001 | 10000 | 30100 | 10000 | 10000 | 1079035 | 5735455 | 6134461 | 0 | 120027 | 120081 | 120059 | 113149 | 3 | 113668 | 50100 | 30200 | 10000 | 10000 | 60200 | 10000 | 10000 | 120054 | 120035 | 1 | 1 | 50201 | 100 | 99 | 100 | 40100 | 10000 | 10000 | 0 | 100 | 10000 | 0 | 1 | 10000 | 0 | 0 | 0 | 10000 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3210 | 2 | 107 | 1 | 1 | 119658 | 40002 | 10 | 10 | 0 | 10000 | 40100 | 120055 | 120052 | 120036 | 120036 | 120055 |
| 50204 | 120102 | 899 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 120020 | 119493 | 109467 | 25 | 60103 | 40100 | 10001 | 10000 | 30100 | 10062 | 10000 | 1079026 | 5736380 | 6134461 | 0 | 120030 | 120079 | 120064 | 113149 | 3 | 113668 | 50100 | 30200 | 10000 | 10000 | 60200 | 10000 | 10000 | 120054 | 120051 | 1 | 1 | 50201 | 100 | 99 | 100 | 40100 | 10000 | 10000 | 0 | 100 | 10000 | 0 | 1 | 10000 | 0 | 0 | 0 | 10000 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 3210 | 1 | 107 | 1 | 1 | 119658 | 40002 | 13 | 10 | 12 | 10000 | 40100 | 120055 | 120055 | 120036 | 120036 | 120055 |
| 50204 | 120035 | 900 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 120039 | 119513 | 109449 | 25 | 60103 | 40102 | 10000 | 10000 | 30100 | 10000 | 10000 | 1079035 | 5735455 | 6136317 | 0 | 120030 | 120097 | 120066 | 113141 | 3 | 113658 | 50100 | 30200 | 10000 | 10000 | 60200 | 10000 | 10000 | 120035 | 120051 | 1 | 1 | 50201 | 100 | 99 | 100 | 40100 | 10000 | 10000 | 0 | 100 | 10000 | 0 | 1 | 10000 | 0 | 0 | 0 | 10000 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 3210 | 1 | 25 | 1 | 1 | 119661 | 40002 | 13 | 0 | 12 | 10000 | 40100 | 120055 | 120055 | 120055 | 120055 | 120060 |
| 50204 | 120051 | 899 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 0 | 0 | 120039 | 119513 | 109464 | 25 | 60103 | 40102 | 10001 | 10000 | 30100 | 10000 | 10000 | 1079182 | 5739164 | 6136730 | 0 | 120011 | 120035 | 120054 | 113149 | 3 | 113671 | 50100 | 30200 | 10000 | 10000 | 60200 | 10000 | 10000 | 120051 | 120035 | 1 | 1 | 50201 | 100 | 99 | 100 | 40100 | 10000 | 10000 | 0 | 100 | 10000 | 0 | 0 | 10000 | 0 | 0 | 0 | 10000 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 3210 | 1 | 101 | 1 | 1 | 119664 | 40002 | 10 | 0 | 9 | 10000 | 40100 | 120055 | 120036 | 120060 | 120036 | 120055 |
Result (median cycles for code, minus 3 chain cycles): 9.0053
| retire uop (01) | cycle (02) | 03 | l1d tlb fill (05) | mmu table walk data (08) | 09 | l2 tlb miss data (0b) | 0e | 0f | 18 | 19 | 1e | 1f | 22 | 24 | 3a | 3f | 4d | 4f | 51 | schedule uop (52) | schedule int uop (53) | schedule simd uop (54) | schedule ldst uop (55) | dispatch int uop (56) | dispatch simd uop (57) | dispatch ldst uop (58) | int uops in schedulers (59) | simd uops in schedulers (5a) | ldst uops in schedulers (5b) | 60 | 61 | 69 | 6d | 6e | map stall dispatch (70) | int prf full (71) | map rewind (75) | map stall (76) | dispatch uop (78) | map int uop (7c) | map ldst uop (7d) | map simd uop (7e) | map int uop inputs (7f) | map ldst uop inputs (80) | map simd uop inputs (81) | 82 | 83 | flush restart other nonspec (84) | 85 | inst all (8c) | inst branch (8d) | inst branch taken (90) | inst branch cond (94) | inst int alu (97) | inst simd load (98) | inst ldst (9b) | 9f | l1d tlb access (a0) | l1d tlb miss (a1) | l1d cache miss ld (a3) | ld unit uop (a6) | l1d cache writeback (a8) | a9 | ac | af | b5 | bb | l1d cache miss ld nonspec (bf) | l1d tlb miss nonspec (c1) | c2 | cf | d0 | d5 | map dispatch bubble (d6) | dd | fetch restart (de) | e0 | ? int output thing (e9) | ea | eb | ec | ? ldst retires (ed) | ? int retires (ef) | f5 | f6 | f7 | f8 | fd |
| 50025 | 120053 | 899 | 1 | 0 | 1 | 1 | 0 | 1 | 0 | 0 | 272 | 0 | 0 | 0 | 0 | 120041 | 119499 | 109469 | 25 | 60016 | 40014 | 10002 | 10000 | 30010 | 10000 | 10000 | 1079602 | 5736620 | 6133764 | 1 | 9 | 120057 | 120056 | 120100 | 113216 | 0 | 3 | 113680 | 50010 | 30020 | 10000 | 10000 | 60020 | 10000 | 10000 | 120041 | 120053 | 1 | 1 | 50021 | 10 | 9 | 10 | 40010 | 10000 | 10000 | 10 | 10002 | 2 | 1 | 10002 | 0 | 1 | 1 | 10000 | 1 | 1 | 0 | 1 | 1 | 3140 | 9 | 9 | 107 | 4 | 4 | 119671 | 40004 | 9 | 6 | 8 | 10000 | 40010 | 120057 | 120042 | 120057 | 120042 | 120042 |
| 50024 | 120041 | 899 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 44 | 0 | 0 | 0 | 0 | 120041 | 119514 | 109466 | 25 | 60013 | 40014 | 10002 | 10000 | 30010 | 10000 | 10000 | 1079463 | 5736476 | 6133764 | 1 | 9 | 120032 | 120056 | 120067 | 113171 | 0 | 3 | 113692 | 50010 | 30020 | 10000 | 10000 | 60020 | 10000 | 10000 | 120041 | 120041 | 1 | 1 | 50021 | 10 | 9 | 10 | 40010 | 10000 | 10000 | 10 | 10002 | 2 | 1 | 10002 | 0 | 1 | 1 | 10000 | 0 | 1 | 1 | 1 | 1 | 3140 | 9 | 3 | 107 | 3 | 4 | 119668 | 40004 | 9 | 9 | 5 | 10000 | 40010 | 120042 | 120057 | 120057 | 120042 | 120054 |
| 50024 | 120053 | 899 | 1 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 74 | 0 | 0 | 0 | 0 | 120041 | 119499 | 109455 | 25 | 60016 | 40014 | 10002 | 10000 | 30010 | 10000 | 10000 | 1079463 | 5736476 | 6133764 | 1 | 9 | 120031 | 120056 | 120053 | 113218 | 0 | 3 | 113695 | 50010 | 30020 | 10000 | 10000 | 60020 | 10000 | 10000 | 120056 | 120041 | 1 | 1 | 50021 | 10 | 9 | 10 | 40010 | 10000 | 10000 | 10 | 10001 | 1 | 1 | 10003 | 0 | 1 | 1 | 10000 | 0 | 1 | 1 | 1 | 1 | 3140 | 9 | 3 | 107 | 3 | 4 | 119656 | 40004 | 6 | 9 | 8 | 10000 | 40010 | 120057 | 120042 | 120057 | 120057 | 120042 |
| 50024 | 120041 | 899 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 59 | 0 | 1 | 0 | 0 | 120026 | 119499 | 109466 | 25 | 60016 | 40014 | 10002 | 10000 | 30010 | 10000 | 10000 | 1079463 | 5736332 | 6133764 | 1 | 9 | 120029 | 120056 | 120056 | 113171 | 0 | 3 | 113695 | 50010 | 30020 | 10000 | 10000 | 60020 | 10000 | 10000 | 120056 | 120041 | 1 | 1 | 50021 | 10 | 9 | 10 | 40010 | 10000 | 10000 | 10 | 10001 | 2 | 0 | 10002 | 0 | 2 | 1 | 10000 | 0 | 1 | 0 | 1 | 0 | 3140 | 9 | 4 | 107 | 4 | 3 | 119668 | 40002 | 9 | 9 | 8 | 10000 | 40010 | 120054 | 120054 | 120057 | 120054 | 120054 |
| 50024 | 120053 | 899 | 1 | 1 | 1 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 0 | 0 | 120026 | 119514 | 109469 | 25 | 60013 | 40014 | 10002 | 10000 | 30010 | 10000 | 10055 | 1079589 | 5735750 | 6133216 | 1 | 9 | 120032 | 120053 | 120056 | 113171 | 0 | 3 | 113695 | 50010 | 30020 | 10000 | 10000 | 60020 | 10000 | 10000 | 120041 | 120053 | 1 | 1 | 50021 | 10 | 9 | 10 | 40010 | 10000 | 10000 | 10 | 10003 | 2 | 0 | 10001 | 1 | 1 | 1 | 10000 | 1 | 1 | 1 | 1 | 0 | 3140 | 9 | 6 | 107 | 4 | 3 | 119671 | 40004 | 9 | 9 | 8 | 10000 | 40010 | 120057 | 120042 | 120042 | 120042 | 120054 |
| 50025 | 120041 | 899 | 1 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 2 | 0 | 1 | 0 | 0 | 120038 | 119556 | 109469 | 25 | 60024 | 40012 | 10002 | 10000 | 30010 | 10000 | 10000 | 1079463 | 5736476 | 6133764 | 1 | 9 | 120032 | 120041 | 120041 | 113171 | 0 | 3 | 113680 | 50010 | 30020 | 10000 | 10000 | 60020 | 10000 | 10000 | 120046 | 120041 | 1 | 1 | 50021 | 10 | 9 | 10 | 40010 | 10000 | 10000 | 10 | 10003 | 1 | 1 | 10002 | 0 | 1 | 4 | 10000 | 1 | 1 | 1 | 1 | 2 | 3140 | 9 | 4 | 107 | 4 | 3 | 119671 | 40004 | 9 | 0 | 0 | 10000 | 40010 | 120057 | 120042 | 120057 | 120042 | 120057 |
| 50024 | 120041 | 900 | 1 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 14 | 0 | 1 | 0 | 1 | 120038 | 119499 | 109469 | 25 | 60016 | 40012 | 10002 | 10000 | 30010 | 10000 | 10000 | 1079463 | 5735750 | 6133764 | 1 | 9 | 120029 | 120056 | 120041 | 113171 | 0 | 3 | 113692 | 50010 | 30020 | 10000 | 10000 | 60020 | 10000 | 10000 | 120056 | 120041 | 1 | 1 | 50021 | 10 | 9 | 10 | 40010 | 10000 | 10000 | 10 | 10003 | 3 | 0 | 10003 | 0 | 1 | 7 | 10000 | 1 | 1 | 1 | 1 | 1 | 3140 | 9 | 6 | 107 | 7 | 4 | 119656 | 40004 | 0 | 9 | 0 | 10000 | 40010 | 120042 | 120057 | 120057 | 120042 | 120057 |
| 50024 | 120056 | 899 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 7 | 0 | 1 | 0 | 0 | 120026 | 119514 | 109455 | 25 | 60016 | 40014 | 10001 | 10000 | 30010 | 10000 | 10000 | 1079575 | 5736476 | 6133216 | 1 | 9 | 120032 | 120056 | 120056 | 113234 | 0 | 3 | 113695 | 50010 | 30020 | 10000 | 10000 | 60020 | 10000 | 10000 | 120053 | 120053 | 1 | 1 | 50021 | 10 | 9 | 10 | 40010 | 10000 | 10000 | 10 | 10001 | 2 | 1 | 10002 | 0 | 0 | 1 | 10000 | 1 | 1 | 1 | 1 | 0 | 3140 | 9 | 4 | 107 | 4 | 6 | 119671 | 40004 | 0 | 9 | 8 | 10000 | 40010 | 120057 | 120042 | 120057 | 120057 | 120054 |
| 50024 | 120053 | 899 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 62 | 0 | 0 | 0 | 0 | 120038 | 119511 | 109455 | 25 | 60016 | 40014 | 10002 | 10000 | 30010 | 10000 | 10000 | 1079602 | 5735750 | 6133764 | 1 | 9 | 120017 | 120061 | 120053 | 113171 | 0 | 3 | 113680 | 50010 | 30020 | 10000 | 10000 | 60020 | 10000 | 10000 | 120053 | 120053 | 1 | 1 | 50021 | 10 | 9 | 10 | 40010 | 10000 | 10000 | 10 | 10001 | 2 | 0 | 10003 | 0 | 2 | 1 | 10000 | 1 | 1 | 1 | 1 | 1 | 3140 | 9 | 4 | 107 | 4 | 4 | 119671 | 40002 | 9 | 6 | 8 | 10000 | 40010 | 120042 | 120057 | 120042 | 120057 | 120057 |
| 50024 | 120056 | 899 | 1 | 1 | 1 | 0 | 1 | 1 | 0 | 0 | 50 | 0 | 1 | 0 | 1 | 120026 | 119499 | 109455 | 25 | 60016 | 40012 | 10002 | 10000 | 30010 | 10000 | 10000 | 1079593 | 5736332 | 6133764 | 1 | 9 | 120032 | 120041 | 120041 | 113171 | 0 | 3 | 113692 | 50010 | 30020 | 10000 | 10000 | 60020 | 10000 | 10000 | 120041 | 120053 | 1 | 1 | 50021 | 10 | 9 | 10 | 40010 | 10000 | 10000 | 10 | 10001 | 2 | 1 | 10001 | 0 | 0 | 1 | 10000 | 1 | 1 | 1 | 1 | 0 | 3140 | 9 | 3 | 107 | 3 | 4 | 119668 | 40002 | 9 | 9 | 8 | 10000 | 40010 | 120057 | 120042 | 120054 | 120042 | 120042 |
Count: 8
Code:
ldr s0, [x6, #8] ldr s0, [x6, #8] ldr s0, [x6, #8] ldr s0, [x6, #8] ldr s0, [x6, #8] ldr s0, [x6, #8] ldr s0, [x6, #8] ldr s0, [x6, #8]
mov x7, x6 mov x8, x6 mov x9, x6 mov x10, x6 mov x11, x6 mov x12, x6 mov x13, x6
(fused SUBS/B.cc loop)
Result (median cycles for code divided by count): 0.3341
| retire uop (01) | cycle (02) | 03 | l1i tlb fill (04) | mmu table walk instruction (07) | mmu table walk data (08) | 09 | l2 tlb miss instruction (0a) | l2 tlb miss data (0b) | 0e | 0f | 18 | 19 | 1e | 1f | 22 | 23 | 3a | 3f | 43 | 46 | 49 | 4f | 51 | schedule uop (52) | schedule int uop (53) | schedule ldst uop (55) | dispatch int uop (56) | dispatch ldst uop (58) | int uops in schedulers (59) | simd uops in schedulers (5a) | 60 | 69 | 6d | 6e | map stall dispatch (70) | map rewind (75) | map stall (76) | dispatch uop (78) | map int uop (7c) | map ldst uop (7d) | map int uop inputs (7f) | map ldst uop inputs (80) | 82 | 83 | flush restart other nonspec (84) | 85 | inst all (8c) | inst branch (8d) | inst branch taken (90) | inst branch cond (94) | inst int alu (97) | inst simd load (98) | inst ldst (9b) | 9d | 9f | l1d tlb access (a0) | l1d tlb miss (a1) | l1d cache miss ld (a3) | a5 | ld unit uop (a6) | st unit uop (a7) | l1d cache writeback (a8) | a9 | ac | af | b5 | b6 | bb | l1d cache miss ld nonspec (bf) | c2 | branch cond mispred nonspec (c5) | cf | d5 | map dispatch bubble (d6) | dd | fetch restart (de) | e0 | ? int output thing (e9) | ea | eb | ec | ? ldst retires (ed) | ? int retires (ef) | f5 | f6 | f7 | f8 | fd |
| 80205 | 26728 | 200 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 45 | 0 | 1 | 0 | 1 | 26712 | 2 | 12 | 12 | 16 | 25 | 80100 | 100 | 80000 | 100 | 80000 | 500 | 1165789 | 0 | 26702 | 26727 | 26727 | 16630 | 3 | 16685 | 80100 | 200 | 80000 | 200 | 80000 | 26731 | 26727 | 1 | 1 | 80201 | 100 | 99 | 100 | 100 | 80000 | 80000 | 1 | 100 | 80000 | 0 | 43 | 0 | 80000 | 0 | 0 | 0 | 38 | 80038 | 6 | 1 | 39 | 43 | 0 | 0 | 5110 | 2 | 16 | 2 | 2 | 26733 | 0 | 14 | 10 | 4 | 80000 | 100 | 26732 | 26732 | 26728 | 26728 | 26728 |
| 80204 | 26727 | 200 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 26716 | 2 | 1 | 12 | 0 | 25 | 80100 | 100 | 80000 | 100 | 80000 | 500 | 1167231 | 1 | 26702 | 26727 | 26727 | 16650 | 3 | 16689 | 80100 | 200 | 80000 | 200 | 80000 | 26731 | 26727 | 1 | 1 | 80201 | 100 | 99 | 100 | 100 | 80000 | 80000 | 0 | 100 | 80000 | 0 | 0 | 0 | 80039 | 0 | 0 | 0 | 39 | 80000 | 0 | 1 | 39 | 44 | 0 | 0 | 5110 | 2 | 16 | 2 | 2 | 26724 | 0 | 10 | 10 | 0 | 80000 | 100 | 26708 | 26728 | 26728 | 26728 | 26732 |
| 80204 | 26731 | 200 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 44 | 0 | 1 | 0 | 0 | 26712 | 2 | 12 | 12 | 19 | 25 | 80100 | 100 | 80000 | 100 | 80000 | 500 | 1166525 | 1 | 26702 | 26727 | 26727 | 16650 | 3 | 16685 | 80100 | 200 | 80000 | 200 | 80000 | 26707 | 26727 | 1 | 1 | 80201 | 100 | 99 | 100 | 100 | 80000 | 80000 | 0 | 100 | 80000 | 0 | 43 | 0 | 80038 | 0 | 0 | 0 | 0 | 80000 | 6 | 1 | 39 | 0 | 0 | 0 | 5110 | 2 | 16 | 2 | 2 | 26724 | 0 | 10 | 10 | 4 | 80000 | 100 | 26728 | 26708 | 26708 | 26728 | 26728 |
| 80204 | 26727 | 200 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 44 | 0 | 0 | 0 | 1 | 26712 | 0 | 1 | 0 | 19 | 25 | 80100 | 100 | 80000 | 100 | 80000 | 500 | 1166525 | 0 | 26702 | 26727 | 26727 | 16650 | 3 | 16685 | 80100 | 200 | 80000 | 200 | 80000 | 26727 | 26727 | 1 | 1 | 80201 | 100 | 99 | 100 | 100 | 80000 | 80000 | 0 | 100 | 80000 | 0 | 0 | 0 | 80039 | 0 | 1 | 0 | 42 | 80000 | 6 | 0 | 39 | 43 | 0 | 0 | 5110 | 2 | 16 | 2 | 2 | 26724 | 0 | 0 | 10 | 4 | 80000 | 100 | 26728 | 26728 | 26732 | 26728 | 26728 |
| 80204 | 26707 | 200 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 45 | 0 | 0 | 0 | 1 | 26714 | 2 | 1 | 1 | 19 | 25 | 80100 | 100 | 80000 | 100 | 80000 | 500 | 1167231 | 0 | 26706 | 26727 | 26731 | 16650 | 3 | 16665 | 80100 | 200 | 80000 | 200 | 80000 | 26731 | 26727 | 1 | 1 | 80201 | 100 | 99 | 100 | 100 | 80000 | 80000 | 0 | 100 | 80000 | 0 | 43 | 0 | 80038 | 0 | 0 | 0 | 0 | 80038 | 6 | 1 | 39 | 0 | 0 | 0 | 5110 | 2 | 16 | 2 | 2 | 27135 | 0 | 14 | 10 | 4 | 80000 | 100 | 26728 | 26728 | 26728 | 26708 | 26708 |
| 80204 | 26731 | 200 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 0 | 45 | 0 | 0 | 0 | 1 | 26728 | 2 | 1 | 12 | 0 | 25 | 80100 | 100 | 80000 | 100 | 80000 | 500 | 1177038 | 1 | 26702 | 26727 | 26727 | 16654 | 3 | 16685 | 80100 | 200 | 80000 | 200 | 80000 | 26727 | 26727 | 1 | 1 | 80201 | 100 | 99 | 100 | 100 | 80000 | 80000 | 0 | 100 | 80000 | 0 | 43 | 0 | 80039 | 0 | 0 | 0 | 39 | 80039 | 6 | 1 | 39 | 44 | 0 | 0 | 5110 | 2 | 16 | 2 | 2 | 26732 | 0 | 0 | 10 | 4 | 80000 | 100 | 26708 | 26732 | 26732 | 26708 | 26728 |
| 80204 | 26727 | 200 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 44 | 0 | 0 | 0 | 1 | 26716 | 2 | 12 | 0 | 16 | 25 | 80100 | 100 | 80000 | 100 | 80000 | 500 | 1167127 | 0 | 26706 | 26731 | 26731 | 16654 | 3 | 16689 | 80100 | 200 | 80000 | 200 | 80000 | 26707 | 26727 | 1 | 1 | 80201 | 100 | 99 | 100 | 100 | 80000 | 80000 | 0 | 100 | 80000 | 0 | 43 | 0 | 80039 | 0 | 0 | 0 | 39 | 80039 | 0 | 0 | 0 | 43 | 0 | 0 | 5110 | 2 | 16 | 2 | 2 | 26727 | 0 | 14 | 10 | 7 | 80000 | 100 | 26708 | 26728 | 26708 | 26728 | 26708 |
| 80204 | 26727 | 200 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 45 | 0 | 1 | 0 | 1 | 26712 | 2 | 12 | 1 | 16 | 25 | 80100 | 100 | 80000 | 100 | 80000 | 500 | 1167231 | 1 | 26702 | 26731 | 26707 | 16654 | 3 | 16685 | 80100 | 200 | 80000 | 200 | 80000 | 26727 | 26727 | 1 | 1 | 80201 | 100 | 99 | 100 | 100 | 80000 | 80000 | 0 | 100 | 80000 | 0 | 43 | 0 | 80000 | 0 | 0 | 0 | 39 | 80000 | 6 | 1 | 39 | 43 | 0 | 0 | 5110 | 2 | 16 | 2 | 2 | 26724 | 0 | 10 | 10 | 7 | 80000 | 100 | 26732 | 26708 | 26728 | 26732 | 26708 |
| 80204 | 26731 | 200 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 44 | 0 | 0 | 0 | 0 | 26712 | 2 | 12 | 0 | 16 | 25 | 80100 | 100 | 80000 | 100 | 80000 | 500 | 1165789 | 0 | 26682 | 26707 | 26727 | 16650 | 3 | 16685 | 80100 | 200 | 80000 | 200 | 80000 | 26727 | 26727 | 1 | 1 | 80201 | 100 | 99 | 100 | 100 | 80000 | 80000 | 0 | 100 | 80000 | 0 | 43 | 0 | 80038 | 0 | 1 | 0 | 39 | 80000 | 6 | 0 | 39 | 43 | 0 | 0 | 5110 | 2 | 16 | 2 | 2 | 26724 | 0 | 10 | 10 | 7 | 80000 | 100 | 26728 | 26708 | 26728 | 26708 | 26732 |
| 80204 | 26727 | 200 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 0 | 45 | 0 | 1 | 0 | 1 | 26902 | 2 | 12 | 1 | 0 | 25 | 80100 | 100 | 80000 | 100 | 80000 | 500 | 1167127 | 0 | 26702 | 26727 | 26731 | 16654 | 3 | 16685 | 80100 | 200 | 80000 | 200 | 80000 | 26727 | 26727 | 1 | 1 | 80201 | 100 | 99 | 100 | 100 | 80000 | 80000 | 1 | 100 | 80000 | 0 | 43 | 0 | 80000 | 0 | 0 | 0 | 629 | 80039 | 0 | 1 | 39 | 43 | 0 | 0 | 5110 | 2 | 16 | 2 | 2 | 26798 | 0 | 14 | 0 | 7 | 80000 | 100 | 26708 | 26732 | 26732 | 26728 | 26728 |
Result (median cycles for code divided by count): 0.3341
| retire uop (01) | cycle (02) | 03 | 0e | 0f | 1e | 22 | 3a | 3f | 43 | 46 | 49 | 4f | 51 | schedule uop (52) | schedule int uop (53) | schedule ldst uop (55) | dispatch int uop (56) | dispatch ldst uop (58) | int uops in schedulers (59) | simd uops in schedulers (5a) | 60 | 69 | 6b | 6d | 6e | map stall dispatch (70) | map rewind (75) | map stall (76) | dispatch uop (78) | map int uop (7c) | map ldst uop (7d) | map int uop inputs (7f) | map ldst uop inputs (80) | 82 | 83 | flush restart other nonspec (84) | 85 | inst all (8c) | inst branch (8d) | inst branch taken (90) | inst branch cond (94) | inst int alu (97) | inst simd load (98) | inst ldst (9b) | 9d | 9f | l1d tlb access (a0) | l1d cache miss ld (a3) | ld unit uop (a6) | l1d cache writeback (a8) | ac | af | b5 | b6 | bb | l1d cache miss ld nonspec (bf) | cf | d5 | map dispatch bubble (d6) | d9 | da | dd | fetch restart (de) | e0 | ea | eb | ec | ? ldst retires (ed) | ? int retires (ef) | f5 | f6 | f7 | f8 | fd |
| 80025 | 26727 | 200 | 0 | 0 | 45 | 1 | 0 | 26693 | 2 | 12 | 12 | 16 | 25 | 80010 | 10 | 80000 | 10 | 80000 | 50 | 1166750 | 1 | 26702 | 0 | 26708 | 26727 | 16659 | 3 | 16707 | 80010 | 20 | 80000 | 20 | 80000 | 26708 | 26727 | 1 | 1 | 80021 | 10 | 9 | 10 | 10 | 80000 | 80000 | 0 | 10 | 80000 | 43 | 80039 | 0 | 38 | 80039 | 6 | 1 | 0 | 43 | 5020 | 11 | 16 | 9 | 0 | 7 | 9 | 26728 | 14 | 10 | 4 | 80000 | 10 | 26709 | 26728 | 26729 | 26728 | 26709 |
| 80024 | 26727 | 200 | 0 | 0 | 0 | 0 | 0 | 26693 | 0 | 12 | 0 | 27 | 25 | 80010 | 10 | 80000 | 10 | 80000 | 50 | 1166886 | 1 | 26703 | 0 | 26708 | 26727 | 16672 | 3 | 16688 | 80010 | 20 | 80000 | 20 | 80000 | 26708 | 26727 | 1 | 1 | 80021 | 10 | 9 | 10 | 10 | 80000 | 80000 | 0 | 10 | 80000 | 43 | 80039 | 0 | 0 | 80039 | 6 | 1 | 39 | 43 | 5020 | 11 | 16 | 8 | 0 | 10 | 8 | 26776 | 0 | 10 | 0 | 80000 | 10 | 26709 | 26709 | 26709 | 26729 | 26728 |
| 80024 | 26727 | 200 | 0 | 0 | 45 | 0 | 0 | 26693 | 2 | 0 | 12 | 0 | 25 | 80010 | 10 | 80000 | 10 | 80000 | 50 | 1168843 | 0 | 26703 | 0 | 26727 | 26727 | 16652 | 3 | 16708 | 80010 | 20 | 80000 | 20 | 80000 | 26728 | 26728 | 1 | 1 | 80021 | 10 | 9 | 10 | 10 | 80000 | 80000 | 0 | 10 | 80000 | 43 | 80038 | 1 | 39 | 80039 | 6 | 1 | 39 | 0 | 5020 | 8 | 16 | 8 | 0 | 7 | 10 | 26705 | 10 | 10 | 4 | 80000 | 10 | 26709 | 26728 | 26731 | 26709 | 26729 |
| 80024 | 26727 | 201 | 0 | 0 | 0 | 0 | 1 | 26716 | 2 | 0 | 0 | 16 | 25 | 80010 | 10 | 80000 | 10 | 80000 | 50 | 1166750 | 0 | 26702 | 3 | 26727 | 26708 | 16676 | 3 | 16688 | 80010 | 20 | 80000 | 20 | 80000 | 26728 | 26727 | 1 | 1 | 80021 | 10 | 9 | 10 | 10 | 80000 | 80000 | 0 | 10 | 80000 | 43 | 80039 | 0 | 0 | 80038 | 6 | 1 | 39 | 43 | 5020 | 9 | 16 | 8 | 0 | 7 | 11 | 27213 | 10 | 0 | 4 | 80000 | 10 | 26732 | 26729 | 26728 | 26728 | 26729 |
| 80024 | 26728 | 200 | 0 | 0 | 45 | 0 | 0 | 26712 | 2 | 0 | 12 | 16 | 25 | 80140 | 10 | 80000 | 10 | 80000 | 50 | 1166750 | 1 | 26702 | 0 | 26727 | 26727 | 16652 | 3 | 16708 | 80010 | 20 | 80000 | 20 | 80000 | 26708 | 26708 | 1 | 1 | 80021 | 10 | 9 | 10 | 10 | 80000 | 80000 | 0 | 10 | 80000 | 0 | 80039 | 0 | 39 | 80039 | 0 | 1 | 39 | 43 | 5020 | 11 | 16 | 8 | 0 | 6 | 10 | 26728 | 10 | 0 | 4 | 80000 | 10 | 26709 | 26728 | 26729 | 26709 | 26729 |
| 80024 | 26708 | 200 | 0 | 0 | 45 | 1 | 1 | 26713 | 2 | 12 | 0 | 16 | 25 | 80010 | 10 | 80000 | 10 | 80000 | 50 | 1166750 | 1 | 26703 | 0 | 26727 | 26727 | 16672 | 3 | 16708 | 80010 | 20 | 80000 | 20 | 80000 | 26727 | 26727 | 1 | 1 | 80021 | 10 | 9 | 10 | 10 | 80000 | 80000 | 0 | 10 | 80000 | 0 | 80000 | 0 | 39 | 80039 | 6 | 1 | 39 | 43 | 5020 | 10 | 16 | 8 | 0 | 10 | 8 | 26724 | 10 | 10 | 4 | 80000 | 10 | 26728 | 26729 | 26709 | 26728 | 26709 |
| 80024 | 26727 | 199 | 0 | 0 | 45 | 1 | 0 | 26712 | 0 | 12 | 0 | 16 | 25 | 80010 | 10 | 80000 | 10 | 80000 | 50 | 1166886 | 0 | 26683 | 0 | 26728 | 26728 | 16672 | 3 | 16688 | 80010 | 20 | 80000 | 20 | 80000 | 26727 | 26728 | 1 | 1 | 80021 | 10 | 9 | 10 | 10 | 80000 | 80000 | 0 | 10 | 80000 | 0 | 80039 | 0 | 0 | 80039 | 6 | 1 | 39 | 43 | 5020 | 10 | 16 | 8 | 0 | 7 | 9 | 26732 | 10 | 10 | 4 | 80000 | 10 | 26728 | 26728 | 26729 | 26709 | 26732 |
| 80024 | 26731 | 200 | 1 | 1 | 45 | 1 | 1 | 26716 | 2 | 12 | 0 | 16 | 25 | 80010 | 10 | 80000 | 10 | 80000 | 50 | 1166896 | 0 | 26702 | 0 | 26727 | 26708 | 16672 | 3 | 16688 | 80010 | 20 | 80000 | 20 | 80000 | 26727 | 26727 | 1 | 1 | 80021 | 10 | 9 | 10 | 10 | 80000 | 80000 | 0 | 10 | 80000 | 0 | 80038 | 0 | 39 | 80040 | 6 | 1 | 0 | 43 | 5020 | 7 | 16 | 8 | 0 | 10 | 10 | 26709 | 0 | 10 | 0 | 80000 | 10 | 26728 | 26709 | 26709 | 26864 | 26728 |
| 80024 | 26708 | 200 | 0 | 0 | 45 | 0 | 1 | 26712 | 2 | 0 | 12 | 16 | 25 | 80010 | 10 | 80000 | 10 | 80000 | 50 | 1166750 | 1 | 26683 | 0 | 26728 | 26708 | 16672 | 3 | 16708 | 80010 | 20 | 80000 | 20 | 80000 | 26727 | 26728 | 1 | 1 | 80021 | 10 | 9 | 10 | 10 | 80000 | 80000 | 0 | 10 | 80000 | 43 | 80000 | 0 | 39 | 80000 | 0 | 1 | 0 | 43 | 5020 | 7 | 16 | 10 | 0 | 10 | 9 | 26728 | 0 | 0 | 4 | 80000 | 10 | 26709 | 26728 | 26709 | 26732 | 26728 |
| 80024 | 26729 | 200 | 0 | 0 | 45 | 1 | 1 | 26712 | 2 | 12 | 12 | 16 | 25 | 80010 | 10 | 80000 | 10 | 80000 | 50 | 1166886 | 1 | 26703 | 0 | 26727 | 26727 | 16652 | 3 | 16708 | 80010 | 20 | 80000 | 20 | 80000 | 26727 | 26727 | 1 | 1 | 80021 | 10 | 9 | 10 | 10 | 80000 | 80000 | 0 | 10 | 80000 | 43 | 80039 | 0 | 0 | 80039 | 0 | 1 | 39 | 43 | 5020 | 6 | 16 | 10 | 0 | 8 | 7 | 26725 | 14 | 0 | 4 | 80000 | 10 | 26709 | 26709 | 26728 | 26709 | 26709 |