Firestorm: LDUR (D) measurements

Code:

  ldur d0, [x6, #1]

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 1.000

SIMD/FP unit issues: 0.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	09	l2 tlb miss data (0b)	0e	0f	1e	22	23	3a	3f	43	46	49	4f	51	schedule uop (52)	schedule ldst uop (55)	dispatch ldst uop (58)	simd uops in schedulers (5a)	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map ldst uop (7d)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	92	inst simd load (98)	inst ldst (9b)	9d	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	st unit uop (a7)	a9	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	ea	eb	ec	? ldst retires (ed)	f5	f6	f7	f8	fd
1005	403	3	1	1	1	1	0	1	67	1	0	3	388	3	7	7	19	25	1000	1000	1000	15524	377	403	402	225	3	257	1000	1000	1000	403	403	1	1	1001	0	1000	1000	1	1020	20	43	1062	1	1	60	1039	6	1	58	43	19	1	73	1	16	1	1	400	13	13	5	1000	404	404	404	404	404
1004	402	3	1	0	1	0	0	0	67	0	0	2	388	3	7	7	19	25	1000	1000	1000	15526	378	402	403	225	3	261	1000	1000	1000	403	403	1	1	1001	0	1000	1000	0	1019	19	43	1059	1	0	61	1039	6	1	59	43	19	1	73	1	16	1	1	400	13	13	5	1000	404	404	407	404	403
1004	403	3	1	1	1	1	0	0	67	0	0	3	388	1	7	7	19	25	1000	1000	1000	15459	378	403	403	225	3	261	1000	1000	1000	403	403	1	1	1001	0	1000	1000	0	1020	19	43	1059	0	1	61	1027	6	1	58	43	19	1	73	1	16	1	1	400	13	13	5	1000	404	404	404	403	404
1004	403	2	1	1	0	1	0	0	66	0	0	2	388	2	7	7	19	25	1000	1000	1000	15506	379	403	405	225	3	261	1000	1000	1000	403	403	1	1	1001	0	1000	1000	0	1020	19	43	1058	1	0	61	1039	6	1	59	43	19	2	73	1	16	1	1	400	13	13	5	1000	404	404	404	403	404
1004	402	3	1	1	1	1	0	0	67	0	0	3	388	3	7	7	20	25	1000	1000	1000	15526	378	402	403	225	3	261	1000	1000	1000	403	402	1	1	1001	0	1000	1000	0	1019	19	43	1058	1	0	60	1039	6	1	59	43	19	2	73	1	16	1	1	400	13	13	5	1000	407	403	404	415	404
1004	403	3	1	1	0	1	0	0	70	1	0	3	389	3	7	7	20	25	1000	1000	1000	15555	401	405	403	225	3	260	1000	1000	1000	403	403	1	1	1001	0	1000	1000	0	1020	19	43	1058	1	0	60	1040	6	1	60	43	19	0	73	1	16	1	1	400	13	13	5	1000	404	403	404	404	404
1004	403	3	1	1	1	1	0	0	66	0	0	3	388	2	7	7	18	25	1000	1000	1000	15567	379	403	402	225	3	261	1000	1000	1000	402	403	1	1	1001	0	1000	1000	0	1020	20	43	1059	0	0	60	1040	6	1	58	43	19	2	73	1	16	1	1	400	13	13	5	1000	403	405	404	404	404
1004	403	3	1	1	0	0	0	0	66	0	0	2	388	2	7	7	20	25	1000	1000	1000	15555	378	403	403	226	3	260	1000	1000	1000	403	402	1	1	1001	0	1000	1000	0	1019	20	43	1058	0	0	61	1040	6	1	59	43	19	0	73	1	16	1	1	400	13	13	5	1000	404	404	404	404	404
1004	403	3	1	1	1	1	0	0	67	0	0	2	387	3	7	7	19	25	1000	1000	1000	15555	378	403	403	254	3	261	1000	1000	1000	403	402	1	1	1001	0	1000	1000	0	1019	19	43	1058	0	0	61	1040	6	1	59	43	19	1	73	1	16	1	1	400	13	13	5	1000	404	404	404	404	404
1004	403	3	1	0	0	1	0	0	66	0	0	2	393	2	7	7	18	25	1000	1000	1000	15555	378	403	403	225	3	262	1000	1000	1000	403	403	1	1	1001	0	1000	1000	0	1020	19	43	1059	0	0	60	1039	6	1	59	45	19	0	73	1	16	1	1	400	13	13	5	1000	404	404	423	404	403

Test 2: Latency 1->2 roundtrip

Chain cycles: 3

Code:

  ldur d0, [x6, #1]
  fmov x0, d0
  eor x8, x8, x0
  eor x8, x8, x0
  add x6, x6, x8

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 9.0056

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	l2 tlb miss data (0b)	0e	0f	18	19	1e	1f	22	23	3a	3f	4d	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	b5	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	branch mispred nonspec (cb)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
50205	120047	899	1	1	1	1	1	0	0	2	0	0	0	0	120038	119515	109466	25	60106	40104	10002	10000	30100	10000	10000	1079242	5736812	6136676	0	120032	120091	120056	113148	3	113673	50100	30200	10000	10000	60200	10000	10000	120059	120053	1	1	50201	100	99	100	40100	10000	10000	0	100	10001	4	0	10003	0	1	2	1	10000	1	1	1	1	1	0	3210	1	135	1	1	119660	40004	9	6	8	10000	40100	120042	120057	120057	120057	120042
50204	120053	899	1	1	0	0	1	0	0	2	0	1	0	0	120041	119515	109455	25	60106	40104	10002	10000	30100	10000	10000	1079026	5735750	6136419	0	120032	120056	120056	113137	3	113630	50100	30200	10000	10000	60200	10000	10000	120053	120053	1	1	50201	100	99	100	40100	10000	10000	0	100	10001	2	0	10002	0	2	1	4	10000	1	1	1	1	0	0	3210	1	107	1	1	119663	40002	9	9	8	10000	40100	120050	120057	120057	120063	120056
50204	120053	900	1	0	1	0	0	0	1	7	0	0	0	1	120026	119513	109455	25	60106	40102	10002	10000	30100	10000	10000	1079053	5736332	6136572	0	120032	120056	120056	113151	3	113673	50100	30200	10000	10000	60200	10000	10000	120056	120053	1	1	50201	100	99	100	40100	10000	10000	0	100	10002	1	1	10003	0	0	1	1	10000	1	1	0	1	0	0	3210	0	107	1	1	119663	40004	9	6	8	10000	40100	120057	120042	120057	120057	120055
50204	120053	899	1	0	0	0	0	0	0	1	0	0	0	1	120038	119515	109469	25	60103	40104	10001	10000	30100	10000	10000	1079026	5736476	6136572	0	120017	120041	120053	113151	3	113670	50100	30200	10000	10000	60200	10000	10000	120056	120053	1	1	50201	100	99	100	40100	10000	10000	0	100	10002	1	0	10003	0	2	0	4	10000	0	1	1	1	1	0	3210	1	135	1	1	119663	40002	0	6	8	10000	40100	120057	120057	120057	120057	120043
50204	120116	899	1	1	1	1	1	0	0	2	0	0	0	0	120041	119515	109469	25	60106	40104	10002	10000	30100	10000	10000	1079053	5736476	6136419	0	120029	120056	120053	113148	3	113630	50100	30200	10000	10000	60200	10000	10000	120056	120041	1	1	50201	100	99	100	40100	10000	10000	0	100	10002	1	1	10002	0	3	0	1	10000	1	1	0	1	1	0	3210	1	135	1	1	119663	40004	6	0	8	10000	40100	120057	120057	120057	120042	120058
50204	120041	899	1	1	1	0	0	0	0	1	0	0	0	0	120038	119535	109469	25	60106	40104	10001	10000	30100	10062	10000	1079053	5736476	6133458	0	120032	120053	120053	113151	3	113673	50100	30200	10000	10000	60200	10000	10000	120056	120041	1	1	50201	100	99	100	40100	10000	10000	0	100	10001	1	1	10004	0	0	0	1	10000	1	0	1	0	0	0	3210	1	107	1	1	119646	40002	0	0	0	10000	40100	120051	120036	120051	120053	120053
50204	120050	899	0	0	0	0	1	0	0	1	0	1	0	0	120035	119509	109449	25	60106	40104	10001	10000	30100	10000	10000	1079026	5736476	6136572	0	120032	120056	120041	113151	3	113673	50100	30200	10000	10000	60200	10000	10000	120041	120041	1	1	50201	100	99	100	40100	10000	10000	0	100	10002	1	1	10003	0	0	0	1	10000	1	1	1	1	0	0	3210	1	135	1	1	119663	40004	9	9	8	10000	40100	120042	120057	120057	120042	120237
50205	120056	900	1	0	0	0	0	0	0	2	0	0	0	0	120041	119515	109469	25	60103	40104	10002	10000	30100	10000	10000	1079097	5736476	6136572	0	120032	120056	120056	113151	3	113630	50100	30200	10000	10000	60200	10000	10000	120056	120041	1	1	50201	100	99	100	40100	10000	10000	0	100	10001	1	1	10003	0	4	2	1	10000	1	1	1	1	1	0	3210	1	135	1	1	119660	40004	9	6	8	10000	40100	120057	120057	120042	120042	120056
50204	120056	899	1	0	0	0	0	0	0	2	0	0	0	0	120041	119515	109455	25	60106	40128	10002	10000	30100	10000	10000	1085906	5736476	6136419	0	120029	120056	120041	113728	3	113673	50100	30200	10000	10000	60200	10000	10000	120061	120064	2	1	50201	100	99	100	40100	10000	10000	0	100	10002	2	1	10002	0	49	0	1	10000	1	1	0	1	0	0	3210	1	107	1	1	119663	40004	9	9	5	10000	40100	120054	120042	120042	120099	120065
50204	120056	899	1	1	0	0	0	0	0	2	0	0	0	0	120041	119515	109466	25	60106	40104	10001	10000	30100	10000	10000	1079053	5736476	6136572	0	120032	120056	120056	113137	3	113673	50100	30200	10000	10000	60200	10000	10000	120056	120053	1	1	50201	100	99	100	40100	10000	10000	1	100	10002	2	1	10002	0	4	0	1	10000	0	1	1	1	0	0	3210	1	135	1	1	119663	40002	6	9	0	10000	40100	120057	120057	120054	120057	120067

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 9.0049

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	09	l2 tlb miss data (0b)	0e	0f	19	1e	1f	22	24	3f	4d	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst ldst (9b)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	ac	af	b5	l1d cache miss ld nonspec (bf)	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
50025	120050	899	0	0	0	0	1	0	61	0	1	0	120035	119508	109464	25	60013	40012	10001	10000	30010	10000	10000	1079548	5736188	6132757	1	120014	120047	120039	113168	3	113674	50010	30020	10000	10000	60020	10000	10000	120050	120047	1	1	50021	10	9	10	40010	10000	10000	10	10000	0	1	10000	0	12	10000	0	1	0	0	3140	3	107	2	3	119662	40000	9	6	8	10000	40010	120051	120051	120051	120051	120051
50024	120051	899	0	1	0	0	0	0	511	108	0	0	120035	119508	109463	25	60013	40012	10001	10000	30010	10000	10000	1079517	5736188	6133499	0	120026	120047	120050	113168	3	113689	50010	30020	10000	10000	60020	10000	10000	120050	120047	1	1	50021	10	9	10	40010	10000	10000	10	10000	0	1	10000	0	0	10000	1	1	0	0	3140	3	107	3	2	119665	40002	6	0	8	10000	40010	120051	120051	120051	120036	120051
50024	120047	900	0	0	0	0	0	0	1	0	1	0	120020	119508	109449	25	60013	40012	10001	10000	30010	10000	10000	1079517	5736044	6132757	0	120026	120050	120050	113168	3	113690	50010	30020	10000	10000	60340	10000	10000	120035	120047	1	1	50021	10	9	10	40010	10000	10000	10	10000	0	0	10006	1	7176	10002	1	1	0	0	3140	2	107	2	4	119841	40019	9	9	8	10000	40010	120036	120051	120051	120036	120048
50024	120047	899	0	1	0	1	1	0	13	0	0	0	120035	119492	109463	25	60013	40012	10001	10000	30010	10000	10000	1079557	5736188	6133499	0	120026	120052	120050	113168	3	113689	50010	30020	10000	10000	60020	10000	10000	120050	120047	1	1	50021	10	9	10	40010	10000	10000	10	10000	0	1	10000	0	147	10000	1	1	0	0	3140	3	107	3	4	119968	40000	9	9	8	10000	40010	120036	120052	120051	120048	120048
50024	120050	899	0	1	0	0	0	0	13	0	1	0	120020	119510	109449	25	60013	40012	10001	10000	30010	10000	10000	1079517	5735455	6133499	1	120026	120050	120050	113168	3	113689	50010	30020	10000	10000	60020	10000	10000	120050	120047	1	1	50021	10	9	10	40010	10000	10000	10	10000	2	1	10000	0	30	10000	0	0	0	0	3140	2	107	3	2	119665	40002	0	9	8	10000	40010	120051	120092	120036	120051	120099
50024	120047	899	0	0	0	0	1	0	9	0	1	0	120020	119508	109463	25	60010	40012	10001	10000	30010	10000	10000	1079548	5736188	6133499	0	120026	120050	120035	113153	3	113689	50010	30020	10000	10000	60020	10000	10000	120035	120047	1	1	50021	10	9	10	40010	10000	10000	10	10000	0	1	10000	0	12	10000	1	1	0	0	3140	3	107	3	3	119665	40000	9	0	8	10000	40010	120036	120048	120052	120048	120051
50024	120035	900	0	0	0	1	1	0	175	0	0	0	120035	119508	109463	25	60013	40010	10000	10000	30010	10000	10000	1079548	5736188	6133499	0	120026	120050	120035	113153	3	113686	50010	30020	10000	10000	60020	10000	10000	120050	120047	1	1	50021	10	9	10	40010	10000	10000	10	10000	0	1	10000	0	12	10000	0	1	0	0	3140	3	107	3	2	119650	40002	9	0	0	10000	40010	120048	120051	120048	120057	120048
50024	120048	899	0	0	0	0	0	0	1	0	0	0	120020	119508	109461	25	60013	40010	10002	10000	30010	10000	10000	1079517	5736044	6133499	1	120011	120050	120035	113153	3	113674	50010	30020	10000	10000	60020	10000	10000	120047	120047	1	1	50021	10	9	10	40010	10000	10000	10	10000	0	0	10000	0	12	10000	1	0	0	0	3140	3	107	2	3	119650	40011	9	0	8	10000	40010	120036	120036	120051	120051	120051
50024	120047	899	0	0	0	0	0	0	0	0	0	0	120035	119508	109449	25	60013	40012	10000	10000	30010	10000	10000	1079548	5736188	6132757	0	120026	120035	120035	113168	3	113689	50010	30020	10000	10000	60020	10000	10000	120050	120047	1	1	50021	10	9	10	40010	10000	10000	10	10000	0	1	10000	0	12	10000	0	1	0	0	3140	3	107	2	3	119650	40002	9	6	8	10000	40010	120036	120036	120051	120051	120051
50024	120054	899	0	0	0	0	0	0	1	0	1	0	120020	119492	109461	25	60010	40012	10000	10000	30010	10000	10000	1079548	5736188	6132757	1	120026	120050	120035	113168	3	113674	50010	30020	10000	10000	60020	10000	10000	120050	120047	1	1	50021	10	9	10	40010	10000	10000	10	10000	0	1	10000	0	9	10000	1	1	0	0	3140	2	107	3	3	119777	40000	6	6	8	10000	40010	120051	120051	120051	120051	120051

Test 3: throughput

Count: 8

Code:

  ldur d0, [x6, #1]
  ldur d0, [x6, #1]
  ldur d0, [x6, #1]
  ldur d0, [x6, #1]
  ldur d0, [x6, #1]
  ldur d0, [x6, #1]
  ldur d0, [x6, #1]
  ldur d0, [x6, #1]

Initialization

  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.3342

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk instruction (07)	mmu table walk data (08)	09	l2 tlb miss data (0b)	0e	0f	19	1e	22	23	3a	3f	43	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	92	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	a5	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
80205	26737	200	1	0	1	1	1	0	0	0	129	1	0	3	26699	3	7	7	23	25	80100	100	80000	100	80000	500	1169868	0	26716	26929	27043	16664	3	16695	80100	200	80000	200	80000	26736	26736	1	1	80201	100	99	0	100	100	80000	80000	0	100	80020	19	43	0	80059	1	12	0	64	80000	6	1	59	43	19	1	5132	4	16	4	4	26733	0	13	5	80000	100	26737	26738	26737	26958	26920
80204	26743	200	1	1	0	1	1	1	1	1	67	1	0	3	26721	0	7	0	4	25	80100	100	80000	100	80000	500	1167815	0	26689	26736	26736	16658	3	16694	80100	200	80000	200	80000	26740	26714	1	1	80201	100	99	0	100	100	80000	80000	0	100	80019	19	0	0	80059	0	32	1	954	80040	6	1	59	43	19	1	5110	4	25	8	3	26711	13	0	5	80000	100	26737	26738	26737	26737	26783
80204	26724	200	1	0	1	1	0	0	0	0	67	0	0	1	26721	0	7	0	22	25	80100	100	80000	100	80000	500	1167446	0	26711	26740	26737	16637	3	16675	80100	200	80000	200	80000	26736	26737	1	1	80201	100	99	0	100	100	80000	80000	0	100	80019	19	0	0	80059	1	63	1	70	80040	0	0	59	43	19	2	5110	3	16	3	4	26733	13	0	5	80000	100	26738	26844	26797	26871	26754
80204	26740	200	1	0	0	1	1	0	0	0	76	1	0	4	26699	2	7	0	20	25	80100	100	80000	100	80000	500	1167514	0	26689	26736	26736	16663	3	16695	80100	200	80000	200	80000	26736	26714	1	1	80201	100	99	0	100	100	80000	80000	0	100	80019	19	0	0	80058	2	2	0	906	80170	6	0	59	43	19	1	5110	5	16	3	5	26870	13	13	0	80000	100	26902	26822	27027	27130	27352
80204	26745	201	1	0	0	0	1	0	0	0	79	1	0	3	26721	0	7	7	19	25	80100	100	80000	100	80000	500	1167768	0	26711	26737	26714	16659	3	16672	80100	200	80000	200	80000	26737	26736	1	1	80201	100	99	0	100	100	80000	80000	0	100	80022	19	0	0	80059	1	3	1	63	80040	6	0	19	0	19	1	5110	4	16	6	6	26733	0	0	5	80000	100	26741	26983	26740	26724	26742
80204	26736	200	1	0	1	0	1	0	0	0	67	1	0	3	26721	3	7	7	0	25	80100	100	80000	100	80000	500	1167555	0	26711	26714	26736	16637	3	16694	80100	200	80000	200	80000	26740	26736	1	1	80201	100	99	0	100	100	80000	80000	1	100	80020	19	43	0	80059	1	5	1	79	80039	0	0	59	43	19	1	5110	3	16	4	4	26711	0	0	5	80000	100	26741	26737	26737	26715	26769
80204	26749	200	1	0	1	0	1	0	0	0	67	0	0	3	26722	3	7	0	1	25	80100	100	80000	100	80000	500	1166758	0	26711	26736	26736	16658	3	16695	80100	200	80000	200	80000	26736	26736	1	1	80201	100	99	0	100	100	80000	80000	0	100	80149	19	43	98	80449	1	4	0	61	80000	0	1	59	43	19	0	5110	4	16	3	4	26740	13	0	5	80000	100	26737	27002	26753	26830	26737
80204	26714	200	1	0	1	1	1	0	0	0	21	0	0	3	26721	3	0	7	23	25	80100	100	80000	100	80000	500	1167764	0	26711	26736	26736	16658	3	16672	80100	200	80000	200	80000	26736	26744	1	1	80201	100	99	0	100	100	80000	80000	0	100	80020	19	0	0	80019	0	0	2	63	80040	6	1	59	43	19	1	5110	4	16	4	4	26711	13	13	5	80000	100	26715	26928	26739	26846	26716
80204	26736	200	1	0	1	0	0	0	0	0	67	0	0	3	26721	3	7	7	102	25	80100	100	80130	100	80000	500	1167995	1	26711	26736	26736	16659	3	16672	80100	200	80000	200	80000	26736	26736	1	1	80201	100	99	0	100	100	80000	80000	0	100	80020	19	0	0	80059	1	0	2	21	80039	6	0	19	43	19	1	5110	4	16	4	3	26733	13	13	0	80000	100	26716	26738	26868	26817	26741
80204	26714	200	1	0	1	0	1	0	0	0	21	0	1	3	26721	3	0	7	72	25	80100	100	80000	100	80000	500	1172437	0	26689	26737	26714	16659	3	16672	80100	200	80000	200	80000	26737	26736	1	1	80201	100	99	0	100	100	80000	80000	1	100	80019	19	0	0	80059	0	0	1	61	80040	6	1	59	43	19	1	5110	4	16	4	4	26733	13	13	5	80000	100	26737	26737	26772	26828	26737

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.3340

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	09	l2 tlb miss data (0b)	0e	0f	1e	22	23	3a	3f	43	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	69	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	cf	l1i cache miss demand (d3)	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
80025	26722	200	1	0	0	0	41	1	0	1	26707	2	18	18	14	25	80010	10	80000	10	80000	50	1168000	1	26697	0	26722	26722	16667	3	16705	80010	20	80000	20	80000	26722	26722	1	1	80021	10	9	10	10	80000	80000	0	10	80000	0	39	80035	26	0	80035	6	1	35	0	5020	0	31	16	28	27	26719	6	6	2	80000	10	26723	26723	26723	26723	26732
80024	26749	200	0	0	0	0	41	1	0	1	26707	2	18	18	12	25	80010	10	80000	10	80000	50	1167605	1	26697	0	26722	26722	16652	3	16688	80010	20	80000	20	80000	26722	26722	1	1	80021	10	9	10	10	80000	80000	1	10	80000	0	39	80035	0	35	80035	6	1	35	39	5020	0	26	16	15	26	26725	6	6	2	80000	10	26723	26723	26723	26709	26727
80024	26727	200	0	0	0	0	41	1	0	1	26712	2	18	0	12	25	80010	10	80000	10	80000	50	1167605	1	26697	0	26727	26722	16652	3	16702	80010	20	80000	20	80000	26722	26722	1	1	80021	10	9	10	10	80000	80000	0	10	80000	0	39	80035	2	39	80000	6	1	35	43	5020	0	26	16	16	24	26725	6	6	2	80000	10	26723	26723	26723	26709	26737
80024	26726	200	0	0	0	0	50	1	0	0	26707	2	12	18	0	25	80010	10	80000	10	80000	50	1166545	1	26697	0	26722	26722	16788	3	16702	80010	20	80000	20	80000	26727	26722	1	1	80021	10	9	10	10	80000	80000	0	10	80000	0	0	80035	3	41	80035	6	1	35	39	5020	0	25	16	27	26	26724	6	10	2	80000	10	26723	26723	26723	26709	26734
80024	26722	200	0	0	0	0	0	1	0	1	26707	0	18	18	12	25	80010	10	80000	10	80000	50	1167605	1	26697	0	26708	26722	16667	3	16702	80010	20	80000	20	80000	26722	26722	1	1	80021	10	9	10	10	80000	80000	0	10	80000	0	39	80035	5	3	80035	6	1	35	39	5020	0	23	16	17	26	26719	0	6	2	80000	10	26709	26723	26723	26709	26728
80024	26722	199	0	0	0	0	41	0	0	0	26707	2	18	0	12	25	80010	10	80000	10	80000	50	1167605	1	26697	0	26722	26722	16667	3	16702	80010	20	80000	20	80000	26730	26726	1	1	80021	10	9	10	10	80000	80000	0	10	80000	0	39	80035	2	35	80035	0	1	35	39	5020	0	27	16	27	28	26719	6	6	2	80000	10	26723	26723	26709	26723	26732
80024	26722	200	0	0	0	0	41	1	0	1	26707	2	18	18	11	25	80010	10	80000	10	80000	50	1172240	1	26697	0	26722	26722	16667	3	16702	80010	20	80000	20	80000	26722	26722	1	1	80021	10	9	10	10	80000	80000	0	10	80000	0	39	80035	3	35	80035	6	0	35	43	5020	0	28	16	26	26	26705	10	6	2	80000	10	26723	26729	26723	26723	26728
80024	26722	200	0	0	0	0	41	0	0	1	26693	2	18	18	12	25	80010	10	80000	10	80000	50	1167605	1	26697	0	26722	26727	16667	3	16702	80010	20	80000	20	80000	26722	26708	1	1	80021	10	9	10	10	80000	80000	0	10	80000	0	39	80035	2	35	80035	6	1	35	39	5020	0	28	16	17	29	26719	6	6	4	80000	10	26723	26709	26723	26723	26733
80024	26728	201	0	0	0	0	41	1	0	1	26707	2	18	18	16	25	80010	10	80000	10	80000	50	1167605	1	26697	0	26722	26727	16672	3	16702	80010	20	80000	20	80000	26722	26708	1	1	80021	10	9	10	10	80000	80000	0	10	80000	0	0	80000	1	47	80035	6	1	35	39	5020	0	16	16	15	26	26719	6	6	2	80000	10	26723	26723	26723	26723	26823
80024	26727	200	0	0	1	0	41	1	0	1	26707	2	18	0	11	25	80010	10	80000	10	80000	50	1172240	1	26791	0	26722	26722	16667	3	16688	80010	20	80000	20	80000	26722	26722	1	1	80021	10	9	10	10	80000	80000	0	10	80000	0	39	80035	1	35	80035	6	1	35	39	5020	0	14	16	26	17	26719	6	6	2	80000	10	26723	26709	26723	26723	26737

LDUR (D)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->2 roundtrip

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations