Firestorm: LDUR (Q) measurements

Code:

  ldur q0, [x6, #1]

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 1.000

SIMD/FP unit issues: 0.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	0e	0f	1e	22	23	3a	3f	43	46	49	4f	51	schedule uop (52)	schedule ldst uop (55)	dispatch ldst uop (58)	simd uops in schedulers (5a)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map ldst uop (7d)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst simd load (98)	inst ldst (9b)	9d	l1d tlb access (a0)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	ea	eb	ec	? ldst retires (ed)	f5	f6	f7	f8	fd
1005	394	3	1	0	45	0	0	1	359	2	0	12	16	25	1000	1000	1000	15133	0	349	394	374	217	3	232	1000	1000	1000	394	394	1	1	1001	1000	1000	0	1000	0	1039	1	0	39	1039	6	1	0	43	73	1	16	1	1	371	0	10	4	1000	395	395	395	398	376
1004	374	3	0	0	44	1	0	1	383	2	1	1	21	25	1000	1000	1000	15267	1	373	401	398	221	3	256	1000	1000	1000	374	394	1	1	1001	1000	1000	0	1000	43	1000	0	0	0	1038	0	1	39	0	73	1	16	1	1	395	14	0	7	1000	399	395	375	399	395
1004	398	3	0	0	45	1	0	1	359	2	1	12	16	25	1000	1000	1000	15267	0	373	374	398	222	3	232	1000	1000	1000	398	374	1	1	1001	1000	1000	0	1000	0	1039	0	0	0	1038	6	1	39	0	73	1	16	1	1	395	14	14	7	1000	399	375	395	399	399
1004	374	3	0	0	44	0	0	1	359	0	0	1	19	25	1000	1000	1000	15267	1	349	398	398	197	3	252	1000	1000	1000	398	394	1	1	1001	1000	1000	0	1000	0	1038	0	0	38	1038	0	0	40	0	73	1	16	1	1	371	14	14	4	1000	375	395	375	399	399
1004	398	3	0	0	44	1	0	0	383	0	0	1	19	25	1000	1000	1000	14060	0	373	398	398	221	3	256	1000	1000	1000	398	394	1	1	1001	1000	1000	0	1000	43	1000	0	0	38	1038	6	0	0	44	73	1	16	1	1	391	0	14	0	1000	375	399	399	399	375
1004	398	3	0	0	0	1	0	1	383	0	0	0	16	25	1000	1000	1000	15274	1	373	398	398	221	3	256	1000	1000	1000	394	394	1	1	1001	1000	1000	0	1000	43	1038	0	0	38	1038	6	1	39	44	73	1	16	1	1	371	14	14	7	1000	375	395	395	375	399
1004	394	3	0	0	44	1	0	1	383	2	0	1	19	25	1000	1000	1000	15338	0	373	398	398	198	3	256	1000	1000	1000	398	394	1	1	1001	1000	1000	0	1000	44	1039	0	0	38	1038	6	0	39	44	73	1	16	1	1	395	0	0	0	1000	399	395	399	375	375
1004	398	3	0	0	44	0	0	1	383	2	1	1	0	25	1000	1000	1000	14060	0	349	394	394	197	3	256	1000	1000	1000	398	394	1	1	1001	1000	1000	0	1000	0	1038	2	0	0	1038	6	0	0	44	73	1	16	1	1	395	0	10	7	1000	399	395	395	375	375
1004	374	3	0	0	0	1	0	0	383	2	1	0	0	25	1000	1000	1000	15274	0	349	374	398	197	3	232	1000	1000	1000	374	394	1	1	1001	1000	1000	0	1000	43	1038	0	0	38	1039	0	0	39	0	73	1	16	1	1	391	0	10	4	1000	399	395	395	399	399
1004	378	3	0	0	44	0	0	1	359	2	0	0	19	25	1000	1000	1000	14060	0	373	394	398	221	3	232	1000	1000	1000	398	394	1	1	1001	1000	1000	0	1000	43	1038	0	0	38	1000	0	1	0	43	73	1	16	1	1	395	14	0	7	1000	399	395	375	375	410

Test 2: Latency 1->2 roundtrip

Chain cycles: 3

Code:

  ldur q0, [x6, #1]
  fmov x0, d0
  eor x8, x8, x0
  eor x8, x8, x0
  add x6, x6, x8

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 9.0050

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	l2 tlb miss data (0b)	0e	0f	19	1e	1f	22	24	3a	3f	4d	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	69	6b	6d	6e	map stall dispatch (70)	int prf full (71)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	b5	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
50205	120053	899	1	1	1	1	0	0	59	352	0	0	0	120030	119515	109603	25	60103	40102	10002	10000	30100	10000	10000	1079053	5746315	6136419	0	120032	0	120056	120041	113151	0	3	113673	50100	30200	10000	10000	60200	10000	10000	120041	120053	1	1	50201	100	99	100	40100	10000	10000	0	100	10002	2	1	10002	0	0	0	1	10000	1	1	0	1	1	0	0	3210	5	107	2	3	119663	40004	0	0	8	10000	40100	120057	120042	120057	120058	120057
50204	120041	899	1	0	0	0	0	0	2	0	0	0	0	120042	119513	109466	25	60106	40102	10002	10000	30100	10000	10000	1079026	5736332	6133458	0	120032	0	120056	120056	113148	0	3	113670	50100	30200	10000	10000	60200	10000	10000	120056	120053	1	1	50201	100	99	100	40100	10000	10000	1	100	10001	1	0	10002	0	0	0	1	10000	1	1	1	1	1	0	0	3210	4	135	3	3	119660	40004	9	6	0	10000	40100	120042	120057	120057	120057	120057
50204	120056	899	1	2	0	0	0	4	7	0	0	0	0	120035	119509	109461	25	60103	40135	10000	10000	30100	10000	10000	1078999	5736188	6136166	0	120026	0	120035	120050	113141	0	3	113667	50100	30200	10000	10000	60200	10000	10000	120050	120047	1	1	50201	100	99	100	40100	10000	10000	0	100	10000	0	1	10000	0	0	0	3	10004	1	0	0	0	0	0	0	3210	3	101	3	3	119657	40004	6	0	8	10000	40100	120057	120042	120054	120042	120432
50204	120041	899	1	1	0	0	0	0	1	0	1	0	0	120032	119493	109463	25	60100	40102	10001	10000	30100	10000	10000	1078999	5736188	6136166	0	120011	0	120050	120035	113145	0	3	113667	50100	30200	10000	10000	60200	10000	10000	120050	120047	1	1	50201	100	99	100	40100	10000	10000	0	100	10002	2	1	10001	0	0	1	1	10000	1	1	1	1	1	0	0	3210	3	135	3	3	119654	40004	9	9	5	10000	40100	120054	120057	120054	120042	120054
50204	120053	899	1	1	0	0	0	0	2	0	0	0	0	120020	119493	109461	25	60103	40100	10001	10000	30100	10000	10000	1078999	5736188	6133818	0	120026	0	120050	120050	113145	0	3	113658	50100	30200	10000	10000	60200	10000	10000	120050	120047	1	1	50201	100	99	100	40100	10000	10000	0	100	10002	2	1	10002	0	0	1	1	10000	1	1	0	1	1	0	0	3210	3	107	3	3	119663	40002	0	9	5	10000	40100	120051	120051	120036	120051	120051
50204	120050	899	0	0	0	0	0	0	1	0	1	0	0	120038	119515	109469	25	60106	40104	10002	10000	30100	10000	10000	1079053	5736476	6136419	0	120032	0	120056	120056	113151	0	3	113673	50100	30200	10000	10000	60200	10000	10000	120056	120041	1	1	50201	100	99	100	40100	10000	10000	0	100	10002	2	1	10003	0	0	0	1	10000	1	1	1	1	0	0	0	3210	3	107	3	3	119663	40002	9	6	8	10000	40100	120057	120057	120054	120057	120057
50204	120056	899	1	0	0	0	0	0	2	0	0	0	0	120026	119515	109455	25	60106	40104	10001	10000	30100	10000	10000	1079097	5736476	6133458	0	120032	0	120056	120053	113151	0	3	113673	50100	30200	10000	10000	60200	10000	10000	120056	120053	1	1	50201	100	99	100	40100	10000	10000	0	100	10000	0	1	10000	0	0	0	3	10000	1	0	0	0	0	1	0	3210	3	101	3	3	119657	40000	6	6	5	10000	40100	120051	120051	120051	120048	120036
50204	120050	899	0	0	0	0	0	0	1	0	0	0	0	120035	119493	109449	25	60100	40102	10000	10000	30100	10000	10000	1078999	5735455	6134461	0	120026	0	120050	120050	113145	0	3	113658	50100	30200	10000	10000	60200	10000	10000	120050	120047	1	1	50201	100	99	100	40100	10000	10000	0	100	10000	0	1	10000	0	0	0	0	10000	0	0	0	0	0	0	0	3210	3	107	3	3	119657	40002	6	0	0	10000	40100	120051	120036	120051	120051	120051
50204	120050	899	0	0	0	0	0	0	0	0	0	0	0	120032	119509	109461	25	60103	40100	10001	10000	30100	10000	10000	1079200	5735455	6133818	0	120026	0	120050	120047	113145	0	3	113638	51071	30200	10000	10000	60200	10000	10000	120037	120048	4	1	50201	100	99	100	40100	10000	10000	0	100	10000	0	1	10000	0	1	7	0	10001	0	0	1	0	2	0	0	3237	4	107	3	3	119660	40002	0	9	8	10000	40100	120036	120037	120038	120054	120039
50204	120036	901	0	1	1	0	1	0	18	0	0	0	0	120036	119519	109461	25	60103	40102	10001	10008	30100	10000	10000	1079200	5736044	6133818	0	120011	0	120047	120053	113145	0	3	113636	50100	30200	10000	10000	60200	10000	10000	120050	120035	1	1	50201	100	99	100	40100	10000	10000	0	100	10000	0	1	10000	0	0	0	0	10000	1	0	1	0	4	0	0	3210	4	124	6	3	119657	40002	0	6	5	10000	40100	120048	120052	120051	120051	120054

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 9.0061

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	09	l2 tlb miss data (0b)	0e	0f	1e	1f	22	23	3f	43	49	4d	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	af	b5	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
50025	120061	899	1	1	0	1	1	0	3	0	1	0	120046	1	0	119519	109474	25	60019	40016	10003	10000	30010	10000	10000	1079647	5736140	6134172	1	120037	120061	120049	113179	3	113700	50010	30020	10000	10000	60020	10000	10000	120061	120049	1	1	50021	10	9	10	40010	10000	10000	0	10	10002	2	2	10003	0	1	2	10001	1	2	0	1	1	3141	2	107	2	2	119676	40006	0	6	5	10000	40010	120050	120062	120106	120062	120062
50024	120061	899	1	0	1	1	1	0	3	0	1	0	120046	1	1	119507	109474	25	60019	40014	10002	10000	30010	10000	10000	1079647	5736140	6133560	1	120037	120049	120061	113179	3	113700	50010	30020	10000	10000	60020	10000	10000	120061	120049	1	1	50021	10	9	10	40010	10000	10000	0	10	10002	2	2	10003	0	1	5	10001	1	2	1	1	1	3141	3	107	2	2	119676	40006	6	6	0	10000	40010	120062	120050	120062	120050	120062
50024	120049	899	1	1	0	1	0	1	8	0	1	0	120046	1	1	119519	109474	25	60019	40016	10003	10000	30010	10000	10000	1079647	5736716	6133560	1	120025	120061	120061	113179	3	113688	50010	30020	10000	10000	60020	10000	10000	120061	120049	1	1	50021	10	9	10	40010	10000	10000	0	10	10003	2	2	10002	0	1	2	10001	1	2	1	1	1	3141	2	107	2	2	119676	40006	6	6	0	10000	40010	120050	120062	120062	120062	120050
50024	120061	899	1	0	0	1	0	0	3	0	0	0	120046	1	1	119519	109462	25	60019	40014	10003	10000	30010	10000	10000	1079647	5736716	6134172	1	120025	120049	120061	113179	3	113689	50010	30020	10000	10000	60020	10000	10000	120061	120061	1	1	50021	10	9	10	40010	10000	10000	0	10	10002	2	2	10004	55	1	2	10001	1	2	1	1	1	3141	2	107	2	2	119664	40006	6	6	5	10000	40010	120062	120062	120062	120050	120050
50024	120049	899	1	1	1	1	0	0	8	0	0	0	120046	1	0	119565	109462	25	60019	40016	10002	10000	30010	10000	10000	1079541	5736716	6134172	1	120025	120061	120061	113179	3	113700	50010	30020	10000	10000	60020	10000	10000	120061	120061	1	1	50021	10	9	10	40010	10000	10000	0	10	10002	3	0	10003	0	0	2	10001	1	2	1	1	0	3141	2	107	2	2	119664	40006	0	6	5	10000	40010	120062	120062	120050	120050	120062
50024	120049	899	1	1	1	1	0	0	2	0	0	0	120046	1	1	119519	109462	25	60019	40014	10003	10000	30010	10000	10000	1079541	5736140	6134172	1	120037	120061	120061	113179	3	113688	50010	30020	10000	10000	60020	10000	10000	120049	120049	1	1	50021	10	9	10	40010	10000	10000	0	10	10003	3	0	10002	0	1	2	10001	1	2	1	1	1	3141	2	107	2	2	119676	40006	6	6	0	10000	40010	120050	120050	120062	120050	120050
50024	120061	899	1	0	0	0	0	0	3	0	0	0	120394	1	1	119519	109761	25	60019	40014	10003	10004	30010	10000	10000	1079541	5751197	6134172	1	120449	120061	120498	113167	3	113688	50496	30020	10000	10000	60020	10000	10000	120061	120062	1	1	50021	10	9	10	40010	10000	10000	1	10	10001	2	2	10003	1	1	2	10001	1	2	1	1	2	3141	2	107	2	8	119676	40012	6	23	5	10000	40010	120052	120062	120050	120062	120062
50024	120061	900	1	0	0	0	0	0	3	0	0	0	120046	1	1	119519	109462	25	60019	40014	10003	10000	30010	10000	10000	1079647	5736716	6134172	1	120037	120049	120061	113179	3	113688	50010	30020	10000	10000	60020	10000	10000	120061	120061	1	1	50021	10	9	10	40010	10000	10000	0	10	10001	1	2	10003	0	0	2	10001	0	2	1	1	1	3141	2	107	2	2	119676	40006	0	6	5	10000	40010	120062	120062	120062	120062	120062
50024	120049	899	1	0	0	1	1	0	8	0	0	0	120046	1	0	119507	109474	25	60016	40016	10003	10000	30010	10000	10000	1079550	5736716	6134172	0	120037	120049	120049	113304	3	113688	50010	30020	10000	10000	60020	10000	10000	120061	120061	1	1	50021	10	9	10	40010	10000	10000	0	10	10001	2	2	10002	0	1	2	10001	1	2	1	1	1	3141	10	107	2	2	119676	40006	0	23	0	10000	40010	120062	120112	120050	120062	120062
50024	120096	899	1	0	1	1	0	0	2	0	1	0	120080	1	1	119519	109474	25	60019	40016	10003	10000	30010	10000	10000	1079647	5736140	6134172	1	120025	120061	120061	113167	3	113700	50010	30020	10000	10000	60020	10000	10000	120061	120061	1	1	50021	10	9	10	40010	10000	10000	1	10	10001	1	2	10002	0	1	2	10001	1	2	1	1	0	3141	2	107	2	2	119676	40006	6	6	5	10000	40010	120062	120062	120062	120062	120062

Test 3: throughput

Count: 8

Code:

  ldur q0, [x6, #1]
  ldur q0, [x6, #1]
  ldur q0, [x6, #1]
  ldur q0, [x6, #1]
  ldur q0, [x6, #1]
  ldur q0, [x6, #1]
  ldur q0, [x6, #1]
  ldur q0, [x6, #1]

Initialization

  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.3341

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	0e	0f	1e	22	23	3a	3f	43	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	e7	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
80205	26728	200	0	0	0	0	0	2	26707	2	0	0	18	25	80100	100	80000	112	80000	500	1166525	1	26697	26727	26727	16650	3	16665	80100	200	80000	200	80000	26732	26835	1	1	80201	100	99	100	100	80000	80000	1	100	80000	0	80039	0	0	39	80000	6	0	0	43	5110	1	16	1	1	26719	0	10	6	2	80000	100	26728	26708	26728	26708	26728
80204	26707	200	0	0	45	0	0	2	26712	2	0	12	11	25	80100	100	80000	100	80000	500	1167231	1	26702	26727	26707	16645	3	16685	80100	200	80000	200	80000	26727	26722	1	1	80201	100	99	100	100	80000	80000	1	100	80000	39	80035	0	0	0	80039	6	1	35	0	5110	1	16	1	1	26723	0	10	6	4	80000	100	26728	26728	26728	26708	26708
80204	26707	200	0	0	45	0	0	0	26712	0	12	12	16	25	80100	100	80000	100	80000	500	1166525	1	26702	26727	26727	16650	3	16685	80100	200	80000	200	80000	26727	26722	1	1	80201	100	99	100	100	80000	80000	0	100	80000	39	80000	1	0	35	80000	0	0	35	39	5110	1	16	1	1	26704	0	10	6	4	80000	100	26708	26708	26728	26728	26708
80204	26707	200	1	1	0	0	0	2	26692	2	12	0	16	25	80100	100	80000	100	80000	500	1167808	1	26702	26707	26727	16630	3	16685	80100	200	80000	200	80000	26727	26722	1	1	80201	100	99	100	100	80000	80000	0	100	80000	0	80000	0	0	39	80039	6	1	35	43	5110	3	16	1	1	26724	0	6	16	2	80000	100	26713	26723	26723	26708	26728
80204	26707	200	0	0	57	0	0	0	26712	2	12	12	16	25	80100	100	80000	100	80000	500	1165789	1	26702	26727	26707	16650	3	16685	80100	200	80000	200	80000	26727	26707	1	1	80201	100	99	100	100	80000	80000	0	100	80000	39	80035	0	0	42	80039	0	1	39	0	5110	1	16	1	1	26724	0	10	0	0	80000	100	26728	26728	26728	26723	26708
80204	26728	200	0	0	45	1	0	2	26712	2	18	12	0	25	80100	100	80000	100	80000	500	1177038	1	26682	26727	26727	16650	3	16685	80100	200	80000	200	80000	26737	26722	1	1	80201	100	99	100	100	80000	80000	0	100	80000	39	80000	0	0	39	80039	6	1	39	43	5110	1	16	1	1	26724	0	0	10	4	80000	100	26728	26708	26708	26728	26728
80204	26727	200	0	0	45	0	0	2	26692	2	12	12	16	25	80100	100	80000	100	80000	500	1166525	1	26702	26727	26727	16650	3	16680	80100	200	80000	200	80000	26727	26722	1	1	80201	100	99	100	100	80000	80000	0	100	80000	43	80035	0	0	39	80000	6	0	35	43	5110	1	16	1	1	26704	0	0	10	0	80000	100	26728	26723	26708	26728	26708
80204	26722	200	0	0	0	0	0	0	26712	2	12	12	12	25	80100	100	80000	100	80000	500	1166525	1	26702	26707	26722	16650	3	16665	80100	200	80000	200	80000	26713	26722	1	1	80201	100	99	100	100	80000	80000	0	100	80000	43	80039	0	0	39	80039	6	0	35	43	5110	1	16	1	1	26724	0	10	0	4	80000	100	26728	26708	26708	26708	26723
80204	26727	200	0	0	0	1	0	2	26712	0	12	0	12	25	80100	100	80000	100	80000	500	1167231	1	26702	26727	26707	16630	3	16665	80100	200	80000	200	80000	26707	26722	1	1	80201	100	99	100	100	80000	80000	0	100	80000	39	80039	0	0	39	80039	0	1	39	43	5110	5	16	1	1	26727	0	10	0	0	80000	100	26881	26884	26728	26728	26708
80204	26707	200	1	1	42	0	0	2	26692	2	12	0	16	25	80100	100	80000	100	80000	500	1167231	1	26682	26707	26727	16630	3	16685	80100	200	80000	200	80000	26727	26722	1	1	80201	100	99	100	100	80000	80000	0	100	80000	0	80035	0	0	39	80039	0	1	35	0	5110	1	16	1	1	26719	0	0	6	4	80000	100	26728	26708	26728	26728	26728

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.3342

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	l2 tlb miss data (0b)	0e	0f	1e	22	23	3a	3f	43	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	69	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	92	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
80025	26736	200	1	1	1	0	0	67	0	0	1	26722	3	0	0	20	25	80010	10	80000	10	80000	50	1167791	1	26690	0	26736	26736	16682	3	16716	80010	20	80000	20	80000	26736	26736	1	1	80021	10	9	0	10	10	80000	80000	1	10	80020	19	43	80059	2	0	0	21	80039	6	1	60	43	19	1	0	0	5020	4	16	6	6	26733	13	13	5	80000	10	26738	26737	26737	26738	26738
80024	26736	200	1	1	1	0	0	67	1	0	3	26722	3	7	7	18	25	80010	10	80000	10	80000	50	1167793	0	26712	3	26744	26745	16681	3	16716	80010	20	80000	20	80000	26741	26736	1	1	80021	10	9	0	10	10	80000	80000	0	10	80020	20	43	80058	0	0	0	60	80040	6	1	19	43	19	0	0	0	5020	8	16	4	3	26734	13	13	5	80000	10	26738	26737	26716	26716	26737
80024	26737	200	1	0	1	0	0	66	1	0	3	26700	3	7	0	0	25	80010	10	80000	10	80000	50	1168286	0	26711	0	26737	26737	16681	3	16716	80010	20	80000	20	80000	26736	26736	1	1	80021	10	9	0	10	10	80000	80000	0	10	80021	21	43	80059	0	0	1	61	80000	6	1	58	43	19	1	0	0	5020	4	16	8	7	26734	13	13	5	80000	10	26737	26715	26737	26737	26715
80024	26715	200	1	0	0	0	0	21	1	0	3	26722	3	7	0	20	25	80010	10	80000	10	80000	50	1168286	1	26711	0	26736	26736	16681	3	16716	80010	20	80000	20	80000	26736	26736	1	1	80021	10	9	0	10	10	80000	80000	0	10	80019	19	0	80059	1	1	0	21	80040	0	1	58	43	19	1	0	0	5020	9	16	4	3	26734	13	13	5	80000	10	26737	26738	26738	26737	26737
80024	26737	200	1	1	0	0	0	66	1	0	1	26716	0	1	12	16	25	80010	10	80000	10	80000	50	1166896	1	26703	0	26728	26728	16672	3	16688	80010	20	80000	20	80000	26727	26727	1	1	80021	10	9	0	10	10	80000	80000	0	10	80000	0	43	80039	0	0	0	0	80039	0	1	0	43	0	0	2	0	5020	4	16	4	4	26724	10	10	0	80000	10	26709	26728	26709	26728	26729
80024	26731	200	0	0	0	0	0	45	1	0	1	26716	0	1	1	16	25	80010	10	80000	10	80000	50	1168843	1	26702	0	26708	26731	16672	3	16707	80010	20	80000	20	80000	26731	26728	1	1	80021	10	9	0	10	10	80000	80000	0	10	80000	0	43	80039	0	0	0	39	80039	6	1	0	43	0	0	0	0	5020	7	16	6	7	26734	13	0	5	80000	10	26738	26738	26737	26737	26737
80024	26736	200	1	0	1	1	0	69	1	0	3	26722	3	7	7	18	25	80010	10	80000	10	80000	50	1169451	1	26689	0	26736	26736	16681	3	16694	80010	20	80000	20	80000	26736	26736	1	1	80021	10	9	0	10	10	80000	80000	0	10	80021	20	43	80059	1	0	2	61	80000	0	0	59	0	19	0	0	0	5020	4	16	4	7	26733	13	0	5	80000	10	26737	26738	26715	26738	26716
80024	26736	200	1	0	1	1	1	67	1	0	3	26700	3	0	7	20	25	80010	10	80000	10	80000	50	1167791	1	26712	0	26714	26737	16682	3	16717	80010	20	80000	20	80000	26736	26736	1	1	80021	10	9	0	10	10	80000	80000	1	10	80020	20	43	80059	1	0	1	61	80000	6	1	59	43	19	0	0	0	5020	7	16	7	8	26734	13	0	0	80000	10	26737	26737	26738	26737	26737
80024	26714	200	1	1	0	0	0	66	0	0	3	26724	3	7	7	20	25	80010	10	80000	10	80000	50	1166960	1	26712	3	26888	26737	16659	3	16716	80010	20	80000	20	80000	26715	26736	1	1	80021	10	9	0	10	10	80000	80000	1	10	80021	21	43	80059	0	0	0	60	80040	6	1	59	43	19	0	0	0	5020	4	16	4	4	26733	13	13	5	80000	10	26737	26738	26737	26737	26738
80024	26736	200	1	1	1	0	0	21	1	0	3	26721	3	7	7	20	25	80010	10	80000	10	80000	50	1168286	1	26690	0	26737	26715	16681	3	16695	80010	20	80000	20	80000	26736	26736	1	1	80021	10	9	0	10	10	80000	80000	0	10	80019	20	43	80060	1	0	0	61	80040	6	1	58	43	19	2	0	0	5020	4	16	3	4	26733	13	0	5	80000	10	26738	26737	26737	26716	26737

LDUR (Q)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->2 roundtrip

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations