Firestorm: LDUR (S) measurements

Code:

  ldur s0, [x6, #1]

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 1.000

SIMD/FP unit issues: 0.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	09	l2 tlb miss data (0b)	0e	0f	1e	22	3a	3f	43	46	49	4f	51	schedule uop (52)	schedule ldst uop (55)	dispatch ldst uop (58)	simd uops in schedulers (5a)	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map ldst uop (7d)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst simd load (98)	inst ldst (9b)	9d	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	ea	eb	ec	? ldst retires (ed)	f5	f6	f7	f8	fd
1005	389	3	0	0	0	0	1	0	41	1	1	359	2	0	18	0	25	1000	1000	1000	14844	364	389	374	212	3	247	1000	1000	1000	391	389	1	1	1001	1000	1000	0	1000	0	39	1000	0	0	0	0	1035	6	0	0	39	0	0	73	2	16	1	1	376	6	6	2	1000	390	390	395	392	390
1004	389	2	0	0	0	0	0	0	41	0	2	379	2	18	18	16	25	1000	1000	1000	15018	369	389	389	197	3	252	1000	1000	1000	381	403	1	1	1001	1000	1000	0	1019	20	0	1057	1	1	1	62	1038	6	1	57	42	19	0	73	1	16	1	1	371	10	6	4	1000	375	392	395	375	375
1004	389	2	0	0	0	0	0	0	0	1	2	359	2	0	18	0	25	1000	1000	1000	14989	369	389	394	212	3	232	1000	1000	1000	381	402	1	1	1001	1000	1000	0	1018	20	42	1019	1	1	1	21	1000	6	1	57	42	19	1	73	1	16	1	1	371	10	0	8	1000	375	395	375	395	395
1004	374	3	0	0	0	0	0	0	0	0	0	359	2	12	12	16	25	1000	1000	1000	14838	349	394	394	212	3	252	1000	1000	1000	389	389	1	1	1001	1000	1000	0	1000	0	0	1039	0	0	0	35	1039	6	0	0	0	0	0	73	1	16	1	1	371	10	0	4	1000	375	375	375	395	395
1004	394	3	0	0	0	0	0	0	45	0	2	384	2	18	18	16	25	1000	1000	1000	15375	374	399	399	221	3	239	1000	1000	1000	374	409	1	1	1001	1000	1000	0	1000	0	39	1000	0	0	0	35	1039	6	0	0	43	0	0	73	1	16	1	1	371	10	10	2	1000	390	390	375	375	395
1004	394	2	0	0	0	0	0	0	45	0	2	384	2	0	18	16	25	1000	1000	1000	15362	373	399	398	221	3	257	1000	1000	1000	409	389	1	1	1001	1000	1000	0	1000	0	39	1039	0	0	0	39	1000	6	1	0	43	0	0	73	1	16	1	1	391	10	10	4	1000	395	395	375	375	375
1004	394	3	0	0	0	0	0	0	0	0	0	376	0	0	12	16	25	1000	1000	1000	14838	364	389	389	212	3	252	1000	1000	1000	374	389	1	1	1001	1000	1000	0	1000	0	39	1035	0	0	0	0	1039	6	1	35	43	0	0	73	1	16	1	1	371	0	0	0	1000	395	375	395	375	395
1004	389	3	0	0	0	0	0	0	45	0	2	384	0	18	18	15	25	1000	1000	1000	14456	356	382	399	221	3	240	1000	1000	1000	398	399	1	1	1001	1000	1000	0	1019	21	42	1057	0	0	0	21	1000	0	1	57	42	19	0	73	1	16	1	1	391	10	6	4	1000	395	395	395	395	395
1004	394	3	0	0	0	0	0	0	0	0	2	379	2	12	12	16	25	1000	1000	1000	14838	349	374	374	217	3	232	1000	1000	1000	399	398	1	1	1001	1000	1000	0	1019	19	42	1019	1	0	2	21	1000	6	1	57	42	19	0	73	1	16	1	1	371	10	6	4	1000	375	395	395	392	395
1004	374	3	0	0	0	0	0	0	45	0	1	379	2	12	12	12	25	1000	1000	1000	14989	369	374	389	217	3	247	1000	1000	1000	394	374	1	1	1001	1000	1000	0	1000	0	39	1035	0	0	0	0	1039	6	1	0	43	0	0	73	1	16	1	1	379	9	9	2	1000	399	400	400	400	382

Test 2: Latency 1->2 roundtrip

Chain cycles: 3

Code:

  ldur s0, [x6, #1]
  fmov x0, d0
  eor x8, x8, x0
  eor x8, x8, x0
  add x6, x6, x8

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 9.0047

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	09	l2 tlb miss data (0b)	0e	0f	18	19	1e	1f	22	23	3a	3f	4d	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	69	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	b5	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	branch mispred nonspec (cb)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
50205	120047	899	0	0	0	0	1	1	0	0	931	0	0	0	1	120038	119515	109466	25	60103	40104	10001	10000	30100	10000	10000	1079097	5736332	6136419	1	120023	0	120047	120047	113143	3	113670	50100	30200	10000	10000	60200	10000	10000	120041	120053	1	1	50201	100	99	100	40100	10000	10000	0	100	10002	2	0	10001	0	0	1	1	10000	1	1	0	1	1	0	3210	3	107	1	1	119660	40002	6	0	0	10000	40100	120042	120054	120054	120054	120042
50204	120056	899	1	0	0	1	0	0	0	0	67	0	1	0	0	120020	119509	109461	25	60103	40102	10001	10000	30100	10000	10000	1078862	5735455	6133818	0	120026	0	120035	120095	113145	3	113667	50100	30200	10000	10000	60200	10000	10000	120035	120035	1	1	50201	100	99	100	40100	10000	10000	0	100	10000	0	1	10000	0	0	0	0	10000	0	0	0	0	0	0	3210	1	135	1	1	119660	40000	0	6	5	10000	40100	120036	120048	120036	120048	120036
50204	120047	899	0	0	0	0	0	0	0	0	806	352	1	0	0	120035	119509	109461	25	60100	40102	10001	10000	30100	10000	10000	1078999	5736044	6133818	0	120063	0	120050	120050	113143	3	113636	50100	30200	10000	10000	60200	10000	10000	120047	120047	1	1	50201	100	99	100	40100	10000	10000	0	100	10000	0	1	10000	0	0	0	0	10000	1	0	1	0	0	0	3210	1	101	1	1	119657	40002	6	6	5	10000	40100	120048	120036	120036	120037	120036
50204	120035	899	0	0	0	0	0	0	0	0	521	0	1	0	0	120032	119493	109449	25	60103	40102	10001	10000	30100	10000	10000	1078999	5736044	6134461	0	120023	0	120047	120050	113143	3	113639	50100	30200	10000	10000	60200	10000	10000	120050	120047	1	1	50201	100	99	100	40100	10000	10000	0	100	10000	0	1	10000	0	0	0	0	10000	1	0	0	0	0	0	3210	1	135	1	1	119660	40002	6	6	0	10000	40100	120051	120051	120048	120048	120051
50204	120050	899	0	0	0	0	0	0	0	0	845	0	1	0	0	120032	119493	109449	25	60103	40102	10001	10000	30100	10000	10000	1078862	5735455	6133818	1	120023	0	120047	120035	113143	3	113639	50100	30200	10000	10000	60200	10000	10000	120047	120035	1	1	50201	100	99	100	40100	10000	10000	0	100	10000	0	0	10000	0	0	0	0	10000	1	0	1	0	0	0	3210	1	17	1	2	119660	40000	0	6	0	10000	40100	120036	120036	120048	120048	120048
50204	120050	899	0	0	0	0	0	0	0	0	7	0	1	0	0	120032	119493	109461	25	60103	40100	10001	10000	30100	10000	10000	1079200	5736188	6133818	0	120011	0	120047	120047	113143	3	113636	50100	30200	10000	10000	60200	10000	10000	120047	120047	1	1	50201	100	99	100	40100	10000	10000	0	100	10000	0	1	10000	0	0	0	0	10000	1	0	0	0	0	0	3210	1	101	1	1	119660	40002	6	6	8	10000	40100	120051	120048	120036	120051	120036
50204	120050	899	0	0	0	0	0	0	0	0	865	0	1	0	0	120032	119493	109463	25	60103	40100	10001	10000	30100	10061	10000	1078862	5736188	6136166	0	120023	0	120047	120047	113143	3	113636	50100	30200	10000	10000	60200	10000	10000	120047	120035	1	1	50201	100	99	100	40100	10000	10000	0	100	10000	0	1	10000	0	0	0	3	10000	1	0	1	0	0	0	3210	1	101	1	1	119657	40000	0	6	5	10000	40100	120051	120038	120036	120036	120048
50204	120047	900	0	0	0	0	0	0	0	0	848	352	0	1	0	120032	119519	109461	25	60103	40134	10001	10000	30100	10000	10000	1078862	5736044	6134283	0	120023	0	120047	120047	113141	3	113636	50100	30200	10000	10000	60200	10000	10000	120047	120047	1	1	50201	100	99	100	40100	10000	10000	0	100	10000	0	1	10000	0	1	0	0	10000	0	0	1	0	0	0	3210	1	101	2	1	119660	40002	0	0	5	10000	40100	120048	120048	120048	120048	120048
50204	120047	899	0	0	0	0	0	0	0	0	722	0	0	1	0	120020	119519	109461	25	60103	40102	10000	10000	30100	10000	10000	1079200	5736188	6133818	0	120023	0	120047	120047	113141	3	113636	50100	30200	10000	10000	60200	10000	10000	120047	120047	1	1	50201	100	99	100	40100	10000	10000	0	100	10000	0	0	10000	0	0	0	0	10001	0	0	0	0	0	0	3210	1	107	1	1	119660	40002	6	6	0	10000	40100	120051	120048	120048	120048	120048
50204	120035	899	0	0	0	0	1	1	0	0	532	0	0	0	0	120020	119519	109461	25	60103	40102	10001	10000	30100	10000	10000	1078862	5736428	6133818	0	120023	0	120047	120047	113143	3	113636	50100	30200	10000	10000	60200	10064	10000	120050	120035	1	1	50201	100	99	100	40100	10000	10000	0	100	10000	0	0	10000	0	0	0	0	10000	1	0	0	0	0	0	3210	1	135	1	1	119660	40000	9	0	8	10000	40100	120036	120051	120048	120048	120048

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 9.0051

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk instruction (07)	mmu table walk data (08)	l2 tlb miss instruction (0a)	l2 tlb miss data (0b)	0e	0f	18	19	1e	1f	22	23	3a	3f	4d	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	af	b5	l1d cache miss ld nonspec (bf)	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
50025	120051	899	0	0	0	0	0	0	0	0	7	0	1	0	0	120036	119509	109464	25	60013	40012	10001	10000	30010	10000	10000	1079517	5736236	6133662	0	120011	120051	120051	113169	3	113690	50010	30020	10000	10000	60020	10000	10000	120089	120068	1	1	50021	10	9	10	40010	10000	10000	0	10	10000	0	1	10000	0	0	0	10000	1	1	0	3140	12	107	6	4	119650	40002	0	10	9	10000	40010	120036	120052	120052	120052	120052
50024	120051	899	0	0	0	0	0	0	0	0	6	0	1	0	0	120036	119642	109464	25	60013	40012	10001	10000	30010	10000	10000	1079557	5736332	6133662	0	120027	120051	120035	113169	24	113603	50275	30020	10000	10000	60020	10000	10000	120063	120054	1	1	50021	10	9	10	40010	10000	10000	0	10	10000	0	1	10000	0	0	0	10000	1	1	0	3140	3	109	3	4	119668	40002	10	10	9	10000	40010	120052	120052	120052	120052	120052
50024	120051	899	0	0	0	0	0	0	0	0	1	0	1	0	0	120036	119509	109464	25	60010	40012	10001	10000	30010	10000	10000	1079557	5736236	6133662	0	120027	120035	120051	113241	3	113690	50010	30020	10000	10000	60020	10000	10000	120086	120070	1	1	50021	10	9	10	40010	10000	10000	0	10	10000	0	1	10000	0	0	0	10000	1	1	0	3140	3	107	3	4	119666	40002	10	10	0	10000	40010	120052	120052	120052	120052	120052
50024	120051	899	0	0	0	0	0	0	0	0	1	0	1	0	0	120036	119509	109464	25	60013	40012	10001	10000	30010	10000	10000	1079557	5736236	6133662	0	120027	120051	120051	113169	3	113674	50010	30020	10000	10000	60020	10000	10000	120050	120054	1	1	50021	10	9	10	40010	10000	10000	0	10	10000	0	0	10000	1	0	0	10000	1	1	0	3140	3	107	4	4	119666	40002	10	10	9	10000	40010	120036	120052	120052	120052	120052
50025	120051	931	0	0	0	0	0	0	0	0	6	0	1	0	0	120036	119509	109464	25	60013	40012	10001	10000	30010	10000	10000	1079557	5736236	6133662	0	120027	120063	120051	113169	3	113690	50010	30020	10000	10000	60020	10000	10000	120091	120058	1	1	50021	10	9	10	40010	10000	10000	1	10	10000	0	1	10000	0	0	3	10000	1	1	0	3140	4	107	6	7	119666	40010	10	10	9	10000	40010	120036	120052	120036	120052	120052
50024	120051	899	0	0	0	0	1	1	0	0	295	0	1	0	0	120036	119575	109528	137	60013	40028	10001	10002	30010	10052	10098	1079517	5736236	6133764	2	120029	120051	120051	113169	3	113690	50010	30179	10000	10110	60020	10160	10000	120112	120185	2	1	50021	10	9	10	40010	10000	10000	0	10	10000	0	1	10000	0	0	6	10000	1	0	0	3140	3	107	4	4	119666	40002	10	10	9	10000	40010	120052	120052	120052	120052	120052
50024	120052	900	0	0	0	0	0	0	0	0	157	88	1	0	1	120235	119509	109464	25	60025	40012	10001	10000	30010	10000	10000	1079557	5736236	6134783	0	120027	120154	120053	113169	3	113690	50010	30020	10000	10000	60020	10053	10000	120061	120067	1	1	50021	10	9	10	40010	10000	10000	0	10	10000	2	1	10000	0	0	3	10000	1	1	0	3140	6	107	7	6	119666	40002	10	10	9	10000	40010	120243	120053	120053	120147	120156
50024	120051	899	0	0	0	0	0	0	0	0	0	0	1	0	0	120036	119569	109464	25	60013	40012	10001	10000	30293	10000	10000	1079557	5736332	6133662	1	120027	120051	120051	113169	3	113690	50010	30020	10000	10000	60020	10000	10054	120086	120086	1	1	50021	10	9	10	40010	10000	10000	0	10	10000	0	1	10000	0	0	0	10000	1	1	0	3140	3	107	3	4	119666	40002	10	10	9	10000	40010	120052	120052	120052	120052	120052
50024	120051	900	0	0	0	0	0	0	0	0	1	0	1	0	0	120020	119509	109483	25	60013	40012	10001	10000	30010	10000	10000	1079557	5736236	6133662	0	120011	120051	120051	113170	3	113690	50010	30020	10000	10000	60020	10000	10000	120051	120051	1	1	50021	10	9	10	40010	10000	10000	0	10	10000	0	1	10000	0	0	3	10000	1	1	0	3140	4	107	7	6	119666	40002	0	10	9	10000	40010	120052	120052	120036	120052	120052
50024	120051	899	0	0	0	0	0	0	0	1	1	0	1	0	0	120036	119569	109464	25	60013	40012	10001	10000	30010	10000	10000	1079557	5736236	6133662	0	120027	120051	120051	113169	17	113776	50010	30020	10000	10000	60020	10000	10000	120051	120052	1	1	50021	10	9	10	40010	10000	10000	1	10	10000	0	1	10000	0	0	0	10000	1	1	0	3140	4	107	3	4	119666	40002	13	0	9	10000	40010	120052	120052	120052	120052	120037

Test 3: throughput

Count: 8

Code:

  ldur s0, [x6, #1]
  ldur s0, [x6, #1]
  ldur s0, [x6, #1]
  ldur s0, [x6, #1]
  ldur s0, [x6, #1]
  ldur s0, [x6, #1]
  ldur s0, [x6, #1]
  ldur s0, [x6, #1]

Initialization

  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.3341

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	09	l2 tlb miss instruction (0a)	0e	0f	19	1e	22	24	3a	3f	43	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d cache miss ld (a3)	a5	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
80205	26736	200	0	0	0	0	0	44	0	0	1	26712	0	0	12	16	25	80100	100	80000	100	80000	500	1172869	0	26706	26707	26727	16650	3	16665	80100	200	80000	200	80000	26727	26727	1	1	80201	100	99	100	100	80000	80000	0	100	80000	43	0	80039	0	0	0	80039	6	0	39	43	5110	1	16	1	1	26728	14	10	7	80000	100	26708	26708	26728	26732	26728
80204	26727	201	0	0	0	1	0	44	1	0	0	26692	3	1	0	0	25	80100	100	80000	100	80000	500	1168317	0	26682	26797	27001	16657	3	16671	80100	200	80000	200	80000	26731	26727	1	1	80201	100	99	100	100	80000	80000	1	100	80000	43	0	80039	0	0	39	80000	0	1	39	43	5110	1	16	1	1	26728	0	14	7	80000	100	26729	26728	26732	26732	26728
80204	26731	200	0	0	0	1	0	45	0	0	1	26692	2	1	1	0	25	80100	100	80000	100	80000	500	1172841	0	26706	26707	26731	16630	3	16665	80100	200	80000	200	80000	26731	26727	1	1	80201	100	99	100	100	80000	80000	1	100	80000	43	0	80038	0	0	38	80038	6	0	0	43	5110	1	16	1	1	26728	14	14	7	80000	100	26732	26732	26732	26732	26708
80204	26727	200	0	0	0	0	0	44	1	0	1	26712	2	0	0	19	25	80100	100	80000	100	80000	500	1173232	1	26682	26727	26707	16650	3	16665	80100	200	80000	200	80000	26707	26727	1	1	80201	100	99	100	100	80000	80000	0	100	80000	43	0	80038	0	0	38	80000	6	1	39	44	5110	1	16	1	1	26704	14	14	4	80000	100	26708	26708	26728	26708	26708
80204	26707	200	1	1	0	0	0	0	1	0	0	26716	0	0	0	19	25	80100	100	80000	100	80000	500	1166525	1	26702	26707	26727	16630	3	16665	80100	200	80193	200	80000	26707	26727	1	1	80201	100	99	100	100	80000	80000	0	100	80000	0	0	80038	0	0	0	80038	6	1	39	0	5110	1	16	1	1	26724	0	0	7	80000	100	26708	26732	26728	26728	26708
80204	26707	201	0	0	0	0	0	45	0	0	0	26712	2	12	0	0	25	80100	100	80000	100	80000	500	1173370	1	26702	26707	26707	16630	3	16689	80100	200	80000	200	80000	26731	26707	1	1	80201	100	99	100	100	80000	80000	0	100	80000	43	0	80038	1	0	38	80039	6	0	39	0	5110	1	16	1	1	26728	14	14	0	80000	100	26728	26728	26708	26728	26728
80204	26727	200	0	0	0	0	0	44	0	0	1	26692	2	1	1	16	25	80100	100	80000	100	80000	500	1170239	1	26706	26731	26707	16630	3	16665	80100	200	80000	200	80000	26707	26727	1	1	80201	100	99	100	100	80000	80000	0	100	80000	0	0	80038	0	0	104	80000	6	0	0	44	5110	1	16	1	1	26704	14	14	7	80000	100	26708	26732	26708	26732	26732
80204	26707	200	0	0	1	0	0	45	0	0	1	26712	2	12	12	16	25	80100	100	80000	100	80000	500	1169914	1	26706	26710	26730	16654	3	16665	80100	200	80000	200	80000	26707	26727	1	1	80201	100	99	100	100	80000	80000	0	100	80000	43	0	80000	0	0	38	80038	6	1	0	43	5110	1	16	1	1	26704	14	14	7	80000	100	26728	26732	26728	26708	26728
80204	26707	200	0	0	0	0	0	0	0	0	1	26715	2	12	12	16	25	80100	100	80000	100	80000	500	1167825	1	26702	26727	26727	16630	3	16685	80100	200	80000	200	80000	26707	26707	1	1	80201	100	99	100	100	80000	80000	0	100	80000	0	0	80000	0	0	0	80039	6	1	0	43	5110	1	16	1	1	26728	0	14	4	80000	100	26728	26732	26732	26728	26728
80204	26707	200	1	0	1	1	0	45	0	0	1	26716	2	0	1	17	25	80100	100	80000	100	80000	500	1168312	1	26706	26731	26707	16654	3	16689	80100	200	80000	200	80000	26707	26707	1	1	80201	100	99	100	100	80000	80000	0	100	80000	43	0	80000	0	0	38	80038	0	1	39	44	5110	1	16	1	1	26728	10	14	7	80000	100	26732	26728	26732	26732	26732

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.3340

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	l2 tlb miss instruction (0a)	l2 tlb miss data (0b)	0e	0f	1e	1f	22	24	3a	3f	43	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
80025	26722	200	0	0	0	1	1	1	41	0	1	0	3	26718	2	18	18	0	25	80010	10	80000	10	80000	50	1172370	1	26697	26722	26722	16667	3	16712	80010	20	80000	20	80000	26732	26733	1	1	80021	10	9	10	10	80000	80000	0	10	80000	0	39	80035	0	1	0	35	80035	6	1	54	42	19	1	5020	11	16	2	6	26719	0	6	2	80000	10	26725	26723	26723	26723	26723
80024	26722	200	0	0	0	0	0	0	65	0	0	0	3	26717	2	18	18	0	25	80010	10	80000	10	80000	50	1170078	0	26708	26732	26715	16660	3	16712	80010	20	80000	20	80000	26732	26732	1	1	80021	10	9	10	10	80000	80000	0	10	80019	20	42	80019	1	0	1	62	80039	6	1	35	39	0	0	5020	2	16	2	2	26719	6	6	2	80000	10	26723	26723	26723	26723	26723
80024	26722	200	0	0	0	0	0	0	41	0	1	0	0	26693	2	18	0	11	25	80010	10	80000	10	80000	50	1166291	1	26683	26714	26722	16654	3	16688	80010	20	80000	20	80000	26722	26722	1	1	80021	10	9	10	10	80000	80000	1	10	80000	0	39	80035	0	0	0	35	80035	6	1	35	39	0	0	5020	2	16	2	2	26719	6	0	2	80000	10	26723	26723	26723	26723	26726
80024	26722	201	0	0	0	0	0	0	50	0	1	0	1	26707	2	0	18	12	25	80010	10	80000	10	80000	50	1167605	0	26708	26732	26733	16677	3	16712	80010	20	80000	20	80000	26732	26733	1	1	80021	10	9	10	10	80000	80000	0	10	80000	0	39	80035	0	0	0	35	80035	6	1	57	42	19	0	5020	2	16	2	2	26729	9	9	2	80000	10	26723	26812	26886	26734	26723
80024	26723	200	0	1	0	0	0	0	41	0	0	0	1	26707	2	18	0	11	25	80010	10	80000	10	80000	50	1174614	1	26697	26722	26722	16667	3	16702	80010	20	80000	20	80000	26708	26722	1	1	80021	10	9	10	10	80000	80000	0	10	80000	0	39	80035	0	0	0	35	80035	6	1	35	0	0	0	5020	2	16	2	2	26719	6	6	2	80000	10	26723	26723	26723	26723	26723
80024	26722	200	0	0	0	0	0	0	0	0	1	0	1	26707	2	18	18	12	25	80010	10	80000	10	80000	50	1173655	0	26697	26708	26708	16652	3	16702	80010	20	80000	20	80000	26722	26708	1	1	80021	10	9	10	10	80000	80000	0	10	80000	0	39	80035	0	0	0	0	80000	0	1	35	39	0	0	5020	2	16	2	2	26719	6	6	2	80000	10	26723	26723	26709	26709	26723
80024	26722	200	0	0	0	0	0	0	0	0	1	0	1	26707	0	18	18	12	25	80010	10	80000	10	80000	50	1172941	0	26697	26722	26708	16729	3	16702	80010	20	80000	20	80000	26722	26722	1	1	80021	10	9	10	10	80000	80000	0	10	80000	0	0	80035	0	0	0	35	80035	6	1	35	39	0	0	5020	2	16	2	2	26719	6	6	2	80000	10	26723	26723	26709	26723	26723
80024	26722	200	0	0	0	1	0	0	65	0	0	0	1	26707	0	18	18	12	25	80010	10	80000	10	80000	50	1172694	0	26697	26722	26722	16652	3	16688	80010	20	80000	20	80000	26722	26722	1	1	80021	10	9	10	10	80000	80000	0	10	80000	0	0	80035	0	0	0	0	80035	0	0	35	39	0	0	5020	2	16	2	6	26705	6	6	2	80000	10	26723	26709	26723	26723	26723
80024	26708	200	0	0	0	0	0	0	41	0	0	0	1	26693	2	18	18	12	25	80010	10	80000	10	80000	50	1166750	0	26697	26722	26708	16667	3	16833	80010	20	80000	20	80000	26722	26722	1	1	80021	10	9	10	10	80000	80000	0	10	80000	0	0	80000	0	0	0	35	80035	6	1	35	39	0	0	5020	2	16	6	2	26719	6	6	2	80000	10	26723	26723	26723	26723	26723
80024	26722	200	0	0	0	1	1	0	21	0	1	0	3	26717	2	18	18	14	25	80010	10	80000	10	80000	50	1173032	0	26708	26722	26708	16667	3	16702	80010	20	80000	20	80000	26722	26722	1	1	80021	10	9	10	10	80000	80000	0	10	80000	0	39	80035	0	0	0	35	80035	6	0	35	39	0	0	5020	2	16	6	2	26705	6	6	2	80000	10	26723	26723	26709	26723	26709

LDUR (S)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->2 roundtrip

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations