Firestorm: MLA (by element, 2S) measurements

Code:

  mla v0.2s, v1.2s, v2.s[1]

Initialization

  movi v0.16b, 1
  movi v1.16b, 2
  movi v2.16b, 3

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	19	1e	3f	4e	51	schedule uop (52)	schedule simd uop (54)	dispatch simd uop (57)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map simd uop (7e)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst simd alu (9a)	l1d tlb miss (a1)	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	f5	f6	f7	f8	fd
1004	3037	25	0	0	61	2548	25	1000	1000	1000	398313	0	3018	3037	3037	2415	3	2895	1000	1000	3000	3037	3037	1	1	1001	1000	0	0	0	73	1	16	1	1	2630	1000	3038	3038	3038	3038	3038
1004	3037	24	0	9	61	2548	25	1000	1000	1000	398313	1	3018	3037	3037	2415	3	2895	1000	1000	3000	3037	3037	1	1	1001	1000	0	0	0	73	1	16	1	1	2630	1000	3038	3038	3038	3038	3038
1004	3037	24	0	0	61	2548	25	1000	1000	1000	398313	1	3018	3037	3037	2415	3	2895	1000	1000	3000	3037	3037	1	1	1001	1000	0	0	0	73	1	16	1	1	2630	1000	3038	3038	3038	3038	3038
1004	3037	24	0	0	61	2548	25	1000	1000	1000	398313	1	3018	3037	3037	2415	3	2895	1000	1000	3000	3037	3037	1	1	1001	1000	0	0	0	73	1	16	1	1	2630	1000	3038	3038	3038	3038	3038
1004	3037	25	0	0	84	2548	25	1000	1000	1000	398313	0	3018	3037	3037	2415	3	2895	1000	1000	3000	3037	3037	1	1	1001	1000	0	0	0	73	1	16	1	1	2630	1000	3038	3038	3038	3038	3038
1004	3037	24	0	0	61	2548	25	1000	1000	1000	398313	1	3018	3037	3037	2415	3	2895	1000	1000	3000	3037	3037	1	1	1001	1000	0	0	0	73	1	16	1	1	2630	1000	3038	3038	3038	3038	3038
1004	3037	24	0	0	61	2548	25	1000	1000	1000	398313	0	3018	3037	3037	2415	3	2895	1000	1000	3000	3037	3037	1	1	1001	1000	0	0	0	73	1	16	1	1	2630	1000	3038	3038	3038	3038	3038
1004	3037	25	0	0	61	2548	25	1000	1000	1000	398313	0	3018	3037	3037	2415	3	2895	1000	1000	3000	3037	3037	1	1	1001	1000	0	0	0	73	1	16	1	1	2630	1000	3038	3038	3038	3038	3038
1004	3037	24	0	0	61	2548	25	1000	1000	1000	398313	1	3018	3037	3037	2415	3	2895	1000	1000	3000	3037	3037	1	1	1001	1000	0	0	0	73	1	16	1	1	2630	1000	3038	3038	3038	3038	3038
1004	3037	24	0	0	61	2548	25	1000	1000	1000	398313	0	3018	3037	3037	2415	3	2895	1000	1000	3000	3037	3037	1	1	1001	1000	0	0	0	73	1	16	1	1	2630	1000	3038	3038	3038	3038	3038

Test 2: Latency 1->1

Code:

  mla v0.2s, v1.2s, v2.s[1]

Initialization

  movi v0.16b, 1
  movi v1.16b, 2
  movi v2.16b, 3

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	09	l2 tlb miss data (0b)	18	19	1e	3a	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	c2	cf	d0	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10204	30037	224	0	0	0	0	0	0	61	29548	25	10100	100	10000	100	10000	500	4277313	30018	30037	30037	28265	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	710	0	2	16	2	3	29634	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	0	0	300	0	61	29548	25	10100	100	10000	100	10000	500	4277313	30018	30037	30037	28265	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	710	1	2	16	2	2	29634	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	0	0	0	0	61	29548	25	10100	100	10000	100	10000	500	4277313	30018	30037	30037	28265	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	710	1	2	16	2	2	29634	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	0	0	474	0	61	29548	25	10100	100	10000	100	10000	500	4277313	30018	30037	30037	28265	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	710	1	2	16	2	2	29634	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	0	0	480	0	61	29548	25	10100	100	10000	100	10000	500	4277313	30018	30037	30037	28265	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	710	1	2	16	2	2	29634	0	10000	100	30038	30038	30038	30038	30038
10204	30037	224	0	0	0	0	429	0	599	29548	25	10100	100	10000	100	10000	500	4277313	30018	30037	30037	28265	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	710	1	2	16	2	2	29634	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	0	0	0	0	61	29548	25	10100	100	10000	100	10000	500	4277313	30018	30037	30037	28265	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	710	1	2	16	2	2	29634	0	10000	100	30038	30038	30038	30038	30038
10204	30037	224	0	0	0	0	495	0	61	29548	25	10100	100	10000	100	10000	500	4277313	30018	30037	30037	28265	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	712	1	2	25	2	2	29634	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	0	0	513	0	61	29548	25	10100	100	10000	100	10000	500	4277313	30018	30037	30037	28265	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	3	0	710	1	2	16	2	2	29634	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	0	0	471	0	61	29548	25	10100	100	10000	100	10000	500	4277313	30018	30037	30037	28265	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	710	1	2	16	2	2	29634	0	10000	100	30038	30038	30038	30038	30038

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l2 tlb miss data (0b)	18	19	1e	1f	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	ld unit uop (a6)	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10024	30037	225	0	0	0	96	0	61	29548	25	10010	10	10000	10	10000	50	4277313	1	30018	30037	30037	28287	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	640	2	16	2	2	29630	0	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	0	525	0	61	29548	25	10010	10	10000	10	10000	50	4277313	0	30018	30037	30037	28287	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	640	2	16	2	2	29630	0	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	0	12	0	170	29548	25	10010	10	10000	10	10000	50	4277313	1	30018	30037	30037	28287	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	640	2	16	2	2	29630	0	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	0	444	0	61	29548	25	10010	10	10000	10	10000	50	4277313	1	30018	30037	30037	28287	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	640	2	16	2	3	29630	0	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	0	285	0	726	29548	25	10010	10	10000	10	10000	50	4277313	1	30018	30037	30037	28287	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	640	2	16	2	2	29630	0	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	0	447	0	61	29548	25	10010	10	10000	10	10000	50	4277313	1	30018	30037	30037	28287	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	640	3	16	2	2	29630	0	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	0	456	0	61	29548	25	10010	10	10000	10	10000	50	4277313	1	30018	30037	30037	28287	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	640	2	16	3	2	29630	0	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	0	411	0	61	29548	25	10010	10	10000	10	10000	50	4277313	1	30018	30037	30037	28287	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	640	3	16	3	2	29630	0	10000	10	30038	30038	30038	30038	30038
10024	30037	224	0	0	0	0	0	61	29548	25	10010	10	10000	10	10000	50	4277313	0	30018	30037	30037	28287	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	640	2	16	2	2	29630	0	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	0	3	0	61	29548	25	10010	10	10000	10	10000	50	4277313	0	30018	30037	30037	28287	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	640	2	16	2	2	29630	0	10000	10	30038	30038	30038	30038	30038

Test 3: Latency 1->2

Code:

  mla v0.2s, v0.2s, v1.s[1]

Initialization

  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	l2 tlb miss data (0b)	18	19	1e	1f	3a	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	c2	branch mispred nonspec (cb)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10204	30037	225	0	0	0	0	36	0	0	61	29548	25	10100	100	10000	100	10000	500	4277313	0	30018	0	30037	30037	28265	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	0	710	1	16	1	1	29634	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	0	0	0	0	0	61	29548	25	10100	100	10000	100	10000	500	4277313	0	30018	0	30037	30037	28265	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	0	710	1	16	1	1	29634	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	0	0	6	0	0	61	29548	25	10100	100	10000	100	10000	500	4277313	0	30018	0	30037	30037	28265	3	28745	10262	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	0	710	1	16	1	1	29634	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	0	0	39	0	0	61	29548	25	10100	100	10000	100	10000	500	4277313	0	30018	0	30037	30037	28265	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	0	710	1	16	1	1	29634	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	0	0	18	0	0	61	29548	25	10100	100	10000	100	10000	500	4277313	0	30018	0	30037	30037	28265	3	28745	10100	200	10000	204	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	0	710	1	16	2	1	29634	0	10000	100	30038	30038	30038	30038	30038
10204	30037	224	0	0	0	0	54	0	0	61	29548	25	10100	100	10000	100	10000	500	4277313	0	30018	0	30037	30037	28265	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	0	710	1	16	1	1	29634	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	0	0	6	0	0	61	29548	25	10100	100	10000	100	10000	500	4277313	0	30018	0	30037	30037	28265	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	0	710	1	16	1	1	29634	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	0	0	6	0	0	61	29548	25	10100	100	10000	100	10000	500	4277313	0	30018	0	30037	30037	28265	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	0	710	1	16	1	1	29634	0	10000	100	30038	30038	30038	30038	30038
10204	30037	226	0	0	0	0	6	0	0	726	29548	25	10100	100	10000	100	10000	500	4277313	0	30018	0	30037	30037	28265	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	0	710	1	16	1	1	29634	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	0	0	3	0	0	536	29548	25	10100	100	10000	100	10000	500	4277313	1	30018	0	30037	30037	28265	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	0	710	1	16	1	1	29634	0	10000	100	30038	30038	30038	30038	30038

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l2 tlb miss data (0b)	1e	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	ld unit uop (a6)	l1d cache writeback (a8)	ac	c3	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	ec	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10024	30037	225	0	180	82	29548	25	10010	10	10000	10	10000	50	4277313	30018	30037	30037	28287	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	640	2	16	2	2	29630	0	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	18	61	29548	25	10010	10	10000	10	10000	50	4277313	30018	30037	30037	28287	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	3	0	0	640	2	16	2	2	29630	0	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	36	61	29548	25	10010	10	10000	10	10000	50	4277313	30018	30037	30037	28287	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	640	2	16	2	2	29630	0	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	468	61	29548	25	10010	10	10000	10	10000	50	4277313	30018	30037	30037	28287	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	640	2	16	2	2	29630	0	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	15	82	29548	25	10010	10	10000	10	10000	50	4277313	30018	30037	30037	28287	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	640	2	16	2	2	29630	1	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	12	61	29548	25	10010	10	10000	10	10000	50	4277313	30018	30037	30037	28287	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	640	2	16	2	2	29630	0	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	33	61	29548	25	10010	10	10000	10	10000	50	4277313	30018	30037	30037	28287	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	640	2	16	2	2	29630	0	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	6	61	29548	25	10010	10	10000	10	10000	50	4277313	30018	30037	30037	28287	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	640	2	16	2	2	29630	0	10000	10	30038	30038	30038	30084	30038
10024	30037	225	0	66	61	29548	25	10010	10	10000	10	10000	50	4277313	30018	30037	30037	28287	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	640	2	16	2	2	29630	0	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	15	61	29548	25	10010	10	10000	10	10000	50	4277313	30018	30037	30037	28287	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	4	0	2	0	0	0	640	2	16	2	2	29630	0	10000	10	30038	30038	30038	30038	30038

Test 4: Latency 1->3

Code:

  mla v0.2s, v1.2s, v0.s[1]

Initialization

  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	1e	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	61	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d cache writeback (a8)	ac	branch mispred nonspec (cb)	cf	d0	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10204	30037	225	0	0	61	29548	25	10100	100	10000	100	10000	500	4277313	0	2	30018	30037	30037	28265	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	96	0	710	2	2	16	2	2	29634	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	61	29548	25	10100	100	10000	100	10000	500	4277313	1	2	30018	30037	30037	28265	3	28745	10100	200	10000	200	30000	30037	30084	1	1	10201	100	99	100	100	10000	100	0	84	0	710	2	2	16	2	2	29634	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	61	29548	25	10100	100	10000	100	10000	500	4277313	1	0	30018	30037	30037	28265	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	4	0	0	710	2	2	16	2	2	29634	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	61	29548	25	10100	100	10000	100	10000	500	4277313	1	2	30018	30037	30037	28265	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	27	0	710	2	2	16	2	2	29634	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	61	29548	25	10100	100	10000	100	10000	500	4277313	1	0	30018	30037	30037	28265	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	36	0	710	2	2	16	2	2	29634	0	10000	100	30038	30038	30038	30038	30038
10204	30037	224	0	0	713	29548	25	10100	100	10000	100	10000	500	4277313	1	2	30018	30037	30037	28265	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	15	0	710	2	2	16	2	2	29634	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	61	29548	25	10100	100	10000	100	10000	500	4277313	0	2	30018	30037	30037	28265	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	87	0	710	2	2	16	2	2	29634	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	61	29548	25	10100	100	10000	100	10000	500	4277313	1	2	30018	30037	30037	28265	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	710	2	2	16	2	2	29634	0	10000	100	30038	30038	30038	30085	30038
10204	30037	225	0	105	61	29548	25	10100	100	10000	100	10000	500	4277313	1	2	30018	30037	30037	28265	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	36	0	710	0	2	16	2	2	29634	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	61	29548	25	10100	100	10000	100	10000	500	4277313	0	2	30018	30037	30037	28265	3	28762	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	710	2	2	16	2	2	29634	0	10000	100	30038	30038	30038	30038	30038

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l2 tlb miss data (0b)	1e	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	61	69	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache writeback (a8)	ac	c2	cf	d0	d2	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10024	30037	225	0	0	105	29548	25	10010	10	10000	10	10000	50	4277313	0	0	30018	0	30037	30037	28287	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	6	0	640	0	0	3	16	2	2	29630	0	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	61	29548	25	10010	10	10000	10	10000	50	4277313	0	0	30018	0	30037	30037	28287	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	93	0	640	0	0	2	16	2	2	29630	0	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	61	29548	25	10010	10	10000	10	10000	50	4277313	0	0	30018	0	30037	30037	28287	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	69	0	640	0	0	2	16	2	2	29630	0	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	61	29548	25	10010	10	10000	10	10000	50	4277313	1	0	30018	0	30037	30037	28287	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	99	0	640	0	0	2	16	2	2	29630	0	10000	10	30038	30038	30038	30038	30038
10024	30037	224	0	0	61	29548	25	10010	10	10000	10	10000	50	4277313	1	0	30018	0	30037	30037	28287	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	90	0	640	0	0	2	16	2	2	29630	0	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	232	29548	25	10010	10	10000	10	10000	50	4277313	1	0	30018	0	30037	30037	28287	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	81	0	640	0	0	2	16	2	2	29630	0	10000	10	30038	30038	30038	30038	30038
10024	30037	224	0	0	61	29548	25	10010	10	10000	10	10000	50	4277313	1	0	30018	0	30037	30037	28287	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	3	0	640	0	0	2	16	2	2	29630	0	10000	10	30038	30038	30038	30038	30038
10024	30037	224	0	0	61	29548	25	10010	10	10000	10	10000	50	4277313	1	0	30018	0	30037	30037	28287	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	96	0	640	0	0	2	16	2	2	29630	0	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	61	29548	25	10010	10	10000	10	10000	50	4277313	1	0	30018	0	30060	30037	28287	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	87	0	640	0	0	2	16	2	2	29630	0	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	61	29548	25	10010	10	10000	10	10000	50	4277313	1	0	30018	0	30037	30037	28287	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	90	0	640	0	0	2	16	2	2	29630	0	10000	10	30038	30038	30038	30038	30038

Test 5: throughput

Count: 8

Code:

  movi v0.16b, 0
  mla v0.2s, v8.2s, v9.s[1]
  movi v1.16b, 0
  mla v1.2s, v8.2s, v9.s[1]
  movi v2.16b, 0
  mla v2.2s, v8.2s, v9.s[1]
  movi v3.16b, 0
  mla v3.2s, v8.2s, v9.s[1]
  movi v4.16b, 0
  mla v4.2s, v8.2s, v9.s[1]
  movi v5.16b, 0
  mla v5.2s, v8.2s, v9.s[1]
  movi v6.16b, 0
  mla v6.2s, v8.2s, v9.s[1]
  movi v7.16b, 0
  mla v7.2s, v8.2s, v9.s[1]

Initialization

  movi v8.16b, 9
  movi v9.16b, 10

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2508

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l2 tlb miss data (0b)	18	19	1e	1f	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d cache writeback (a8)	a9	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160204	20091	150	0	0	0	0	0	62	25	80100	100	80000	100	80000	500	640000	0	20045	20064	20064	3	22	80100	200	80000	200	240000	20064	20064	1	1	160201	100	99	100	100	160000	100	0	0	0	10111	1	16	1	1	20061	160000	100	20065	20065	20065	20065	20065
160204	20064	150	0	0	1	0	264	39	25	80100	100	80000	100	80000	500	640000	0	20045	20064	20064	3	22	80538	200	80000	200	240000	20064	20064	1	1	160201	100	99	100	100	160000	100	0	0	0	10111	1	16	1	1	20061	160000	100	20065	20065	20065	20065	20065
160204	20064	151	0	0	0	0	0	81	25	80100	100	80000	100	80000	500	640000	0	20045	20064	20064	3	22	80100	200	80000	200	240000	20064	20064	1	1	160201	100	99	100	100	160000	100	0	0	0	10111	1	16	1	1	20061	160000	100	20065	20065	20065	20065	20065
160204	20064	151	1	0	0	0	0	39	25	80100	100	80000	100	80000	500	640000	0	20045	20064	20064	3	22	80330	200	80000	200	240000	20064	20064	1	1	160201	100	99	100	100	160000	100	0	0	0	10111	1	16	1	1	20061	160000	100	20065	20065	20065	20065	20065
160204	20064	150	0	0	0	12	0	39	25	80100	100	80000	100	80000	500	640000	0	20045	20305	20064	3	22	80100	200	80000	200	240000	20064	20064	1	1	160201	100	99	100	100	160000	100	0	2	0	10111	1	16	1	1	20061	160000	100	20065	20065	20065	20065	20065
160204	20064	150	0	0	0	0	0	39	25	80100	100	80000	100	80000	500	640000	0	20045	20064	20064	3	22	80100	200	80000	200	240000	20064	20064	1	1	160201	100	99	100	100	160000	100	0	0	12	10111	1	16	1	1	20061	160000	100	20065	20065	20065	20065	20065
160204	20064	150	0	0	1	12	0	39	25	80100	100	80000	100	80000	500	640000	0	20045	20064	20064	3	22	80229	200	80000	200	240000	20064	20064	1	1	160201	100	99	100	100	160000	100	9	0	0	10111	1	16	1	1	20061	160000	100	20065	20065	20065	20065	20065
160204	20064	150	0	0	0	0	0	39	25	80100	100	80000	100	80000	500	640000	0	20045	20064	20064	3	22	80100	200	80000	200	240000	20064	20064	1	1	160201	100	99	100	100	160000	100	0	0	3	10111	1	16	1	1	20061	160000	100	20065	20065	20065	20065	20065
160204	20064	150	0	0	0	0	0	39	25	80100	123	80000	100	80000	500	640000	0	20045	20064	20064	3	22	80100	200	80417	200	240000	20064	20064	1	1	160201	100	99	100	100	160000	100	0	0	0	10111	1	16	1	1	20061	160000	100	20065	20065	20065	20065	20146
160204	20064	150	0	0	0	0	0	39	25	80100	100	80000	118	80000	500	640000	0	20045	20064	20064	3	22	80100	200	80000	200	240000	20064	20064	1	1	160201	100	99	100	100	160000	100	0	0	0	10111	1	16	1	1	20061	160000	100	20065	20065	20065	20065	20065

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2506

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	18	1e	3a	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	5f	60	61	69	6d	6e	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d cache writeback (a8)	a9	ac	branch cond mispred nonspec (c5)	cf	d0	d2	l1i cache miss demand (d3)	d5	map dispatch bubble (d6)	d9	da	db	dd	fetch restart (de)	e0	? int output thing (e9)	ea	ec	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160024	20087	150	0	0	1	45	106	80012	12	80000	12	80000	62	640000	1	0	10	20032	20051	20051	3	22	80012	20	80000	20	240000	20051	20051	1	1	160021	10	9	10	10	160000	10	1	0	0	0	10040	3	4	1	15	25	2	1	1	16	18	20048	2	20	1	160000	10	20052	20052	20052	20052	20052
160024	20051	150	0	21	0	45	80	80012	12	80000	12	80000	62	640000	1	1	10	20032	20051	20051	3	22	80012	20	80000	20	240000	20051	20051	1	1	160021	10	9	10	10	160000	10	6	0	6	0	10039	13	6	1	15	25	2	1	1	15	18	20048	2	20	1	160000	10	20052	20052	20052	20052	20052
160024	20051	150	1	0	0	45	64	80012	12	80000	12	80000	62	640000	1	0	0	20032	20051	20051	3	22	80012	20	80000	20	240000	20051	20051	1	1	160021	10	9	10	10	160000	10	0	0	33	0	10037	13	6	1	18	83	2	1	1	16	14	20048	2	20	1	160000	10	20052	20052	20052	20052	20052
160024	20051	150	0	0	0	45	69	80012	12	80000	12	80000	62	640000	1	1	0	20032	20051	20051	3	22	80012	20	80000	20	240000	20051	20051	1	1	160021	10	9	10	10	160000	10	7	0	0	0	10041	13	4	1	14	25	2	1	1	15	16	20048	2	20	1	160000	10	20052	20052	20052	20052	20052
160024	20051	150	0	0	0	45	57	80012	12	80000	12	80000	62	640000	1	0	10	20032	20051	20051	3	22	80012	20	80000	20	240000	20051	20051	1	1	160021	10	9	10	10	160000	10	41	0	3	0	10041	13	4	1	16	25	2	1	1	16	17	20048	2	20	1	160000	10	20052	20052	20052	20052	20052
160024	20051	150	0	0	0	45	51	80012	12	80000	12	80000	62	640000	1	0	0	20032	20051	20051	3	22	80012	20	80000	20	240000	20051	20051	1	1	160021	10	9	10	10	160000	10	37	0	102	0	10041	13	4	1	18	25	2	1	1	16	18	20048	2	20	1	160000	10	20052	20052	20052	20052	20052
160024	20051	150	0	0	0	45	57	80012	12	80000	12	80000	62	640000	1	0	10	20032	20051	20051	3	22	80012	20	80000	20	240000	20051	20051	1	1	160021	10	9	10	10	160000	10	31	0	0	0	10041	13	5	1	18	25	2	1	1	16	17	20048	2	20	1	160000	10	20052	20052	20052	20052	20052
160024	20051	150	0	0	0	45	63	80012	12	80000	12	80000	62	640000	1	1	10	20032	20051	20051	3	22	80012	20	80000	20	240000	20051	20051	1	1	160021	10	9	10	10	160000	10	0	0	0	0	10039	13	5	1	16	25	2	1	1	18	16	20048	2	20	1	160000	10	20052	20052	20052	20052	20052
160024	20051	150	0	0	0	45	50	80012	12	80000	12	80000	62	640000	1	0	10	20032	20051	20051	3	22	80012	20	80000	20	240000	20051	20051	1	1	160021	10	9	10	10	160000	10	51	0	3	0	10040	13	1	1	15	25	2	1	1	18	16	20048	2	20	1	160000	10	20052	20052	20052	20052	20052
160024	20051	150	0	9	0	66	82	80012	12	80000	12	80000	62	640000	1	1	0	20032	20051	20051	3	22	80012	20	80000	20	240000	20051	20051	1	1	160021	10	9	10	10	160000	10	0	0	108	0	10037	13	6	1	16	25	2	1	1	16	19	20048	2	20	1	160000	10	20052	20052	20052	20052	20052

Test 6: throughput

Count: 12

Code:

  mla v0.2s, v12.2s, v13.s[1]
  mla v1.2s, v12.2s, v13.s[1]
  mla v2.2s, v12.2s, v13.s[1]
  mla v3.2s, v12.2s, v13.s[1]
  mla v4.2s, v12.2s, v13.s[1]
  mla v5.2s, v12.2s, v13.s[1]
  mla v6.2s, v12.2s, v13.s[1]
  mla v7.2s, v12.2s, v13.s[1]
  mla v8.2s, v12.2s, v13.s[1]
  mla v9.2s, v12.2s, v13.s[1]
  mla v10.2s, v12.2s, v13.s[1]
  mla v11.2s, v12.2s, v13.s[1]

Initialization

  movi v12.16b, 13
  movi v13.16b, 14

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2503

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk instruction (07)	mmu table walk data (08)	09	l2 tlb miss instruction (0a)	l2 tlb miss data (0b)	1e	37	3a	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d cache writeback (a8)	a9	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
120204	30227	234	1	0	1	1	0	0	0	2	51	0	25	120117	100	120000	100	120000	500	990000	30020	30039	30039	14973	3	16732	120100	200	120000	200	360000	30039	30039	1	1	120201	100	99	100	100	120000	100	0	31	0	0	7614	12	16	11	11	30036	120000	100	30040	30040	30040	30040	30040
120204	30039	225	1	0	0	1	0	0	0	2	51	0	25	120100	100	120000	100	120000	500	960000	30020	30041	30039	14973	3	14997	120100	200	120000	200	360000	30039	30039	1	1	120201	100	99	100	100	120000	100	0	30	0	6	7614	8	16	10	10	30036	120000	100	30040	30040	30040	30040	30040
120204	30039	225	1	0	0	1	0	0	0	2	64	0	25	120100	100	120000	100	120000	500	960000	30020	30039	30089	14973	3	14997	120100	200	120000	200	360000	30040	30042	1	1	120201	100	99	100	100	120000	100	0	33	0	2053	7614	11	16	11	10	30036	120000	100	30040	30040	30040	30040	30043
120204	30039	225	1	0	0	1	0	186	0	2	51	0	25	120117	100	120000	100	120000	500	960000	30020	30039	30039	14973	3	14997	120100	200	120000	200	360000	30039	30039	1	1	120201	100	99	100	100	120000	100	0	3	0	3	7614	10	16	10	11	30036	120000	100	30040	30040	30040	31754	30923
120204	30039	224	1	0	0	1	0	0	0	2	51	0	25	120100	100	120000	100	120000	500	960000	30020	30039	31750	14973	3	14997	120100	200	120000	200	360000	30039	30039	1	1	120201	100	99	100	100	120000	100	0	1	0	0	7614	10	16	10	11	30036	120000	100	30040	30040	30041	30040	30040
120204	30039	225	1	0	0	1	0	0	79	2	51	0	25	120100	100	120001	100	120000	500	960000	30020	30039	30039	14973	3	14997	120100	200	120000	200	360000	30039	30039	1	1	120201	100	99	100	100	120000	100	0	37	0	3	7614	11	16	10	10	30036	120000	100	30040	30040	30041	30042	30040
120204	30039	225	1	0	0	1	0	0	0	2	51	0	25	120100	100	120000	100	120000	500	960000	30020	30039	30039	14973	3	14997	120100	200	120000	200	360000	30039	30039	1	1	120201	100	99	100	100	120000	100	0	1	0	0	7614	11	16	10	11	30036	120000	100	30040	30040	30040	30040	30040
120204	30039	224	1	0	0	1	0	0	0	2	51	0	25	120100	100	120000	100	120000	500	960000	30020	30039	30039	15828	3	14997	120100	200	120000	200	360000	30039	30039	1	1	120201	100	99	100	100	120000	100	0	1	0	63	7614	11	16	11	11	30036	120000	100	30040	30040	30040	30040	30040
120204	30039	225	1	0	0	1	0	0	0	2	151	0	25	120100	100	120017	100	120000	500	960000	30020	30039	30039	14973	3	14997	120100	200	120000	200	360000	30039	30039	1	1	120201	100	99	100	100	120000	100	0	0	0	0	7614	10	16	10	11	30036	120000	100	30040	30040	30040	30040	30040
120204	30039	225	1	0	0	1	0	0	0	2	51	0	25	120117	100	120000	100	120000	500	960000	30020	30039	30039	14973	3	15000	120100	200	120000	200	360000	30039	30039	1	1	120201	100	99	100	100	120000	100	0	1	0	0	7614	8	16	11	11	30037	120000	100	30040	30040	30041	30040	30040

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2503

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	1e	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	5f	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb miss (a1)	l1d cache writeback (a8)	ac	branch cond mispred nonspec (c5)	cf	d0	d2	l1i cache miss demand (d3)	d5	map dispatch bubble (d6)	d9	da	db	dd	fetch restart (de)	e0	ea	eb	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
120024	30040	225	0	0	46	25	120010	10	120000	10	120000	50	960000	1	1	30020	30039	30039	14996	3	15019	120010	20	120000	20	360000	30039	30039	1	1	120021	10	9	10	10	120000	10	0	0	0	0	7524	6	2	2	29	16	4	1	1	5	7	30036	20	6	120000	10	30040	30040	30040	30040	30040
120024	30039	225	0	0	52	25	120010	10	120017	10	120000	50	960000	1	1	30020	30039	30039	14996	3	15019	120010	20	120000	20	360000	30039	30039	1	1	120021	10	9	10	10	120000	10	0	0	0	0	7524	6	2	2	14	16	4	2	2	14	8	30036	40	12	120000	10	30040	30040	30040	30040	30040
120024	30039	225	0	0	52	25	120010	10	120000	10	120000	50	960000	1	1	30020	30039	30039	14996	3	15019	120010	20	120000	20	360000	30039	30039	1	1	120021	10	9	10	10	120000	10	0	0	0	0	7522	3	1	1	9	16	2	1	1	8	14	30036	20	6	120000	10	30040	30040	30040	30040	30040
120024	30039	225	0	0	46	25	120010	10	120000	10	120000	50	960000	0	1	30020	30039	30039	14996	3	15019	120010	20	120000	20	360000	30039	30039	1	1	120021	10	9	10	10	120000	10	0	0	0	0	7522	3	1	1	13	16	2	1	1	5	13	30036	20	6	120000	10	30040	30040	30040	30040	30040
120024	30039	224	1	0	46	25	120010	10	120000	10	120000	50	960000	0	1	30020	30039	30039	16670	3	15019	120010	20	120000	20	360000	30039	30039	1	1	120021	10	9	10	10	120000	10	0	0	0	0	7524	3	1	1	7	16	2	1	1	6	6	30036	20	12	120000	10	30040	30040	30040	30040	30040
120024	30039	224	0	0	46	25	120010	10	120000	10	120000	50	960000	0	1	30020	30039	30922	14996	3	15019	120010	20	120000	20	360000	30039	30039	1	1	120021	10	9	10	10	120000	10	0	0	0	0	7522	3	2	1	8	16	2	1	1	11	4	30036	20	6	120000	10	30040	30040	30040	30040	30040
120024	30039	225	0	27	52	25	120010	10	120000	10	120000	50	960000	0	1	30020	30039	30039	14996	3	15019	120010	20	120000	20	360000	30039	30039	1	1	120021	10	9	10	10	120000	10	0	0	0	1	7522	3	1	1	5	16	2	1	1	5	6	30036	20	13	120000	10	30040	30040	30040	30040	30040
120024	30922	225	0	0	46	25	120010	10	120000	10	120000	50	960000	1	1	30020	30039	30039	14996	3	15019	120010	20	120000	20	360000	30039	30039	1	1	120021	10	9	10	10	120000	10	0	0	0	0	7522	3	1	1	7	16	2	1	1	6	13	30036	20	6	120000	10	30040	30040	30040	30040	30040
120024	30039	225	0	0	46	25	120010	10	120000	10	120000	50	960000	1	1	30020	30039	30039	14996	3	15019	120010	20	120000	20	360000	30039	30039	1	1	120021	10	9	10	10	120000	10	0	0	0	0	7522	3	1	1	5	16	2	1	1	7	7	30036	20	6	120000	10	30040	30040	30040	30040	30040
120024	30039	225	0	0	46	25	120010	10	120000	10	120000	50	960000	1	1	30020	30039	30039	14996	3	15019	120010	20	120000	20	360000	30039	30039	1	1	120021	10	9	10	10	120000	10	0	0	0	0	7522	3	1	1	5	16	2	1	1	6	6	30036	20	6	120000	10	30040	30040	30040	30040	30040

MLA (by element, 2S)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->1

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: Latency 1->2

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 4: Latency 1->3

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 5: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 6: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations