Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

MLA (by element, 8H)

Test 1: uops

Code:

  mla v0.8h, v1.8h, v2.h[1]
  movi v0.16b, 1
  movi v1.16b, 2
  movi v2.16b, 3

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

retire uop (01)cycle (02)031e3f4e51schedule uop (52)schedule simd uop (54)dispatch simd uop (57)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map simd uop (7e)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst simd alu (9a)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)f5f6f7f8fd
100430372306125482510001000100039831313018303730372415328951000100030003037303711100110000073116112630100030383038303830383038
100430372306125482510001000100039831313018303730372415328951000100030003037303711100110000073116112630100030383038303830383038
1004303723015625482510001000100039831313018303730372415328951000100030003037303711100110000073116112630100030383038303830383038
100430372306125482510001000100039831313018303730372415328951000100030003037303711100110000073116112630100030383038303830383038
100430372306125482510001000100039831313018303730372415328951000100030003037303711100110000073116112630100030383038303830383038
100430372306125482510001000100039831313018303730372415328951000100030003037303711100110000073116112630100030383038303830383038
100430372306125482510001000100039831313018303730372415328951000100030003037303711100110000073116112630100030383038303830383038
100430372206125482510001000100039831313018303730372415328951000100030003037303711100110000073116112630100030383038303830383038
100430372306125482510001000100039831313018303730372415328951000100030003037303711100110000073116112630100030383038303830383038
100430372306125482510001000100039831313018303730372415328951000100030003037303711100110000073116112630100030383038303830383038

Test 2: Latency 1->1

Code:

  mla v0.8h, v1.8h, v2.h[1]
  movi v0.16b, 1
  movi v1.16b, 2
  movi v2.16b, 3

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)031e3a3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)a9accfd0d5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
102043003722500612954825101001001000010010000500427731303001830037300372826532874510100200100002003000030037300371110201100991001001000010000071012162229634100001003003830038300383003830038
102043008422500612954825101001001000010010000500427731303001830037300372826532874510100200100002003000030037300371110201100991001001000010000071012162229634100001003003830038300383003830038
102043003722500822954825101001001000010010000500427731303001830037300372826532874510100200100002003000030037300371110201100991001001000010000071012162229634100001003003830038300383003830038
102043003722500612954825101001001000010010000500427731303001830037300372826532874510100200100002003000030037300371110201100991001001000010000071012162229634100001003003830038300383003830038
102043003722590612953625101001001000010010000500427731303005430037300372826532874510100200100002003000030037300371110201100991001001000010000071012162329634100001003003830038300383003830038
102043003722501612954825101001001000010010000500427731313001830037300372826532874510100200100002003000030037300371110201100991001001000010000071212162229634100001003003830038300383003830038
102043003722400612954825101001001000010010000500427731313001830037300372826532874510100200100002003000030037300371110201100991001001000010000071012162229634100001003003830038300383003830038
102043003722500612954825101001001000010010000500427731313001830037300372826532874510100200100002003000030037300371110201100991001001000010000071012162229634100001003003830038300383003830038
102043003722500612954825101001001000010010000500427731303001830037300372826532874510100200100002003000030037300371110201100991001001000010000071002162229634100001003003830038300383003830038
1020430037224001032954825101001001000010010000500427731303001830037300372826532874510100200100002003000030037300371110201100991001001000010000071012162229634100001003003830038300383003830038

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)031e1f3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)simd prf full (72)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)st unit uop (a7)l1d cache writeback (a8)accdcfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
10024300372250025129548251001010100001010000504277313030018300373003728287032876710010201000020300003003730037111002110910101000010000390640216222963010000103003830038300383003830038
100243003722500612954825100101010000101000050427731303001830037300372828703287671001020100002030000300373003711100211091010100001000000640216222963010000103003830038300383003830038
100243003722500612954825100101010000101000050427731303001830037300372828703287671001020100002030000300373003711100211091010100001000000640216222963010000103003830038300383003830038
100243003722500612954825100101010000101000050427731303001830037300372828703287671001020100002030000300373003711100211091010100001000000640216222963010000103003830038300383003830038
100243003722500612954825100101010000101000050427731303001830037300372828703287671001020100002030000300373003711100211091010100001000000640216222963010000103003830038300383003830038
100243003722500612954825100101010000101000050427731303001830037300372828703287671001020100002030000300373003711100211091010100001000000640216222963010000103003830038300383003830038
100243003722500612954825100101010000101000050427731303001830037300372828703287671001020100002030000300373003711100211091010100001000000640216222963010000103003830038300383003830038
100243003722500612954825100101010000101000050427731303001830037300372828703287671001020100002030000300373003711100211091010100001000000640216222963010000103003830038300383003830038
100243003722500612954825100101010000101000050427731303001830037300372828703287671001020100002030000300373003711100211091010100001000000640216222963010000103003830038300383003830038
100243003722500612954825100101010000101000050427731303001830037300372828703287671001020100002030000300373003711100211091010100001000000640216222963010000103003830038300383003830038

Test 3: Latency 1->2

Code:

  mla v0.8h, v0.8h, v1.h[1]
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)03091e1f3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)696b6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)ld unit uop (a6)l1d cache writeback (a8)a9accfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
102043003722500061295482510100100100001001000050042773133001803003730037282653287451010020010000200300003003730037111020110099100100100001000000071021622296340100001003003830038300383003830038
10204300372240001103295482510100100100001001000050042773133001803003730037282653287451010020010000200300003003730037111020110099100100100001000000071021622296340100001003003830038300383003830038
10204300372250672061295482510100100100001001000050042773133001803003730037282653287451010020010000200300003003730037111020110099100100100001000000071021622296340100001003003830038300383003830038
102043003722500061295482510100100100001001000050042773133001803003730037282653287451010020010000200300003003730037111020110099100100100001000000071021622296340100001003003830038300383003830038
102043003722500061295482510100100100001001000050042773133001803003730037282653287451010020010000200300003003730037111020110099100100100001000000071021622296340100001003003830038300383003830038
102043003722500061295482510100100100001001000050042773133001803003730037282653287451010020010000200300003003730037111020110099100100100001000000071021622296340100001003003830038300383003830038
102043003722500061295482510100100100001001000050042773133001803003730037282653287451010020010000200300003003730037111020110099100100100001000000071021622296340100001003003830038300383003830038
1020430037225000612954825101001001000010010000500427731330018030037300372826532874510100200100002003000030037300371110201100991001001000010000000710216222963416100001003003830038300383003830038
102043003722500061295482510100100100001001000050042773133001803003730037282653287451010020010000200300003003730037111020110099100100100001000000071021622296340100001003003830038300383003830038
102043003722500061295482510100100100001001000050042773133001803003730037282653287451010020010000200300003003730037111020110099100100100001000000071021622296340100001003003830038300383003830038

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)031e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696b6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
10024300372250612954825100101010000101000050427731303001803003730037282873287671001020100002030000300373003711100211091010100001000640316332963010000103003830038300383003830038
10024300372250612954825100101010000101000050427731303001803003730037282873287671001020100002030000300373003711100211091010100001000640316332963010000103003830038300383003830038
10024300372240612954825100101010000111000050427731313001803013330037282873287671001020100002030000300373003711100211091010100001000640316332963010000103003830038300383003830038
100243003722505362954825100101010000101000050427731313001803003730037282873287671001020100002030000300373003711100211091010100001000640316332963010000103003830038300383003830038
10024300372250612954825100101010000101000050427731313001803003730037282873287671001020100002030000300373003711100211091010100001000640416332963010000103003830038300383003830038
10024300372250612954825100101010000101000050427731313001803003730037282873287671001020100002030000300373003711100211091010100001000640316332963010000103003830038300383003830038
10024300372250612954825100101010000101000050427731313001803003730037282873287671001020100002030000300373003711100211091010100001000640416332963010000103003830038300383003830038
10024300372250612954825100101010000101000050427731313001803003730037282873287671001020100002030000300373003711100211091010100001000640416332963010000103003830038300383003830038
10024300372250612954825100101010000101000050427731313001803003730037282873287671001020100002030000300373003711100211091010100001000640416332963010000103003830038300383003830038
10024300372250612954825100101010000101000050427731313001803003730037282873287671001020100002030000300373003711100211091010100001000640316332963010000103003830038300383003830038

Test 4: Latency 1->3

Code:

  mla v0.8h, v1.8h, v0.h[1]
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)033f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696b6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)acbranch cond mispred nonspec (c5)cfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
1020430037225612954825101001001000010010000500427731303001803003730037282653287451010020010000200300003003730037111020110099100100100001000007102161129634100001003003830038300383003830038
1020430037225612954825101001001000010410000500427731303001803003730037282653287451010020010000200300003003730037111020110099100100100001000007102161129634100001003003830038300383003830038
10204300372256129548251010010010000100100005004277313130018030037300372826532874510100200100002003000030037300371110201100991001001000010049007101161129634100001003003830038300383003830038
1020430037225612954825101001001000010010000500427731313001803003730037282653287451010020210494204300003003730037111020110099100100100001000007101161129634100001003003830038300383003830038
1020430037224612954825101001001000010010000500427731313001803003730037282653287451010020010000200300003003730037111020110099100100100001000007101161129634100001003003830038300383003830038
1020430037225612954825101001001000010010000500427731313001803003730037282653287451010020010000200300003003730037111020110099100100100001000007101161129634100001003003830038300383003830038
1020430037225612954825101001001000010010000500427731313001803003730037282653287451010020010000200300003003730037111020110099100100100001000007101161129634100001003003830038300383003830038
1020430037224612954825101001001000010010000500427731313001803003730037282653287451010020010000200300003003730037111020110099100100100001000007101161129634100001003003830038300383003830038
1020430037225612954825101001001000010010000500427731313001803003730037282657287451010020010000200300003003730037111020110099100100100001000607101161129634100001003003830038300383003830038
1020430037224612954825101001001000010010000500427731313001803003730037282653287451010020010000200300003003730037111020110099100100100001000007101161129634100001003003830038300383003830038

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)030f191e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)696b6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d cache writeback (a8)a9accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
10024300372250006129548251001010100001010000504277313300180300373003728287328767100102010000203000030037300371110021109101010000100000640316222963010000103003830038300383003830038
10024300372250006129548251001010100001010000504277313300180300373003728287328767100102010000203000030037300371110021109101010000100000640216222963010000103003830038300383003830038
10024300372250006129548441001010100001010000504277313300180300373003728287328767100102010000203000030037300371110021109101010000100300640216222963010000103003830038300383003830038
10024300372250006129548251001010100001010000504277313300640300373003728287328767100102010000203000030037300371110021109101010000100000640216222963010000103003830038300383003830038
10024300372250006129548251001010100001010000504277313300180300373003728287328767101582010000203000030037300371110021109101010000100000640216222963010000103003830038300383003830038
10024300372250006129548251001010100001010000504277313300180300373003728287328767100102010000203000030037300371110021109101010000100000640216222963010000103003830038300383003830038
10024300372250006129548251001010100001010000504277313300180300373003728287328767100102010000203000030037300371110021109101010000100000640216222963010000103003830038300383003830038
10024300372250006129548251001010100001010000504277313300180300373003728287328767100102010000203000030037300371110021109101010000100000640216222963010000103003830038300383003830038
10024300372250006129548251001010100001010000504277313300180300373003728287328767100102010000203000030037300371110021109101010000100000640216222963010000103003830038300383003830038
10024300372250006129548251001010100001010000504277313300180300373003728287328767100102010000203000030037300371110021109101010000100000640216222963010000103003830038300383003830038

Test 5: throughput

Count: 8

Code:

  movi v0.16b, 0
  mla v0.8h, v8.8h, v9.h[1]
  movi v1.16b, 0
  mla v1.8h, v8.8h, v9.h[1]
  movi v2.16b, 0
  mla v2.8h, v8.8h, v9.h[1]
  movi v3.16b, 0
  mla v3.8h, v8.8h, v9.h[1]
  movi v4.16b, 0
  mla v4.8h, v8.8h, v9.h[1]
  movi v5.16b, 0
  mla v5.8h, v8.8h, v9.h[1]
  movi v6.16b, 0
  mla v6.8h, v8.8h, v9.h[1]
  movi v7.16b, 0
  mla v7.8h, v8.8h, v9.h[1]
  movi v8.16b, 9
  movi v9.16b, 10

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2508

retire uop (01)cycle (02)031e3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)696d6emap rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
16020420065150039258010010080000100800005006400002004520064200643228010020080000200240000200642006411160201100991001001600001000151011221622200611600001002006520065200652006520065
1602042006415006025801001008000010080000500640000200452006420064322801002008000020024000020064200641116020110099100100160000100001011221622200611600001002006520065200652006520065
1602042006415003925801001008000010080000500640000200452006420064322801002008000020024000020145200641116020110099100100160000100001011221622200611600001002006520065200652006520065
1602042006415063925801001008000010080000500640000200452006420064322801002008000020024000020064200641116020110099100100160000100001011221622200611600001002006520065200652006520065
1602042006415003925801001008000010080000500640000200452006420064322801002008000020024000020064200641116020110099100100160000100001011221622200611600001002006520065200652006520065
1602042006415103925801001008000010080000500640000200452006420064322801002008000020024000020064200641116020110099100100160000100001011221622200611600001002006520065200652006520065
1602042006415006925801001008000010080000500640000200452006420064322801002008000020024000020064200641116020110099100100160000100001011221622200611600001002006520065200652006520065
16020420064150012325801001008000010080000500640000200452006420064322801002008000020024000020064200641116020110099100100160000100001011221622200611600001002006520065200652006520065
1602042006415003925801001008000010080000500640000200452006420064322801002008000020024000020064200641116020110099100100160000100001011221622200611600001002006520065200652006520065
1602042006415003925801001008000010080000500640000200452006420064322801002008000020024000020064200641116020110099100100160000100001011221622200611600001002006520065200652006520065

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2506

retire uop (01)cycle (02)03l2 tlb miss data (0b)18191e3a3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)5f60696b6d6emap rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)ld unit uop (a6)a9acc2branch cond mispred nonspec (c5)cfd0d2l1i cache miss demand (d3)d5map dispatch bubble (d6)d9dadbddfetch restart (de)e0? int output thing (e9)eaec? simd retires (ee)? int retires (ef)f5f6f7f8fd
1600242008515000000452780012128000012800006264000011200320200512005132280012208000020240000200512005111160021109101016000010000000100353118252111315200482201160000102005220052200522005220052
1600242005115000000452780012128000012800006264000011200320200512012132280012208000020240000200512005111160021109101016000010000000100323111225211128200482201160000102005220052200522005220052
16002420051150000004527800121280000128000062640000112003202005120051322800122080000202400002005120051111600211091010160000100000001003331114252111212200482201160000102005220052200522005220052
1600242005115000000452780012128000012800006264000011200320200512005132280012208000020240000200512005111160021109101016000010000000100363111225211128200482451160000102005220052200522005220052
1600242005115000000662780012128000012800006264000011200320200512005132280012208000020240000200512005111160021109101016000010000000100363119252111214200482201160000102005220052200522005220052
1600242005115000000452780012128000012800006264000011200320200512005132280012208000020240000200512005111160021109101016000010000000100373111225211128200482201160000102005220052200522005220052
16002420051150000004527800121280000128000062640000112003202005120051322800122080000202400002005120051111600211091010160000100000001003631112252111212200482201160000102005220052200522005220052
16002420051150000004527800121280000128000062640000112003202005120051322800122080000202400002005120051111600211091010160000100024850010037311925211914200482201160000102005220052200522005220052
1600242005115000001452780012128000012800006264000011200320200512005132280012208000020240000200512005111160021109101016000010000000100353111725211149200482201160000102005220052200522005220052
1600242005115000000452780012128000012800006264000011200320200512005132280012208000020240000200512005111160021109101016000010000000100373111225211812200482201160000102005220052200522005220052

Test 6: throughput

Count: 12

Code:

  mla v0.8h, v12.8h, v13.h[1]
  mla v1.8h, v12.8h, v13.h[1]
  mla v2.8h, v12.8h, v13.h[1]
  mla v3.8h, v12.8h, v13.h[1]
  mla v4.8h, v12.8h, v13.h[1]
  mla v5.8h, v12.8h, v13.h[1]
  mla v6.8h, v12.8h, v13.h[1]
  mla v7.8h, v12.8h, v13.h[1]
  mla v8.8h, v12.8h, v13.h[1]
  mla v9.8h, v12.8h, v13.h[1]
  mla v10.8h, v12.8h, v13.h[1]
  mla v11.8h, v12.8h, v13.h[1]
  movi v12.16b, 13
  movi v13.16b, 14

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2503

retire uop (01)cycle (02)03mmu table walk data (08)0918191e1f373f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d tlb miss (a1)ld unit uop (a6)st unit uop (a7)l1d cache writeback (a8)a9accfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
120204303432240000000412512010010012000010012000050045183741300203003930039149733150001201002001200002003600003003930039111202011009910010012000010000000007610116113003601200001003004030040300403004030040
12020430039225000000041251201001001200001001200005009600001300203003930039149733149971201002001200002003600003003930039111202011009910010012000010000000007610116113003601200001003004030040300403004030040
12020430039225000000041251201001001200001001200005009600001300203003930039149733149971201002001200002003600003003930039111202011009910010012000010000000007610116113003601200001003004030040300403004030040
12020430039225000000041251201001001200001001200005009600001300203004130039149733149971201002001205362003600003003930042111202011009910010012000010000000007610116113003601200001003004030040300403004030040
12020430039225000000041251201001001200001001200005009600001300203003930039149733158801201002001200002003600003003930039111202011009910010012000010000000007610116113003601200001003257630040300403004130040
12020430039225000000041251201001001200001001200005009600001300203003930039149736149981201002001200002003600003003930039111202011009910010012000010000000007610116113003601200001003004030042309443004030040
12020430039225000000061251201001001200001001200005009600001300203003930039149733149971201002001200002003600003003930039111202011009910010012000010000000007610116113003601200001003004030040300403004030040
12020430039225000000041251201001001200001001200005009600001300203003930039149733149971201002001200002003600003003930039111202011009910010012000010000000007610116113003601200001003004030040300403004030040
12020430039225000000046251201001001200001001200005009600001300203003930039149733149971204232001200002003600003003930039111202011009910010012000010000000007610116113003601200001003004030040300403004030041
12020430039225000000041251201001001200001001200005009600001300203003930039149733149971201002001200002003600003003930039111202011009910010012000010000000007610116113003601200001003004030040300403004030040

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2503

retire uop (01)cycle (02)0318191e373f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)5f60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d tlb miss (a1)ld unit uop (a6)l1d cache writeback (a8)accdcfd0d2l1i cache miss demand (d3)d5map dispatch bubble (d6)d9dadbddfetch restart (de)e0eaeb? simd retires (ee)? int retires (ef)f5f6f7f8fd
120024300482240012073025120010101200001012000050960000013002030039300391499531501912001020120000203600003003930039111200211091010120000100000007522321816421166300361510120000103004030040300893004030040
1200243003922500150460251200101012000010120000509600000130020300393003916670315019120010201200002036000030039300391112002110910101200001000000075223111716211161630036155120000103004030040300403004030040
120024300392250000460251200101012000010120000509600001030020300393003914996315019120010201200002036000030039300391112002110910101200001000000075223111616211161630036155120000103004030040300403004030040
1200243003922500180460251200101012000010120000509600001030020300393003914996315019120010201200002036000030039300391112002110910101200001000000075223111616421616300363010120000103004030040300403004030040
120024300392250027046025120010101200001012000050960000113002030039300391499631517912001020120000203600003003930039111200211091010120000100009607522321161621171630036155120000103004030040300403004030040
120024300392250000167025120010101200001012000050960000013002030039300391667031501912001020120000203600003003930039111200211091010120000100001007522311161621116630036155120000103004030040300403004030040
1200243003922500004602512001010120000101200005096000011300203003930039149963150191200102012000020360000300393003911120021109101012000010000000752231151621161630036155120000103004030040300403004030040
12002430039224000097902512001010120000101200005096000011300203003930039149963150191200102012000020360000300393003911120021109101012000010000000752231161621116630036155120000103004030040300403004030040
12002430039224000010902512001010120000101200005096000011300203003930039149963159021200102012000020360000300393003911120021109101012000010000000752231116162111616300361510120000103004030040300403004030040
1200243003922500270052025120010101200001012000050960000013002030039300391667031501912001020120442203600003003930039111200211091010120000100000007522321131622161730036155120000103004030040300403004030040