Firestorm: MLA (vector, 16B) measurements

Code:

  mla v0.16b, v1.16b, v2.16b

Initialization

  movi v0.16b, 1
  movi v1.16b, 2
  movi v2.16b, 3

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	3f	4e	51	schedule uop (52)	schedule simd uop (54)	dispatch simd uop (57)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map simd uop (7e)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst simd alu (9a)	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	f5	f6	f7	f8	fd
1004	3037	23	61	2548	25	1000	1000	1000	398313	1	3018	3037	3037	2415	3	2895	1000	1000	3000	3037	3037	1	1	1001	1000	0	6	73	2	16	1	1	2630	1000	3038	3038	3038	3038	3038
1004	3037	22	61	2548	25	1000	1000	1000	398313	1	3018	3037	3037	2415	3	2895	1000	1000	3000	3037	3037	1	1	1001	1000	0	24	73	1	16	1	1	2630	1000	3038	3038	3038	3038	3038
1004	3037	23	61	2548	25	1000	1000	1000	398313	1	3018	3037	3037	2415	3	2895	1000	1000	3000	3037	3037	1	1	1001	1000	0	0	73	1	16	1	1	2630	1000	3038	3038	3038	3038	3038
1004	3037	23	61	2548	25	1000	1000	1000	398313	1	3018	3037	3037	2415	3	2895	1000	1000	3000	3037	3037	1	1	1001	1000	0	3	73	1	16	1	1	2630	1000	3038	3038	3038	3038	3038
1004	3037	23	61	2548	25	1000	1000	1000	398313	1	3018	3037	3037	2415	3	2895	1000	1000	3000	3037	3037	1	1	1001	1000	0	0	73	1	16	1	1	2630	1000	3038	3038	3038	3038	3038
1004	3037	23	61	2548	25	1000	1000	1000	398313	1	3018	3037	3037	2415	3	2895	1000	1000	3000	3037	3037	1	1	1001	1000	0	0	73	1	16	1	1	2630	1000	3038	3038	3038	3038	3038
1004	3037	23	61	2548	25	1000	1000	1000	398313	1	3018	3037	3037	2415	3	2895	1000	1000	3000	3037	3037	1	1	1001	1000	0	0	73	1	16	1	1	2630	1000	3038	3038	3038	3038	3038
1004	3037	23	61	2548	25	1000	1000	1000	398313	1	3018	3037	3037	2415	3	2895	1000	1000	3000	3037	3037	1	1	1001	1000	0	33	73	1	16	1	1	2630	1000	3038	3038	3038	3038	3038
1004	3037	23	61	2548	25	1000	1000	1000	398313	1	3018	3037	3037	2415	3	2895	1000	1000	3000	3037	3037	1	1	1001	1000	1	0	73	1	16	1	1	2630	1000	3038	3038	3038	3038	3038
1004	3037	22	61	2548	25	1000	1000	1000	398313	1	3018	3037	3037	2415	3	2895	1000	1000	3000	3037	3037	1	1	1001	1000	0	0	73	1	16	1	1	2630	1000	3038	3038	3038	3038	3038

Test 2: Latency 1->1

Code:

  mla v0.16b, v1.16b, v2.16b

Initialization

  movi v0.16b, 1
  movi v1.16b, 2
  movi v2.16b, 3

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	18	19	1e	1f	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	61	69	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb miss (a1)	l1d cache writeback (a8)	ac	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d0	d2	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10204	30037	225	0	0	0	0	61	29548	25	10100	100	10000	100	10000	500	4277313	1	3	30018	0	30037	30037	28272	6	28741	10100	200	10008	200	30024	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	2763	1	1	1	720	3	3	0	16	0	0	29646	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	0	0	61	29548	25	10100	100	10000	100	10000	500	4277313	1	3	30018	0	30037	30037	28272	7	28740	10100	200	10008	200	30024	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	3	1	1	1	717	3	3	0	16	0	0	29646	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	0	0	61	29548	25	10100	100	10000	100	10000	500	4277313	1	3	30018	0	30037	30037	28272	6	28741	10100	200	10008	200	30024	30037	30037	1	1	10201	100	99	100	100	10000	100	2	0	0	1	1	1	717	3	3	0	16	0	0	29646	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	0	0	61	29548	25	10100	100	10000	100	10000	500	4277313	1	3	30018	0	30037	30037	28272	7	28740	10100	200	10008	200	30024	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	1	1	1	718	3	3	0	16	0	1	29646	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	0	0	61	29548	25	10100	100	10000	100	10000	500	4277313	1	3	30018	0	30037	30037	28272	6	28740	10100	200	10008	200	30024	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	710	4	3	2	16	2	2	29634	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	0	0	61	29548	25	10100	100	10000	100	10000	500	4277313	1	3	30018	0	30037	30037	28265	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	712	4	3	2	16	2	2	29634	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	0	0	285	29548	25	10100	100	10000	100	10000	500	4277313	1	3	30018	0	30037	30037	28265	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	710	4	3	2	16	2	2	29634	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	0	0	61	29548	25	10100	100	10000	100	10000	500	4277313	1	3	30018	0	30037	30037	28265	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	710	4	3	2	16	2	2	29634	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	6	0	61	29548	25	10100	100	10000	100	10000	500	4277313	1	3	30018	0	30037	30037	28265	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	710	4	3	2	16	2	2	29634	0	10000	100	30038	30038	30038	30038	30038
10204	30037	224	0	0	0	0	61	29548	25	10100	100	10000	100	10000	500	4277313	1	3	30018	0	30037	30037	28265	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	710	4	3	2	16	2	2	29634	0	10000	100	30038	30038	30038	30038	30038

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	09	l2 tlb miss data (0b)	18	1e	3f	4e	50	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10024	30037	225	0	0	0	0	726	29548	0	25	10010	10	10000	10	10000	50	4277313	1	30018	30037	30037	28287	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	640	2	16	2	2	29630	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	0	0	156	29548	30021	25	10010	10	10000	10	10000	50	4277313	1	30018	30037	30037	28287	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	640	2	16	2	2	29630	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	0	0	736	29548	0	25	10010	10	10000	10	10000	50	4277313	1	30018	30037	30037	28287	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	640	2	16	2	2	29630	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	0	0	61	29548	0	25	10010	10	10000	10	10000	50	4277313	1	30018	30037	30037	28287	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	640	2	16	2	2	29630	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	0	0	61	29548	0	25	10010	10	10000	10	10000	50	4277313	1	30018	30037	30037	28287	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	640	2	16	2	2	29630	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	0	0	61	29548	0	25	10010	10	10000	10	10000	50	4277313	1	30018	30037	30037	28287	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	640	2	16	2	2	29630	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	0	0	61	29548	0	25	10010	10	10000	10	10000	50	4277313	1	30018	30037	30037	28287	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	640	2	16	2	2	29630	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	0	0	61	29548	0	25	10010	10	10000	10	10000	50	4277313	1	30018	30037	30037	28287	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	640	2	16	2	2	29630	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	0	0	61	29548	0	25	10010	10	10000	10	10000	50	4277313	1	30018	30037	30037	28287	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	640	2	16	2	2	29630	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	0	0	61	29548	0	25	10010	10	10000	10	10000	50	4277313	1	30018	30037	30037	28287	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	1	0	640	2	16	2	2	29630	10000	10	30038	30038	30038	30038	30038

Test 3: Latency 1->2

Code:

  mla v0.16b, v0.16b, v1.16b

Initialization

  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk instruction (07)	mmu table walk data (08)	1e	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d cache writeback (a8)	ac	branch cond mispred nonspec (c5)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10204	30037	225	0	0	0	61	29548	25	10100	100	10000	100	10000	500	4277313	0	30018	30037	30037	28265	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	710	3	16	1	1	29634	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	0	61	29548	25	10100	100	10000	100	10000	500	4277313	0	30018	30037	30037	28265	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	710	1	16	1	1	29634	10000	100	30038	30038	30038	30038	30038
10204	30037	224	0	0	0	61	29548	25	10100	100	10000	100	10000	500	4277313	1	30018	30084	30037	28265	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	710	1	16	1	1	29634	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	0	61	29548	25	10100	100	10000	100	10000	500	4277313	0	30065	30037	30037	28265	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	710	2	16	1	1	29634	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	0	61	29548	25	10100	100	10000	100	10000	500	4277313	0	30018	30037	30037	28265	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	3	0	710	1	16	1	1	29634	10000	100	30038	30038	30038	30038	30038
10204	30037	224	0	0	0	61	29548	25	10100	100	10000	100	10000	500	4277313	0	30018	30037	30037	28265	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	710	1	16	1	1	29634	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	0	61	29548	25	10100	100	10000	100	10000	500	4277313	0	30018	30037	30037	28265	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	12	0	710	1	16	1	1	29634	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	0	61	29548	25	10100	100	10000	100	10000	500	4277313	0	30018	30037	30037	28265	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	710	1	16	1	1	29634	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	0	61	29548	25	10100	100	10000	100	10000	500	4277313	0	30018	30037	30037	28265	3	28745	10100	200	10000	200	30495	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	710	1	16	1	1	29634	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	0	61	29548	25	10100	100	10000	100	10000	500	4277313	0	30018	30037	30037	28265	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	710	1	16	1	1	29634	10000	100	30038	30038	30038	30038	30038

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	18	1e	1f	3a	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	branch mispred nonspec (cb)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10024	30037	225	0	9	0	0	61	29548	25	10010	10	10000	10	10000	50	4277313	1	30018	30037	30037	28287	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	640	3	16	3	3	29630	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	0	0	61	29548	25	10010	10	10000	10	10000	50	4277313	1	30018	30037	30037	28287	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	640	3	16	3	3	29630	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	0	0	61	29548	25	10010	10	10000	10	10000	50	4277313	1	30018	30037	30037	28287	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	640	3	16	3	3	29630	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	0	0	82	29548	25	10010	10	10000	10	10000	50	4277313	1	30018	30037	30037	28287	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	640	3	16	3	3	29630	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	0	0	61	29548	25	10010	10	10000	10	10000	50	4277313	1	30018	30037	30037	28287	3	28767	10010	20	10000	20	30000	30037	30213	2	1	10021	10	9	10	10	10000	10	0	0	0	0	0	640	3	16	3	3	29630	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	0	0	61	29548	25	10010	10	10000	10	10000	50	4277313	1	30018	30037	30037	28287	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	640	3	16	3	3	29630	10000	10	30038	30038	30038	30038	30038
10024	30037	224	0	0	0	0	61	29548	25	10010	10	10000	10	10000	50	4277313	0	30018	30037	30037	28287	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	4	0	0	0	640	3	16	3	3	29630	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	0	0	61	29548	25	10010	10	10000	10	10000	50	4277313	1	30018	30037	30037	28287	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	640	3	16	3	3	29630	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	0	0	61	29548	25	10010	10	10000	10	10000	50	4277313	0	30018	30037	30037	28287	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	640	3	16	3	3	29630	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	0	0	61	29548	25	10010	10	10000	10	10000	50	4277313	1	30018	30037	30037	28287	3	28767	10010	20	10000	20	31935	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	640	3	16	3	3	29630	10000	10	30038	30038	30038	30038	30038

Test 4: Latency 1->3

Code:

  mla v0.16b, v1.16b, v0.16b

Initialization

  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	1f	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10204	30037	225	0	0	61	29548	25	10100	100	10000	100	10000	500	4277313	0	30018	30037	30037	28265	3	28745	10100	200	10000	200	30000	30037	30179	1	1	10201	100	99	100	100	10000	100	0	0	0	710	1	16	2	1	29634	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	61	29548	25	10100	100	10000	100	10000	500	4277313	0	30018	30037	30037	28265	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	710	1	16	1	1	29708	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	61	29548	25	10100	100	10000	100	10000	500	4277313	0	30018	30037	30037	28265	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	710	1	16	1	1	29634	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	943	29548	25	10100	100	10000	100	10000	500	4277313	1	30018	30037	30037	28265	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	710	1	16	1	1	29634	10000	100	30038	30038	30038	30038	30038
10204	30037	225	15	0	156	29548	25	10100	100	10000	100	10000	500	4277313	0	30018	30037	30037	28265	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	710	1	16	1	1	29634	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	61	29548	25	10100	100	10000	100	10000	500	4277313	0	30018	30037	30037	28265	3	28745	10100	200	10000	200	30987	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	710	1	16	1	1	29634	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	61	29548	25	10100	100	10000	100	10000	500	4277313	0	30018	30037	30037	28265	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	710	1	16	1	1	29634	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	61	29548	25	10100	100	10000	100	10000	500	4277313	0	30018	30037	30037	28265	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	710	1	16	1	1	29634	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	61	29548	25	10100	100	10000	100	10000	500	4277313	0	30018	30037	30037	28265	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	710	1	16	1	1	29634	10000	100	30038	30038	30038	30038	30038
10204	30037	224	0	0	61	29548	25	10100	100	10000	100	10000	500	4277313	0	30018	30037	30037	28265	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	710	1	16	1	1	29634	10000	100	30038	30038	30038	30038	30038

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	18	1e	1f	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10024	30037	225	0	60	0	61	29548	25	10010	10	10000	10	10000	50	4277313	1	30018	0	30037	30037	28287	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	640	2	16	2	2	29630	10000	10	30038	30038	30038	30038	30038
10024	30037	224	0	21	0	82	29548	25	10010	10	10000	10	10000	50	4277313	1	30018	0	30037	30037	28287	3	28767	10159	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	640	2	16	2	2	29630	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	27	0	218	29548	25	10010	10	10000	10	10000	50	4277313	0	30018	0	30037	30037	28287	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	640	2	16	2	2	29630	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	411	0	61	29548	25	10010	10	10000	10	10000	50	4277313	1	30018	0	30037	30037	28287	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	640	2	16	2	2	29630	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	24	0	66	29548	25	10010	10	10000	10	10000	50	4277313	0	30018	0	30037	30037	28287	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	640	2	16	2	2	29630	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	21	0	61	29548	25	10010	10	10000	10	10000	50	4277313	0	30018	0	30037	30037	28287	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	640	2	16	2	2	29630	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	15	0	61	29548	25	10010	10	10000	10	10000	50	4277313	0	30018	0	30037	30037	28287	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	640	2	16	2	2	29630	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	33	0	61	29548	25	10010	10	10000	10	10000	50	4277313	0	30018	0	30037	30037	28287	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	640	2	16	2	2	29630	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	270	0	61	29548	25	10010	10	10000	10	10000	50	4277313	0	30018	0	30037	30037	28287	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	3	640	2	16	2	2	29630	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	27	0	61	29548	25	10010	10	10000	10	10000	50	4277313	0	30018	0	30037	30037	28287	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	640	2	16	2	2	29630	10000	10	30038	30038	30038	30038	30038

Test 5: throughput

Count: 8

Code:

  movi v0.16b, 0
  mla v0.16b, v8.16b, v9.16b
  movi v1.16b, 0
  mla v1.16b, v8.16b, v9.16b
  movi v2.16b, 0
  mla v2.16b, v8.16b, v9.16b
  movi v3.16b, 0
  mla v3.16b, v8.16b, v9.16b
  movi v4.16b, 0
  mla v4.16b, v8.16b, v9.16b
  movi v5.16b, 0
  mla v5.16b, v8.16b, v9.16b
  movi v6.16b, 0
  mla v6.16b, v8.16b, v9.16b
  movi v7.16b, 0
  mla v7.16b, v8.16b, v9.16b

Initialization

  movi v8.16b, 9
  movi v9.16b, 10

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2508

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	18	19	1e	1f	3a	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	69	6d	6e	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d cache writeback (a8)	ac	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160204	20065	150	0	0	0	0	0	39	25	80100	100	80000	100	80000	500	640000	20045	20064	20064	3	22	80100	200	80000	200	240000	20064	20064	1	1	160201	100	99	100	100	160000	100	0	0	0	10112	2	16	2	2	20061	160000	100	20065	20065	20065	20065	20065
160204	20064	150	0	0	0	0	0	636	25	80100	100	80000	100	80000	500	640000	20045	20064	20064	3	22	80100	200	80000	200	240000	20064	20064	1	1	160201	100	99	100	100	160000	100	0	0	0	10112	2	16	2	2	20061	160000	100	20065	20065	20065	20065	20065
160204	20064	151	0	0	0	0	0	39	25	80100	100	80000	100	80000	500	640000	20045	20064	20064	3	22	80100	200	80000	200	240000	20064	20064	1	1	160201	100	99	100	100	160000	100	0	0	0	10112	2	16	2	2	20061	160000	100	20065	20065	20065	20065	20065
160204	20064	151	0	0	9	0	0	39	25	80100	100	80000	100	80000	500	640000	20045	20064	20064	3	22	80100	200	80000	200	240000	20064	20064	1	1	160201	100	99	100	100	160000	100	0	0	0	10112	2	16	2	2	20061	160000	100	20065	20065	20065	20065	20065
160204	20064	150	0	0	0	0	0	39	25	80100	100	80000	100	80000	500	640000	20045	20064	20064	3	22	80100	200	80000	200	240000	20064	20064	1	1	160201	100	99	100	100	160000	100	0	0	0	10112	2	16	2	2	20061	160000	100	20065	20065	20065	20065	20065
160204	20064	150	0	0	6	0	0	39	25	80100	100	80000	100	80000	500	640000	20045	20064	20064	3	22	80100	200	80000	200	240000	20064	20064	1	1	160201	100	99	100	100	160000	100	0	0	0	10112	2	16	2	2	20061	160000	100	20065	20065	20065	20065	20065
160204	20064	150	0	0	21	0	0	39	25	80100	100	80000	100	80000	500	640000	20045	20064	20064	3	22	80100	200	80000	200	240000	20064	20064	1	1	160201	100	99	100	100	160000	100	0	0	0	10112	2	16	2	2	20061	160000	100	20065	20065	20065	20065	20065
160204	20064	150	0	0	0	0	0	704	25	80100	100	80000	100	80000	500	640000	20045	20064	20064	3	22	80100	200	80000	200	240000	20064	20064	1	1	160201	100	99	100	100	160000	100	0	0	0	10112	2	16	2	2	20061	160000	100	20065	20065	20065	20065	20065
160204	20064	150	0	0	0	0	0	39	25	80100	100	80000	100	80000	500	640000	20045	20064	20064	3	22	80100	200	80000	200	240000	20064	20064	1	1	160201	100	99	100	100	160000	100	0	0	0	10112	2	16	2	2	20061	160000	100	20065	20065	20065	20065	20065
160204	20064	150	0	0	6	0	0	39	25	80100	100	80000	100	80000	500	640000	20045	20064	20064	3	22	80100	200	80000	200	240000	20064	20064	1	1	160201	100	99	100	100	160000	100	0	0	0	10112	2	16	2	2	20061	160000	100	20065	20065	20065	20065	20065

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2506

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	19	1e	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	5f	60	69	6d	6e	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d cache writeback (a8)	ac	cf	d0	d2	l1i cache miss demand (d3)	d5	map dispatch bubble (d6)	d9	da	db	dd	fetch restart (de)	e0	? int output thing (e9)	ea	ec	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160024	20080	150	0	0	51	27	80012	12	80000	12	80000	62	640000	3	1	20032	20051	20051	3	22	80012	20	80000	20	240000	20051	20051	1	1	160021	10	9	10	10	160000	10	0	0	10030	3	1	1	6	25	2	1	1	7	7	20048	2	20	1	160000	10	20061	20052	20052	20061	20052
160024	20051	151	0	0	1233	27	80012	12	80000	12	80000	62	640000	1	1	20032	20051	20051	3	22	80012	20	80000	20	240000	20051	20051	1	1	160021	10	9	10	10	160000	10	0	0	10027	6	2	2	4	34	4	1	1	4	4	20057	2	20	2	160000	10	20052	20052	20052	20052	20052
160024	20051	150	0	0	45	27	80012	12	80000	12	80000	62	640000	1	1	20032	20051	20051	3	22	80012	20	80000	20	240000	20051	20051	1	1	160021	10	9	10	10	160000	10	0	0	10029	3	1	1	6	25	2	1	1	4	4	20048	2	20	1	160000	10	20052	20052	20052	20052	20052
160024	20060	150	0	0	45	27	80012	12	80000	12	80000	62	640000	1	1	20032	20051	20051	3	22	80012	20	80000	20	240000	20051	20051	1	1	160021	10	9	10	10	160000	10	0	0	10029	3	1	1	7	25	2	1	1	3	4	20048	2	20	1	160000	10	20052	20052	20052	20052	20052
160024	20051	151	0	0	45	27	80012	12	80000	12	80000	62	640000	2	1	20032	20051	20051	3	22	80012	20	80000	20	240000	20051	20051	1	1	160021	10	9	10	10	160000	10	0	0	10030	3	1	1	6	25	2	1	1	3	4	20048	2	20	2	160000	10	20052	20052	20052	20052	20052
160024	20051	150	0	0	45	27	80012	12	80000	12	80000	62	640000	1	1	20032	20051	20051	3	22	80012	20	80000	20	240000	20051	20051	1	1	160021	10	9	10	10	160000	10	0	0	10027	3	1	1	6	25	2	1	1	3	4	20048	2	20	1	160000	10	20052	20052	20052	20052	20052
160024	20051	150	1	162	45	27	80012	12	80000	12	80000	62	640000	2	1	20032	20051	20051	10	43	80012	20	80000	20	240000	20051	20051	1	1	160021	10	9	10	10	160000	10	0	0	10029	3	1	1	4	25	2	1	1	4	4	20048	2	20	1	160000	10	20061	20052	20052	20052	20052
160024	20051	150	0	0	45	27	80012	12	80000	12	80000	62	640000	1	1	20032	20051	20051	3	22	80012	20	80000	20	240000	20051	20051	1	1	160021	10	9	10	10	160000	10	0	0	10029	3	1	1	6	25	2	1	1	3	4	20048	2	20	1	160000	10	20052	20052	20052	20052	20052
160024	20051	150	0	0	45	27	80012	12	80000	12	80000	62	640000	1	1	20032	20051	20051	26	22	80012	20	80000	20	240000	20051	20051	1	1	160021	10	9	10	10	160000	10	0	0	10026	3	1	1	3	25	2	1	1	3	4	20048	2	20	1	160000	10	20052	20052	20052	20052	20052
160024	20051	150	0	0	45	29	80012	12	80000	12	80000	62	640000	1	1	20032	20051	20051	3	22	80012	20	80000	20	240000	20051	20051	1	1	160021	10	9	10	10	160000	10	0	0	10027	3	1	1	4	25	2	1	1	6	8	20048	2	40	1	160000	10	20052	20052	20052	20052	20052

Test 6: throughput

Count: 16

Code:

  mla v0.16b, v16.16b, v17.16b
  mla v1.16b, v16.16b, v17.16b
  mla v2.16b, v16.16b, v17.16b
  mla v3.16b, v16.16b, v17.16b
  mla v4.16b, v16.16b, v17.16b
  mla v5.16b, v16.16b, v17.16b
  mla v6.16b, v16.16b, v17.16b
  mla v7.16b, v16.16b, v17.16b
  mla v8.16b, v16.16b, v17.16b
  mla v9.16b, v16.16b, v17.16b
  mla v10.16b, v16.16b, v17.16b
  mla v11.16b, v16.16b, v17.16b
  mla v12.16b, v16.16b, v17.16b
  mla v13.16b, v16.16b, v17.16b
  mla v14.16b, v16.16b, v17.16b
  mla v15.16b, v16.16b, v17.16b

Initialization

  movi v16.16b, 17
  movi v17.16b, 18

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2502

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	09	19	1e	37	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160204	40060	302	0	0	0	1	42	0	25	160100	100	160017	100	160000	500	2399055	0	40030	40039	40048	19973	3	19997	160100	200	160000	200	480000	40039	40040	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	10110	1	16	1	1	40036	0	160000	100	40049	40040	40050	40040	40040
160204	40048	300	0	0	39	0	51	0	25	160101	100	160000	100	160000	500	2398999	0	40020	40039	40039	19973	3	20029	160100	200	160000	200	480000	40039	40040	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	10110	1	16	1	1	40046	0	160000	100	40050	40040	40040	40040	40040
160204	40048	300	0	0	0	0	169	0	25	160100	100	160000	100	160000	500	1319998	0	40020	40039	40049	19973	3	19997	160100	200	160000	200	480000	40049	40039	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	10110	1	16	1	2	40036	0	160000	100	40041	40040	40040	40040	40050
160204	40039	300	0	0	0	0	42	0	25	160100	100	160001	100	160000	500	1319998	1	40020	40039	40040	19973	3	19997	160100	200	160000	200	480000	40040	40039	1	1	160201	100	99	100	100	160000	100	0	0	0	0	15	10110	1	16	1	2	40068	0	160000	100	40040	40050	40040	40072	40040
160204	40048	300	0	0	0	0	136	0	25	160100	100	160000	100	160000	500	1280000	0	40020	40049	40039	19973	3	19997	160100	200	160000	200	480000	40039	40039	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	10110	1	16	1	1	40036	0	160000	100	40040	40041	40050	40041	40163
160204	40039	300	0	0	420	17	41	0	25	160101	100	160017	100	160000	500	1319999	0	40021	40048	40039	19973	3	20006	160100	200	160000	200	480000	40039	40048	1	1	160201	100	99	100	100	160000	100	0	0	0	0	3	10110	1	16	1	1	40036	0	160000	100	40040	40041	40050	40040	40040
160204	40049	302	0	0	0	17	41	0	25	160117	100	160017	100	160000	500	2398999	0	40020	40049	40048	19973	3	20007	160100	200	160000	200	480000	40039	40048	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	10110	1	16	1	1	40036	0	160000	100	40072	40040	40072	40040	40072
160204	40039	300	0	0	0	1	41	0	105	160117	100	160018	100	160000	500	1280000	0	40029	40071	40039	19973	3	19997	160100	200	160000	200	480000	40039	40049	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	10110	1	16	1	1	40036	0	160000	100	40049	40040	40050	40040	40041
160204	40049	300	0	0	0	0	64	25	25	160100	100	160017	100	160000	500	1280000	0	40020	40039	40039	19973	3	19997	160100	200	160548	200	480000	40040	40049	1	1	160201	100	99	100	100	160000	100	0	2	3	0	0	10177	1	16	2	2	40036	0	160000	100	40040	40255	40041	40040	40040
160204	40040	300	0	0	0	0	42	0	25	160100	100	160416	100	160000	500	2398999	0	40020	40039	40039	19973	3	20007	160100	200	160000	200	480000	40048	40039	1	1	160201	100	99	100	100	160000	100	0	0	1	0	0	10110	1	16	2	2	40036	0	160000	100	40040	40050	40040	40040	40049

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2502

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	l2 tlb miss data (0b)	18	19	1e	1f	37	3a	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	5f	60	61	69	6d	6e	map stall dispatch (70)	simd prf full (72)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	cd	cf	d0	d2	l1i cache miss demand (d3)	d5	map dispatch bubble (d6)	d9	da	db	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160024	40049	299	0	0	0	0	0	0	17	0	55	0	25	160027	10	160000	12	160000	50	2398999	1	1	0	40029	40039	40039	19996	0	3	20019	160010	20	160107	20	480000	40048	40039	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	603	0	10022	3	1	1	10	16	2	1	1	12	8	40036	0	20	9	160000	10	40049	40040	40050	40040	40040
160024	40039	299	0	0	0	0	0	0	0	0	52	0	25	160027	10	160000	12	160000	50	1280000	1	0	5	40029	40039	40039	19996	0	3	20019	160010	20	160000	20	480000	40039	40039	2	1	160021	10	9	10	10	160000	10	0	0	0	0	0	24	0	10022	8	2	1	7	16	2	1	1	12	11	40045	0	20	6	160000	10	40040	40041	40041	40049	40040
160024	40071	300	0	0	0	0	0	0	17	0	46	0	25	160010	10	160000	12	160000	50	2398999	0	1	5	40020	40039	40048	19996	0	3	20028	160010	20	160000	20	480000	40039	40039	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	18	0	10024	3	5	2	12	16	4	2	2	11	12	40037	0	40	6	160000	10	40050	40049	40040	40041	40040
160024	40049	300	0	0	0	0	0	0	18	0	47	0	25	160010	10	160000	12	160000	50	1280000	0	1	0	40020	40049	40039	19996	0	3	20028	160010	20	160000	20	480000	40039	40039	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	18	0	10022	8	1	1	7	60	2	1	1	7	10	40036	0	20	6	160000	10	40040	40040	40040	40049	40049
160024	40039	299	0	0	0	0	0	0	242	0	1750	18	196	161020	11	161096	10	161472	55	1744658	1	0	0	40521	40728	40509	20027	2	46	20276	161150	20	161233	20	483444	40353	40558	11	1	160021	10	9	10	10	160000	10	7	0	0	1	0	4571	0	10193	8	1	1	13	141	2	1	1	15	20	40310	4	20	9	160000	10	40574	40654	40643	40635	40622
160024	40623	304	1	1	10	10	1452	440	40	1	1964	55	178	161221	11	161262	14	161115	55	1811202	1	0	5	40537	40729	40598	20157	0	44	20323	161274	20	161297	20	483849	40613	40520	11	1	160021	10	9	10	10	160000	10	2	2	2	1	0	5496	0	10221	3	4	1	10	132	2	1	1	11	14	40590	0	20	9	160000	10	40040	40049	40040	40049	40040
160024	40039	300	0	0	0	0	0	0	0	0	47	0	25	160010	10	160000	12	160000	50	1280000	1	1	5	40020	40039	40040	19996	0	3	20029	160010	20	160000	20	480000	40039	40039	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	42	0	10022	8	4	1	14	16	2	1	1	9	12	40045	0	20	9	160000	10	40040	40040	40040	40040	40049
160024	40040	299	0	0	0	0	0	0	17	0	46	0	25	160010	10	160000	12	160000	50	1280000	1	1	5	40020	40039	40048	19996	0	3	20019	160010	20	160000	20	480000	40039	40039	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	0	0	10022	8	4	1	12	16	2	1	1	12	9	40036	0	20	9	160000	10	40040	40040	40040	40040	40049
160024	40039	300	0	0	0	0	0	0	17	0	47	0	25	160027	10	160017	12	160000	50	2398999	1	1	5	40020	40039	40048	19996	0	3	20019	160010	20	160000	20	480000	40039	40039	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	0	0	10022	8	5	2	9	16	2	1	1	9	12	40036	0	20	6	160000	10	40040	40040	40040	40040	40040
160024	40049	299	0	0	0	0	0	0	17	0	55	0	25	160011	10	160018	12	160000	50	2399082	1	1	5	40020	40048	40048	19996	0	3	20019	160010	20	160000	20	480000	40039	40048	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	0	0	10022	8	4	1	9	16	2	1	1	12	10	40045	0	20	6	160000	10	40050	40049	40040	40049	40049

MLA (vector, 16B)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->1

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: Latency 1->2

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 4: Latency 1->3

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 5: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 6: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations