Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

MLA (vector, 8B)

Test 1: uops

Code:

  mla v0.8b, v1.8b, v2.8b
  movi v0.16b, 1
  movi v1.16b, 2
  movi v2.16b, 3

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

retire uop (01)cycle (02)031e3f4e51schedule uop (52)schedule simd uop (54)dispatch simd uop (57)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map simd uop (7e)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst simd alu (9a)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)f5f6f7f8fd
100430372306125482510001000100039831313018303730372415328951000100030003037303711100110000073116112630100030383038303830383038
100430372206125482510001000100039831313018303730372415328951000100030003037303711100110000073116112630100030383038303830383038
100430372206125482510001000100039831313018303730372415328951000116330003037307311100110000073116112630100030383038303830383038
100430372206125482510001000100039831313018303730372415328951000100030003037303711100110001073116112630100030383038303830383038
100430372306125482510001000100039831313018303730372415328951000100030003037303711100110000073116112630100030383038303830383038
1004303723061254825100010001000398313130183037303724153289510001000300030373037111001100001273116112630100030383038303830383038
100430372206125482510001000100039831313018303730372415328951000100030003037303711100110000073116112630100030383038303830383038
100430372306125482510001000100039831313018303730372415328951000100030003037303711100110000073116112630100030383038303830383038
100430372306125482510001000100039831313018303730372415328951000100030003037303711100110000073116112630100030383038303830383038
100430372306125482510001000100039831313018303730372415328951000100030003037303711100110000073116112630100030383038303830383038

Test 2: Latency 1->1

Code:

  mla v0.8b, v1.8b, v2.8b
  movi v0.16b, 1
  movi v1.16b, 2
  movi v2.16b, 3

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)0318191e3a3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)acc2cfd0d5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
10204300372250000612954825101001001000010010000500427731330018300373003728265328745101002001000020030000300373003711102011009910010010000100000710021622296340100001003003830038300383003830179
102043003722500011032954825101331001000010010149500427731330090300373003728265328745101002001000020030000300373003711102011009910010010000100160710021622296340100001003003830038300383003830038
1020430037225001201032954825101001001000010010000500427731330018300373003728265328745101002001000020030000300373003711102011009910010010000100000710021622296340100001003003830038300383003830038
10204300372250000612954825101001001000010010000500427731330018300373003728265328745101002001000020030000300373003711102011009910010010000100000710021622296340100001003003830038300383003830038
10204300372250000612954825101001001000010010000500427731330018300373003728265328745101002001000020030000300373003711102011009910010010000100000710021622296340100001003003830038300383003830038
10204300372250000612954825101001001000010010000500427731330018300373003728265328745101002001000020030000300373003711102011009910010010000100000710021622296340100001003003830038300383003830038
10204300372250000612954825101001001000010010000500427731330018300373003728265328745101002001000020030000300373003711102011009910010010000100000710021622296340100001003003830038300383003830038
102043003722400006129548251010010010000100100005004277313300183003730037282653287451010020010000200300003003730037111020110099100100100001001700712121622296340100001003003830038300383003830038
10204300372250000612954825101001001000010010000500427731330018300373003728265328745101002001000020030000300373003711102011009910010010000100000710121622296340100001003003830038300383003830038
10204300372250000612954825101001001000010010000500427731330018300373003728265328745101002001000020030000300373003711102011009910010010000100000710121622296340100001003003830038300383003830038

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)03mmu table walk data (08)l2 tlb miss data (0b)18191e1f3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d tlb miss (a1)ld unit uop (a6)l1d cache writeback (a8)a9acc2cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
100243003722500000061295482510010101000010100005042773131300183003730037282873287671001020100002030000300373003711100211091010100001000000006402162229630010000103003830038300383003830038
1002430037225000000536295482510010101000010100005042773131300183003730037282873287671001020100002030000300373003711100211091010100001000010006402162229630010000103003830038300383003830038
10024300372250000459132726295482510010101000010100005042773130300183003730037282873287671001020100002030000300373003711100211091010100001000000006402162229630010000103003830038300383003830038
1002430037225000000536295482510010101000010100005042773131300183003730037282873287671001020100002030000300373003711100211091010100001000000006402162229630010000103003830038300383003830038
1002430037224000000726295482510010101000010100005042773131300183003730037282873287671001020100002030000300373003711100211091010100001000000006402162229630010000103003830038300383003830038
100243003722500000061295482510010101000010100005042773131300183003730037282873287671001020100002030000300373003711100211091010100001000000006402162229630010000103003830038300383003830038
100243003722500000061295482510010101000010100005042773131300183003730037282873287671001020100002030000300373003711100211091010100001000000006402162229630010000103003830038300383003830038
100243003722500000061295482510010101000010100005042773131300183003730037282873287671001020100002030000300373003711100211091010100001000000006402162229630010000103003830038300383003830038
1002430037225000000612954825100101010000101000050427731313001830037300372828732876710010201000020300003003730037111002110910101000010000001806402162229630010000103003830038300383003830038
100243003722500000061295302510010101000010100006142773131300183003730037282873287671001020100002030000300373003711100211091010100001000000006402162229630010000103003830038300383003830038

Test 3: Latency 1->2

Code:

  mla v0.8b, v0.8b, v1.8b
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)031e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696b6d6emap stall dispatch (70)simd prf full (72)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
10204300372250612954825101001001000010010000500427731313001803003730037282650328745101002001000020030000300373003711102011009910010010000100007101161129634100001003003830038300383003830038
102043003722561562954825101001001000010010000500427731313001803003730037282650328745101002001000020030000300373003711102011009910010010000100007101161129634100001003003830038300383003830038
10204300372250612954825101001001000010010000500427731313001803003730037282650328745101002001000020030000300373003711102011009910010010000100007101161129634100001003008630038300383003830038
10204300372250612954825101001001000010010000500427731313001803003730037282650328745101002001000020030000300373003711102011009910010010000100007101161129634100001003003830038300383003830038
10204300372250612954825101001001000010010000500427731313001803003730037282650328745101002001000020030000300373003711102011009910010010000100007101161129634100001003003830038300383003830038
10204300372250612954825101001001000010010000500427731313001803003730037282650328745101002001000020030000300373003711102011009910010010000100007101161129634100001003003830038300383003830038
10204300372250612954825101001001000010010000500427731313001803003730037282650328745101002001000020030000300373003711102011009910010010000100007101161129634100001003003830038300383003830038
10204300372250822954825101001001000010010000500427731313001803003730037282650328745101002001000020030000300373008411102011009910010010000100007101161129634100001003003830038300383003830038
10204300372250612954825101001001000010010000500427731313001803003730037282650328745101002001000020030000300373003711102011009910010010000100107101161129634100001003003830038300383003830038
10204300372250612954825101001001000010010000500427731313001803003730037282650328745101002001000020030000300373003711102011009910010010000100007101161129634100001003003830038300383003830038

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)03mmu table walk data (08)191e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fld unit uop (a6)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
100243003722500061295482510010101000010100005042773131300183003730037282873287671001020100002030000300373003711100211091010100001001506405163329630010000103003830038300383003830038
10024300372250006129548251001012100001010000504277313030018300373003728287328767100102010000203000030037300371110021109101010000100106403163329630010000103003830038300383003830038
1002430037225000612954825100121210000121000060427731313001830037300372828732876710010201000020300003003730037111002110910101000010049486403163329630010000103003830038300383003830038
10024300372250006129548251001010100001010000504277313030018300373003728287328767100102010000203000030037300371110021109101010000100329916405163329630010000103018030085300383003830038
1002430037225000182629548251001210100001010000504277313130018300373003728287328767100102010000203000030037300371110021109101010000100606403163329630010000103003830038300383003830038
10024300372240006129548251001012100001210000504277313130018300373003728287328767100102010000203000030037300371110021109101010000100206403163329630010000103003830038300383003830038
10024300372250006129548251001010100001010000504277313030018300373003728287328767100102010000203000030037300371110021109101010000100406403163329630010000103003830038300383003830038
10024300372240006129548251001212100001210000504277313130018300373003728287328767100102010000203000030037300371110021109101010000100106683163329630010000103003830038300383003830038
10024300372250006129548251001210100001010000504277313130018300373003728287328767100102010000203000030037300371110021109101010000102106403163329630010000103003830084300383003830038
10024300372250006129548251001212100001210000504277313130018300373003728287328767100122010000203000030037300371110021109101010000100306403163329630010000103003830038300383003830038

Test 4: Latency 1->3

Code:

  mla v0.8b, v1.8b, v0.8b
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)03mmu table walk data (08)09l2 tlb miss data (0b)18191e1f3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb miss (a1)l1d cache writeback (a8)a9accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
1020430037225000001209612954864101001211000010010000500427731303001830037300372826532874510100200100002003000030037300371110201100991001001000010000007101161129634100001003003830038300383003830038
1020430037224000001207862954825101001001000010010000500427731303001830037300372826532874510100200100002003000030037300371110201100991001001000010004037101161129634100001003003830230300383003830038
102043003722400000002122954825101001001000010010000500427731313001830037300372826532874510100200100002003000030037300371110201100991001001000010000007101161129634100001003003830038300383003830038
102043003722500000006662954825101001001000010010000500427731303001830037300372826532874510100200100002003000030037300371110201100991001001000010000007101161129634100001003003830038300383003830038
102043003722500000001662954825101001001000010010000500427731303001830037300372826532874510100200100002003000030037300371110201100991001001000010020007101321129634100001003003830038300383003830086
102043003722500000001452954825101001001000010010000500427731303001830037300372826532874510100200100002003000030037300374110201100991001001000010000107101161129634100001003003830038300383003830038
102043003722500000002162954825101001001000010010000500427731303001830227300372826532874510100200100002003000030037300371110201100991001001000010000007101251129634100001003003830038300383003830038
102043003722500000001492954825101001001000010010000500427731303001830037300372827132874510100200100002003000030037300371110201100991001001000010000007101161129634100001003003830038300383003830038
102043003722500100001662954825101001001000010010000500427731303001830037300372826532874510100200100002003000030037300371110201100991001001000010000007101161129634100001003003830038300383003830038
102043003722500000302142954825101001001000010010149500427731303001830037300372826532874510100200100002003000030037300371110201100991001001000010000007101161129634100001003003830038300863003830038

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)03mmu table walk data (08)181e1f3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)a9accfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
1002430037224000019129548251001212100001210000504277313130018300373003728287328767100102010000203000030037300371110021109101010000100006402162229630010000103003830038300383003830131
1002430037225000083529548251001212100001010000504277313130018300373003728287328767100102010000203000030037300371110021109101010000100006402162229630010000103003830038300383003830038
1002430037225000014729548251001010100001010000504277313130018300373003728287328767100102010000203000030037300371110021109101010000100006402326229630010000103003830038300383003830038
1002430037225000012629548251001010100001010000504277313130018300373003728287328767100102010000203000030037300371110021109101010000100006402162229630010000103003830038300383003830038
1002430037225000022429548251001010100001010000504277313130018300373003728287328767100102010000203000030037300371110021109101010000100006402162229630010000103003830038300383003830038
1002430037225000016629548251001010100001010000504277313130018300373003728287328767100102010000203000030037300371110021109101010000100006402162229630010000103003830038300383003830038
1002430037225000016829548251001010100001010000504277313130018300373003728287328767100102010000203000030037300371110021109101010000100006402162229630010000103003830038300383003830038
1002430037225000016829548251001010100001010000504277313130018300373003728287328767100102010000203000030037300371110021109101010000100006402162229630010000103003830038300383003830038
100243003722500008429548251001010100001010000504277313130018300373003728287328767100102010000203000030037300371110021109101010000100006402162229630010000103003830038300383003830038
100243003722500008229548251001010100001010000504277313130018300373003728287328767100102010000203000030037300371110021109101010000100006402162229632010000103003830038300383003830038

Test 5: throughput

Count: 8

Code:

  movi v0.16b, 0
  mla v0.8b, v8.8b, v9.8b
  movi v1.16b, 0
  mla v1.8b, v8.8b, v9.8b
  movi v2.16b, 0
  mla v2.8b, v8.8b, v9.8b
  movi v3.16b, 0
  mla v3.8b, v8.8b, v9.8b
  movi v4.16b, 0
  mla v4.8b, v8.8b, v9.8b
  movi v5.16b, 0
  mla v5.8b, v8.8b, v9.8b
  movi v6.16b, 0
  mla v6.8b, v8.8b, v9.8b
  movi v7.16b, 0
  mla v7.8b, v8.8b, v9.8b
  movi v8.16b, 9
  movi v9.16b, 10

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2508

retire uop (01)cycle (02)03l2 tlb miss data (0b)1e3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)696d6emap rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fld unit uop (a6)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
1602042008915000125258010010080000100800005006400002004520064200643228010020080000200240000200642006411160201100991001001600001000001011151611200611600001002006520065200652006520065
1602042006415100995258010010080000100800005006400002004520064200643228010020080000200240000200642006411160201100991001001600001000001011111611200611600001002006520065200652006520065
160204200641500081258010010080000100800005006400002004520064200643228010020080000200240000200642006411160201100991001001600001000001011111611200611600001002006520065200652006520065
160204200641500039258010010080000100800005006400002004520064200643228010020080000200240000200642006411160201100991001001600001000101011111611200611600001002006520065200652006520065
1602042006415000127258010010080000100800005006400002004520064200643228010020080000200240000200642006411160201100991001001600001000001011111611200611600001002006520065200652006520065
160204200641500081258010010080000100800005006400002004520064200643228010020080000200240000200642006411160201100991001001600001000001011111611200611600001002006520065200652006520065
1602042006415000190258010010080000100800005006400002004520064200643228010020080000200240000200642006411160201100991001001600001000061011111611200611600001002006520065200652006520065
160204200641500039258010010080000100800005006400002004520064200643228010020080000200240000200642006411160201100991001001600001000001011111611200611600001002006520065200652006520065
1602042006415000102258010010080000100800005006400002004520064200643228010020080000200240000200642006411160201100991001001600001000101011111611200611600001002006520065200652006520065
16020420064150003699258010010080000100800005006400002004520064200643228010020080000200240000200642006411160201100991001001600001000001011111611200611600001002006520065200652006520065

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2506

retire uop (01)cycle (02)03l1i tlb fill (04)mmu table walk instruction (07)l2 tlb miss instruction (0a)l2 tlb miss data (0b)191e1f3a3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)5f6061696b6d6emap rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fld unit uop (a6)l1d cache writeback (a8)acc2cfd0d2l1i cache miss demand (d3)l1i tlb miss demand (d4)d5map dispatch bubble (d6)d9dadbddfetch restart (de)e0? int output thing (e9)ea? simd retires (ee)? int retires (ef)f5f6f7f8fd
16002420056150100000022772580012128000012800006264000000020033020052200523228001220800002024000020052200521116002110910101600001000001005362213526322282920244231160000102005320053200532005320053
1600242005215010100001632580012128000012800006264000000020033020052200523228001220800002024000020052200521116002110910101600001001001004562211826322291920194231160000102005320053200532005320053
16002420052150111000009325800121280000128000062640000000200330200522005232280012208000020240000200522005211160021109101016000010000010057113203026322192920182231160000102005320053200532005320053
16002420052150122000007525800121280000128000062640000000200330200522005232280012208000020240000200522005211160021109101016000010000010058164212826322193120202231160000102005320053200532005320053
16002420052150133000017525800121280000128000062640000011020033020052200523228001220800002024000020052200521116002110910101600001000001005862213126322313020175231160000102005320053200532005320053
1600242005215012200000752580012128000012800006264000000020033020052200523228014820800002024000020052200521116002110910101600001000001005862213126322243120189231160000102005320053200532005320053
160024200521501330000063258001212800001280000626400000110200330200522005232280012208000020240000200522005211160021109101016000010000010056164213126322232820220231160000102005320053200532005320053
1600242005215013300001692580012128000012800006264000001020033020052200523228001220800002024000020052200521116002110910101600001020301005862213126322303020191231160000102005320053200532005320053
16002420052150143000017525800121280000128000062640000011020033020052200523228001220800002024000020052200521116002110910101600001005001005862213026322253020172231160000102005320053200532005320053
16002420052150132000017525800121280000128000062640000001020033020052200523228001220800002024000020052200521116002110910101600001000001005864213026322163020188231160000102004720047200472004720047

Test 6: throughput

Count: 16

Code:

  mla v0.8b, v16.8b, v17.8b
  mla v1.8b, v16.8b, v17.8b
  mla v2.8b, v16.8b, v17.8b
  mla v3.8b, v16.8b, v17.8b
  mla v4.8b, v16.8b, v17.8b
  mla v5.8b, v16.8b, v17.8b
  mla v6.8b, v16.8b, v17.8b
  mla v7.8b, v16.8b, v17.8b
  mla v8.8b, v16.8b, v17.8b
  mla v9.8b, v16.8b, v17.8b
  mla v10.8b, v16.8b, v17.8b
  mla v11.8b, v16.8b, v17.8b
  mla v12.8b, v16.8b, v17.8b
  mla v13.8b, v16.8b, v17.8b
  mla v14.8b, v16.8b, v17.8b
  mla v15.8b, v16.8b, v17.8b
  movi v16.16b, 17
  movi v17.16b, 18

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2502

retire uop (01)cycle (02)03mmu table walk data (08)1e1f373f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)5f696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d tlb miss (a1)ld unit uop (a6)l1d cache writeback (a8)a9acc2cdcfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
1602044008330000017500251601171001600171001600005001280000040020400394004819973319997160100200160000200480000400484003911160201100991001001600001000000000010110216224003601600001004004040050400404004940049
1602044004830000017420251601001001600001001600005001280000040020400394003919973319997160100200160000200480000400394004811160201100991001001600001000000000010110216224003601600001004004040049400404004940040
16020440048300015017710251601171001600171001600005002398999040020400394003919973319997160100200160000200480000400394004811160201100991001001600001000000000010110216224004501600001004004040040400404004940040
1602044004830000017410251601001001600001001600005001280000040029400394004819973320006160100200160000200480000400394004011160201100991001001600001000000000010110216244004501600001004004940049400494004940040
160204400393000000500251601011001600171001600005001280000040020400394004819973319997160100200160000200480000400484003911160201100991001001600001000000000010110216224003601600001004004940040400494004040049
160204400483000000410251601001001600171001600005001280000040029400484004819973320006160100200160000200480000400394004811160201100991001001600001000000000010110216224003601600001004004040041400404004940040
1602044003929900881500251601171001600001001600005001319998040020400394003919973320032160100200160000200480000400394004811160201100991001001600001000000000010110216224004501600001004004940049400494004940040
1602044003930000017410251601011001600001001600005002398999040029400394004819993319997160100200160000200480000401074003911160201100991001001600001000200000010110216224004501600001004004940040400494005040049
160204400392990000410251601001001600001001600005002399027040029400484003919973319997160100200160000200480000400394004811160201100991001001600001000000000010110216224008801600001004004940040400404004040040
1602044009730000017500251601001001600001001600005001280000040029400394003919973320006160100200160000200480000400394004811160201100991001001600001000000000010110216224003601600001004004140040400404005040050

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2502

retire uop (01)cycle (02)03mmu table walk data (08)191e373f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)5f60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb miss (a1)l1d cache writeback (a8)a9acc2branch mispred nonspec (cb)cfd0d2l1i cache miss demand (d3)d5map dispatch bubble (d6)d9dadbddfetch restart (de)e0eaeb? simd retires (ee)? int retires (ef)f5f6f7f8fd
1600244008630000005212516002710160000101600005012800001140020400394003919989320012160010201600002048000040039400391116002110910101600001000000010022311816233410840036155160000104004940049400404004040040
160024400393000000462516001010160017101600005012800001140020400394003919989320012160010201600002048000040040400391116002110910101600001000000010022311716433210940036155160000104004140040400404004940040
160024400393000000462516001010160000101600005012800000140020400394003919989320012160010201600002048000040039400391116002110910101600001000000010022311916231210940036156160000104004040049400404004040040
160024400393000000462516001010160000101600005012800001140020400394003919989320012160010201600002048000040039400391116002110910101600001000000010022311101623728940036155160000104004040040400404004040040
1600244004930000007425160010101600001016000050128000011400204003940039199893200121600102016000020480000400484003911160021109101016000010000000100223111016230281040045155160000104004040049400404004040040
16002440039300009021825160010101600001016000050128000011400204003940039199893200121600102016000020480000400394004811160021109101016000010000000100223111016232291140036155160000104004040040400404004040040
16002440039300000067251600101016000010160000502398999114002040039400391998932001216001020160000204800004003940039111600211091010160000100000001002231110172322101040036155160000104004040040400404004040040
160024400483000000462516002710160000101600005023990821140020400394003919989320012160010201600002048000040039400391116002110910101600001000000010022311111623729640036155160000104004040040400404004040040
1600244004830000009282516002710160000101600005012800001140020400394003919989320012160010201600002048000040039400391116002110910101600001000000010022311616241210740036155160000104004040040400404004040040
1600244003930000003322516001010160001101600005012800001140020400394003919989320012160010201600002048000040039400391116002110910101600001000000010022311101623329940036155160000104004040040400404004040040