Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

MLS (vector, 4H)

Test 1: uops

Code:

  mls v0.4h, v1.4h, v2.4h
  movi v0.16b, 1
  movi v1.16b, 2
  movi v2.16b, 3

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

retire uop (01)cycle (02)03191e1f3a3f4e51schedule uop (52)schedule simd uop (54)dispatch simd uop (57)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map simd uop (7e)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst simd alu (9a)l1d tlb miss (a1)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)f5f6f7f8fd
1004303722000161254825100010001000398313130183037303724153289510001000300030373037111001100000075516552630100030383038303830383038
1004303723000161254825100010001000398313130183037303724153289510001000300030373037111001100000375616552630100030383038303830383038
1004303722000161254825100010001000398313130183037303724153289510001000300030373037111001100001075516662630100030383038303830383038
1004303723000161254825100010001000398313030183037303724153289510001000300030373037111001100000075716552630100030383038303830383038
1004303722000161254825100010001000398313030183037303724153289510001000300030373037111001100000075616772630100030383038303830383038
1004303723030161254825100010001000398313030183037303724153289510001000300030373037111001100000075516562630100030383038303830383038
1004303722000161254825100010001000398313030183037303724153289510001000300030373037111001100000075616552630100030383038303830383038
1004303722000161254825100010001000398313030183037303724153289510001000300030373037111001100000375516552630100030383038303830383038
1004303723000161254825100010001000398313030183037303724153289510001000300030373037111001100000077516552630100030383038303830383038
1004303723000161254825100010001000398313030183037303724153289510001000300030373037111001100000075716652630100030383038303830383038

Test 2: Latency 1->1

Code:

  mls v0.4h, v1.4h, v2.4h
  movi v0.16b, 1
  movi v1.16b, 2
  movi v2.16b, 3

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)031e3a3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696b6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)acbranch cond mispred nonspec (c5)cfd0d5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
10204300372258106129548251010010010000100100005004277313030018030037300372826532876410100200100002003000030037300371110201100991001001000010000071012162229634100001003003830038300383003830038
1020430037225016129548251010010010000100100005004277313030018030037300372826532874510100200100002003000030037300371110201100991001001000010000071012162229634100001003003830038300383003830038
1020430037224006129548251010010010000100100005004277313030018330037300372826532874510100200100002003000030037300371110201100991001001000010000071012162229634100001003003830038300383008630038
102043003722538706129548251010010010000100100005004277313130018030037300372826532874510100200100002003000030037300371110201100991001001000010000071013162229634100001003003830038300383003830038
1020430037225006129548251010010010000100100005004277313130018030037300372826532874510100200100002003000030037300371110201100991001001000010000071013162229634100001003003830038300383003830038
1020430037225016129548251010010010000100100005004277313130018030037300372826532874510100200100002003000030037300371110201100991001001000010000071012162229634100001003003830038300383003830038
1020430037225306129548251010010010000100100005004277313130018030037300372826532874510100200100002003000030037300371110201100991001001000010000071012162229634100001003003830038300383003830038
10204300372250012829548251010010010000100100005004277313030018030037300372826532874510100200100002003000030037300371110201100991001001000010000071012162229634100001003003830038300383003830038
10204300372252706129548251010010010000100100005004277313030018030037300372826532874510100200100002003000030037300371110201100991001001000010000071012162329634100001003003830038300383003830038
1020430037225006129548251010010010000100100005004277313030018030037300372826532874510100200100002003000030037300371110201100991001001000010000071212162229634100001003003830038300383003830038

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)031e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)a9accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
100243003722527612954825100101010000101000050427731303001830037300372828732876710010201000020300003003730037111002110910101000010000640216222963010000103003830038300383003830038
10024300372250612954825100101010000101000050427731303001830037300372828732876710010201000020300003003730037111002110910101000010000640216222963010000103003830038300383003830038
1002430037225392802954825100101010000101000050427731303001830037300372828732876710010201000020300003003730037111002110910101000010000640216222963010000103003830038300383003830038
100243003722524612954825100101010000101000050427731303001830037300372828732876710010201000020300003003730037111002110910101000010000640216222963010000103003830038300383003830038
100243003722527612954825100101010000101000050427731303001830037300372828732876710010201000020300003003730037111002110910101000010000640216222963010000103003830038300383003830038
10024300372250612954825100101010000101000050427731303001830037300372828732876710010201000020300003003730037111002110910101000010000640216222963010000103003830038300383003830038
10024300372250612954825100101010000101000050427731303001830037300372828732876710010201000020300003003730037111002110910101000010000640216222963010000103003830038300383003830038
10024300372253612954825100101010000101000050427731303001830037300372828732876710010201000020300003003730037111002110910101000010000640216222963010000103003830038300383003830038
10024300372250612954825100101010000101000050427731303001830037300372828732876710010201000020300003003730037111002110910101000010000640216222963010000103003830038300383003830038
100243003722515612954825100101010000101000050427731303001830037300372828732876710010201000020300003003730037111002110910101000010000640216222963010000103003830038300383003830038

Test 3: Latency 1->2

Code:

  mls v0.4h, v0.4h, v1.4h
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)03mmu table walk data (08)l2 tlb miss data (0b)181e3a3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fld unit uop (a6)l1d cache writeback (a8)a9acc2branch cond mispred nonspec (c5)branch mispred nonspec (cb)cfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
1020430037225000120612954825101001001000010010000500427731313001830037300372826532874510100200100002003000030037300371110201100991001001000010000000007101161129634100001003003830038300383003830038
102043003722500000612954825101001001000010010000500427731313001830037300372829132874510100200100002003000030037300371110201100991001001000010000000007101161129634100001003003830038300383003830038
102043003722500000612954825101001001000010010000500427731313001830037300372826532874510100200100002003000030037300371110201100991001001000010000000007101161129634100001003003830038300383003830038
102043003722500000612954825101001001000010010000500427731313001830037300372826532874510100200100002003000030037300371110201100991001001000010000000007101161129634100001003003830038300383003830038
102043003722500000612954825101001001000010010000500427731313001830037300372826532874510100200100002003000030037300371110201100991001001000010000000107101161129634100001003003830038300383003830038
102043003722500000612954825101001001000010010000500427731313001830037300372826532874510100200100002003000030037300371110201100991001001000010000000007101161129634100001003003830038300383003830038
102043003722400000612954825101001001000010010000500427731303001830037300372826532874510100200100002003000030037300371110201100991001001000010000000007101161129634100001003003830038300383003830038
102043003722500000612954825101001001000010010000500427731313001830037300372826532874510100200100002003000030037300372110201100991001001000010001000007101161129634100001003003830038300383003830038
102043003722500000612954825101001001000010010000500427731303001830037300372826532874510100200100002003000030037300371110201100991001001000010000000007101161129634100001003003830038300383003830038
102043003722500000612954825101001001000010010000500427731313001830037300372826532874510100200100002003000030037300371110201100991001001000010000030007101161129634100001003003830038300383003830038

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)03l2 tlb miss data (0b)18191e1f3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb miss (a1)l1d cache writeback (a8)acc2cfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
1002430037225000420612954825100101010000101000050427731330018300373003728287328767100102010000203000030037300371110021109101010000100000640216222963010000103003830038300383003830038
100243003722500000612954825100101010000101000050427731330018300373003728287328767100102010000203000030037300371110021109101010000100000640216222963010000103003830038300383003830038
100243003722400000612954825100101010000101000050427731330018300373003728287328767100102010000203000030037300371110021109101010000100000683216222963010000103003830038300383003830038
100243003722400000612954825100101010000101000050427731330018300373003728287328767100102010000203000030037300371110021109101010000100132703234322963010000103003830038300383003830038
100243003722500000612954825100101010000101000050427731330018300373003728287328767100102010000203000030037300371110021109101010000100000640216222963010000103003830038300383003830038
100243003722500000612954825100101010000101000050427731330018300373003728287328767100102010000203000030037300371110021109101010000100000640216222963010000103003830038300383003830038
100243003722500000612954825100101010000101000050427731330018300373003728287328767100102010000203000030037300371110021109101010000100000640216222963010000103003830038300383003830038
100243003722500000612954825100101010000101000050427731330018300373003728287328767100102010000203000030037300371110021109101010000100000640216222963010000103003830038300383003830038
100243003722510000612954825100101010000101000050427731330018300373003728287328767100102010000203000030037300371110021109101010000100000640216222963010000103003830038300383003830038
100243003722500000612954825100101010000101000050427731330018300373003728287328767100102010000203000030037300371110021109101010000100000640216222963010000103003830038300383003830038

Test 4: Latency 1->3

Code:

  mls v0.4h, v1.4h, v0.4h
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)03mmu table walk data (08)0918191e1f3a3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d tlb miss (a1)ld unit uop (a6)st unit uop (a7)l1d cache writeback (a8)a9acc2cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
1020430037225000000061295482510100100100001001000050042773130300183003730037282653287451010020010000200300003003730037111020110099100100100001000000000071011611296340100001003003830038300383003830038
1020430037224000000061295482510100100100001001000050042773130300183003730037282653287451010020010000200300003003730037111020110099100100100001000000000071011611296340100001003003830038300383003830038
1020430037225000000061295482510100100100001001000050042773130300183003730037282653287451010020010000200300003003730037111020110099100100100001000000000071011611296340100001003003830038300383003830038
1020430037225000000061295482510100100100001001000050042773130300183003730037282653287451010020010000200300003003730037111020110099100100100001000000000071011611296340100001003003830038300383003830038
1020430037225000000061295482510100100100001001000050042773130300183003730037282653287451010020010000200300003003730037111020110099100100100001000000003071011611296340100001003003830038300383003830038
10204300372250000000631295482510100100100001001000050042773130300183003730037282653287451010020010000200300003003730037111020110099100100100001000000000071011611296340100001003003830082300383003830038
10204300372250000000251295482510100100100001001000050042773130300183003730037282653287451010020010000200300003003730037111020110099100100100001000000000071011611296340100001003003830038300383003830038
10204300372250000000256295482510100100100001001000050042773130300183003730037282653287451010020010000200300003003730037111020110099100100100001000000000071011611296340100001003003830038300383003830038
10204300372250000000726295482510100100100001001000050042773131300183003730037282653287451010020010000200300003003730037111020110099100100100001000000000071011611296340100001003003830038300383003830038
1020430037224000000061295482510100100100001001000050042773130300183003730037282653287451010020010000200300003003730037111020110099100100100001000000000071011611296340100001003003830038300383003830038

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)03l1i tlb fill (04)mmu table walk data (08)1e1f3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)simd prf full (72)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)acbranch cond mispred nonspec (c5)branch mispred nonspec (cb)cdcfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
10024300372250000612954825100101010000101000050427731313001830037300372828703287671001020100002030000300373003711100211091010100001000000640416342963010000103003830038300383003830038
10024300372250000612954825100101010000101000050427731313001830037300372828703287671001020100002030000300373003711100211091010100001000000640416432963010000103003830038300383003830038
10024300372250000612954825100101010000101000050427731313001830037300372828703287671001020100002030000300373003711100211091010100001000000640416342963010000103003830038300383003830038
10024300372250100612954825100101010000101000050427731313001830037300372828703287671001020100002030000300373003711100211091010100001000010640416442963010000103003830038300383003830038
10024300372250000612954825100101010000101000050427731313001830037300372828703287671001020100002030000300373003711100211091010100001000000640416442963010000103003830038300383003830038
10024300372250000612954825100101010000101000050427731313001830037300372828703287671001020100002030000300373003711100211091010100001000001640416442963010000103003830038300383003830038
10024300372250000612954825100101010000101000050427731313001830037300372828703287671001020100002030000300373003711100211091010100001000000640316442963010000103003830038300383003830038
10024300372250000612954825100101010000101000050427731313001830037300372828703287671001020100002030000300373003711100211091010100001000000640416432963010000103003830038300383003830038
1002430037225000010872954825100101010000101000050427731313001830037300372828703287671001020100002030000300373003711100211091010100001000000640316442963010000103003830038300383003830038
10024300372250000612954825100101010000101000050427731313001830037300372828703287671001020100002030000300373003711100211091010100001000000640316342963010000103003830038300383003830038

Test 5: throughput

Count: 8

Code:

  movi v0.16b, 0
  mls v0.4h, v8.4h, v9.4h
  movi v1.16b, 0
  mls v1.4h, v8.4h, v9.4h
  movi v2.16b, 0
  mls v2.4h, v8.4h, v9.4h
  movi v3.16b, 0
  mls v3.4h, v8.4h, v9.4h
  movi v4.16b, 0
  mls v4.4h, v8.4h, v9.4h
  movi v5.16b, 0
  mls v5.4h, v8.4h, v9.4h
  movi v6.16b, 0
  mls v6.4h, v8.4h, v9.4h
  movi v7.16b, 0
  mls v7.4h, v8.4h, v9.4h
  movi v8.16b, 9
  movi v9.16b, 10

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2508

retire uop (01)cycle (02)03091e3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9faccdcfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
160204200911510060258010010080000100800005006400001200452006420064322801002008000020024000020064200641116020210099100100160000100001011111611200611600001002006520065200652006520065
160204200641500939258010010080000100800005006400001200452006420064322801002008000020024000020064200641116020110099100100160000100001011111611200611600001002006520065200652006520065
160204200641500039258010010080000100800005006400001200452006420064322801002008000020024000020064200641116020110099100100160000100001011111611200611600001002006520065200652006520065
160204200641500039258010010080000100800005006400001200452006420064322801002008000020024000020064200641116020110099100100160000100001011111611200611600001002006520065200652006520065
160204200641500039258010010080000100800005006400001200452006420064322801002008000020024000020064200641116020110099100100160000100001011111611200611600001002006520065200652006520065
160204200641500039258010010080000100800005006400001200452006420064322801002008000020024000020064200641116020110099100100160000100001011111611200611600001002006520065200652006520065
160204200641500039258010010080000100800005006400001200452006420064322801002008000020024000020064200641116020110099100100160000100001011111611200611600001002006520065200652006520065
160204200641510039258010010080000100800005006400001200452006420064322801002008000020024000020064200641116020110099100100160000100001011111611200611600001002006520065200652006520065
160204200641500039258010010080000100800005006400001200452006420064322801002008000020024000020064200641116020110099100100160000100001011111611200611600001002006520065200652006520065
160204200641510039258010010080000100800005006400001200452006420064322801002008000020024000020064200641116020110099100100160000100001011111611200611600001002006520065200652006520065

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2508

retire uop (01)cycle (02)03l1i tlb fill (04)mmu table walk instruction (07)l2 tlb miss instruction (0a)1e3a3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)5f6061696d6erob full (74)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fld unit uop (a6)st unit uop (a7)l1d cache writeback (a8)acc2cfd0d2l1i cache miss demand (d3)d5map dispatch bubble (d6)d9dadbddfetch restart (de)e0? int output thing (e9)eaec? simd retires (ee)? int retires (ef)f5f6f7f8fd
16002420089150110005672980012128000012800006264000001102004320062200620322800122080000202400002006220062111600211091010160000100000010056165229363222827200592412160000102006320063200632006320063
1600242006215103001512980012128000012800006264000001102004320062200620322800122080000202400002006220062111600211091010160000100000010052166227363221928200592412160000102006320063200632006320063
16002420062151011121512980012128000012800006264000001102004320062200620322800122080000202400002006220062111600211091010160000100000010054166228363222727200592412160000102006320063200632006320156
160024200621500010163298001212800001280000626400000102004320062200620322800122080000202400002006220062111600211091010160000100000010054166226363222627200592412160000102006320063200632006320063
16002420062151011016329800121280000128000062640000010200432006220062032280012208000020240000200622006211160021109101016000010000001004962222363222918200592412160000102006320063200632006320063
1600242006215101100512980012128000012800006264000001102004320062200620322800122080000202400002006220062111600211091010160000100000010054167227363222327200592412160000102006320063200632006320063
1600242006215001100632980012128000012800006264000001102004320062200620322800122080000202400002006220062111600211091010160000100000010053167227363221625200592412160000102006320063200632006320063
1600242006215001000621298001212800001280000626400000110200432006220062032280012208000020240396200622006211160021109101016000010000001005267225363221726200592412160000102006320063200632006320063
1600242006215001100632980012128000012800006264000001102004320062200620322800122080000202400002006220062111600211091010160000100000010054167227363222228200592412160000102006320063200632006320063
160024200621500110163298001212800001280000626400000110200452006220062032280012208000020240000200622006211160021109101016000010000001005167227363222227200592412160000102006320063200632006320063

Test 6: throughput

Count: 16

Code:

  mls v0.4h, v16.4h, v17.4h
  mls v1.4h, v16.4h, v17.4h
  mls v2.4h, v16.4h, v17.4h
  mls v3.4h, v16.4h, v17.4h
  mls v4.4h, v16.4h, v17.4h
  mls v5.4h, v16.4h, v17.4h
  mls v6.4h, v16.4h, v17.4h
  mls v7.4h, v16.4h, v17.4h
  mls v8.4h, v16.4h, v17.4h
  mls v9.4h, v16.4h, v17.4h
  mls v10.4h, v16.4h, v17.4h
  mls v11.4h, v16.4h, v17.4h
  mls v12.4h, v16.4h, v17.4h
  mls v13.4h, v16.4h, v17.4h
  mls v14.4h, v16.4h, v17.4h
  mls v15.4h, v16.4h, v17.4h
  movi v16.16b, 17
  movi v17.16b, 18

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2503

retire uop (01)cycle (02)03l1i tlb fill (04)l2 tlb miss data (0b)18191e373f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)acc2branch mispred nonspec (cb)cdcfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
1602044007130000000174125160100100160001100160000500128000014002940039400481997332000616010020016000020048000040039400391116020110099100100160000100000001011011611400361600001004004940040400494004040040
16020440039299000001751725160100100160017100160000500251912904002940039400481997331999716010020016000020048000040039400481116020110099100100160000100000001011011611400451600001004004940049400414004040049
160204400493000000005025160100100160017100160000500131999814002040039400391997331999716010020016000020048000040039400481116020110099100100160000100000001011011611400371600001004004140040400494004140041
1602044003930000000174125160117100160000100160000500131999814002940049400481997332000616010020016000020048000040048400391116020110099100100160000100000001011011611400371600001004004040049400404004040040
160204400493000000005025160100100160000100160000500239899914002040040400491997331999716010020016000020048000040040400391116020110099100100160000100000101011011611400451600001004004040041400404004940049
160204400482990000008325160117100160017100160000500128000014002940039400401997331999716010020016000020048000040039400401116020110099100100160000100000001011011611400461600001004004040041400404004940040
1602044004829900000174125160100100160000100160000500239899914002040039400481997331999716010020016000020048000040039400391116020110099100100160000100000001011011611400451600001004004940050400504004940040
160204400393000000004225160100100160017100160000500239899914003040039400391997331999716010020016000020048000040039400481116020110099100100160000100000001011011611400451600001004004040049400404004940049
16020440048300000091770625160117100160001100160000500239905514002140048400391997332000616010020016000020048000040049400391116020110099100100160000100000001011011611400371600001004004040049400404005040040
160204400393000000005353160100100160000100160000500128000014002040039400391997332000616010020016000020048000040040400481116020110099100100160000100000001011011611400371600001004004140040400404004040049

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2502

retire uop (01)cycle (02)03mmu table walk instruction (07)mmu table walk data (08)l2 tlb miss instruction (0a)l2 tlb miss data (0b)18191e1f373f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)5f60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d tlb miss (a1)ld unit uop (a6)l1d cache writeback (a8)a9acc2cfd0d2l1i cache miss demand (d3)d5map dispatch bubble (d6)d9dadbddfetch restart (de)e0? int output thing (e9)eaeb? simd retires (ee)? int retires (ef)f5f6f7f8fd
16002440055299000000001746251600271016000010160000501280000114002040039400491999632001916001020160000204800004003940039111600211091010160000100000000100223112916211106400360155160000104004040040400404004040040
16002440039299100000000462516002710160018101600005023989990140020400494003919996320020160010201600002048000040039400391116002110910101600001000000001002462211164227114003603010160000104004040040400404004040049
1600244003930000000000195225160010101600001016000050128000001400304003940039199963200191600102016010720480792400394010111160021109101016000010022125323210196622613042215134044033011160000104053840582404174060940530
16002440601304310196132379280170021316122314161023141612996617384590140485405754054420106402020816119020161217204832914069740583101160021109101016000010200025228010224322171244221594052923011160000104060440388406224062940652
1600244070630401014111329880017844160010101600181016000050128000001400204004840048199963200191600102016000020480000400394023911160021109101016000010000103010024622816422884003603010160000104004040049400404004040040
16002440039299000000210052251600101016001710160000501280000014002940039400391999632001916001020160000204800004003940040111600211091010160000100002000100246221416422764003603010160000104004040040400404004040040
160024400393000010000004625160010101600001016000050243886501400294004940039199963200191600102016000020480000400394003911160021109101016000010000200010024322616412674003603012160000104004940049400404004040040
160024401112990000000005225160028101600001016000050128000001400204003940039199963200191600102016000020480000400394004911160021109101016000010000000010024322716422684003601510160000104005040040400404004040049
160024400393000000000006125160027101600001016000050128000001400304004940039199963200191600102016000020480000400394003911160021109101016000010000000010024621916421764004603012160000104005040040400404005040040
160024400392990000000018822516002710160017101600005012800000140020400394004919996320019160010201600002048000040039400391116002110910101600001000000001002432214162221394003701510160000104004040040400404004040050