Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

MOVI (vector, 2S)

Test 1: uops

Code:

  movi v0.2s, #3

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

retire uop (01)cycle (02)031e3f51schedule uop (52)schedule simd uop (54)dispatch simd uop (57)ldst uops in schedulers (5b)696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map simd uop (7e)8283flush restart other nonspec (84)85inst all (8c)inst simd alu (9a)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)f5f6f7f8fd
100428830402510001000100070002692882881233146100010002882881110011000973116112851000289289289289289
100428820402510001000100070002692882881233146100010002882881110011000073116112851000289289289289289
100428820402510001000100070002692882881233146100010002882881110011000073116112851000289289289289289
100428820402510001000100070002692882881233146100010002882881110011000073116112851000289289289289289
100428820402510001000100070002692882881233146100010002882881110011000373116112851000289289289289289
100428820402510001000100070002692882881233146100010002882881110011000073116112851000289289289289289
100428820402510001000100070002692882881233146100010002882881110011000073116112851000289289289289289
100428820402510001000100070002692882881233146100010002882881110011000073116112851000289289289289289
100428820402510001000100070002692882881233146100010002882881110011000073116112851000289289289289289
100428820402510001000100070002692882881233146100010002882881110011000073116112851000289289289289289

Test 2: throughput

Count: 8

Code:

  movi v0.2s, #3
  movi v1.2s, #3
  movi v2.2s, #3
  movi v3.2s, #3
  movi v4.2s, #3
  movi v5.2s, #3
  movi v6.2s, #3
  movi v7.2s, #3

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)031e3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d tlb miss (a1)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
802042003815012402580100100800001008000050056000002001920038200389973399968010020080000200200382003811802011009910010080000100000051102162220035800001002003920039200392003920039
802042003815012402580100100800001008000050056000002001920038200389973399968010020080000200200382003811802011009910010080000100000051102162220035800001002003920039200392003920039
8020420038150040258010010080000100800005005600000200192003820038997339996801002008000020020038200381180201100991001008000010000020151102162220035800001002003920039200392003920039
80204200381500612580100100800001008000050056000002001920038200389973399968010020080000200200382003811802011009910010080000100000051102162220035800001002003920039200392003920039
80204200381500402580100100800001008000050056000002001920038200389973399968010020080000200200382003811802011009910010080000100001051102162220035800001002003920039200392003920039
80204200381500402580100100800001008000050056000002001920038200389973399968010020080000200200382003811802011009910010080000100000051102162220035800001002003920039200392003920039
80204200381500402580100100800001008000050056000012001920038200389973399968010020080000200200382003811802011009910010080000100000051102162220035800001002003920039200392003920039
80204200381500402580100100800001008000050056000002001920038200389982399968010020080000200200382003811802011009910010080000100000051102162220035800001002003920039200392003920039
80204200381500402580100100800001008000050056000012001920038200389973399968010020080000200200382003811802011009910010080000100000051102162220035800001002003920039200392003920039
80204200381550402580100100800001008000050056000012001920038200389973399968010020080000200200382003811802011009910010080000100000051102162220035800001002003920039200392003920039

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)031e3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)accfd0d5map dispatch bubble (d6)dadbddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
800242004015501272580010108000010800005056000012001920038200389996310018800102080000202003820038118002110910108000010005020051600752003580000102003920039200392003920039
80024200381550622580010108000010800005056000012001920038200389996310018800102080000202003820038118002110910108000010005020051600572003580000102003920039200392003920039
80024200381550812580010108000010800005056000002001920038200389996310018800102080000202003820038118002110910108000010005020071600752003580000102003920039200392003920039
800242003815501252580010108000010800005056000002001920038200389996310018800102080000202003820038118002110910108000010005020071600572003580000102003920039200392003920039
800242003815501272580010108000010800005056000002001920038200389996310018800102080000202003820038118002110910108000010005020051600752003580000102003920039200392003920039
800242003815501232580010108000010800005056000002001920038200389996310018800102080000202003820038118002110910108000010005020071600572003580000102003920039200392003920039
80024200381550392580010108000010800005056000002001920038200389996310018800102080000202003820038118002110910108000010005020071600752003580000102003920039200392003920039
80024200381560392580010108000010800005056000002001920038200389996310018800102080000202003820038118002110910108000010005020051600752003580000102003920039200392003920039
800242003815503522580010108000010800005056000002001920038200389996310018800102080000202003820038118002110910108000010005020051600572003580000102003920039200392003920039
800242003815602072580010108000010800005056000002001920038200389996310018800102080000202003820038118002110910108000010005020051600752003580000102003920039200392003920039