Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

MOVI (vector, 2S, msl)

Test 1: uops

Code:

  movi v0.2s, #3, msl #8

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

retire uop (01)cycle (02)031e3a3f51schedule uop (52)schedule simd uop (54)dispatch simd uop (57)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map simd uop (7e)8283flush restart other nonspec (84)85inst all (8c)inst simd alu (9a)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)f5f6f7f8fd
100428820140251000100010007000126928828812331461000100028828811100110000073616342851000289289289289289
100428820040251000100010007000126928828812331461000100028828811100110000073316332851000289289289289289
100428820040251000100010007000126928828812331461000100028828811100110000073316332851000289289289289289
100428820040251000100010007000126928828812331461000100028828811100110000073316332851000289289289289289
100428820040251000100010007000126928828812331461000100028828811100110003073316442851000289289289289289
100428820040251000100010007000126928828812331461000100028828811100110000073316332851000289289289289289
100428820040251000100010007000126928828812331461000100028828811100110000073316332851000289289289289289
100428820040251000100010007000126928828812331461000100028828811100110000073316332851000289289289289289
100428830040251000100010007000126928828812331461000100028828811100110000073316332851000289289289289289
100428820040251000100010007000126928828812331461000100028828811100110000073316332851000289289289289289

Test 2: throughput

Count: 8

Code:

  movi v0.2s, #3, msl #8
  movi v1.2s, #3, msl #8
  movi v2.2s, #3, msl #8
  movi v3.2s, #3, msl #8
  movi v4.2s, #3, msl #8
  movi v5.2s, #3, msl #8
  movi v6.2s, #3, msl #8
  movi v7.2s, #3, msl #8

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)03mmu table walk data (08)l2 tlb miss instruction (0a)l2 tlb miss data (0b)18191e1f3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d tlb miss (a1)ld unit uop (a6)l1d cache writeback (a8)a9acc2cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
802042005815500000004025801001008000010080000500560000020019200382003899733999680100200800002002003820038118020110099100100800001000000000511031633200350800001002003920039200392003920039
802042003815600000004025801001008000010080000500560000020019200382003899733999680100200800002002003820038118020110099100100800001000001000511031633200350800001002003920039200392003920039
802042003815500000004025801001008000010080000500560000020019200382003899733999680100200800002002003820038118020110099100100800001000000000511031633200350800001002003920039200392003920039
802042003815500000004025801001008000010080000500560000020019200382003899733999680100200800002002003820038118020110099100100800001000000000511031633200350800001002003920039200392003920039
802042003815500000004025801001008000010080000500560000020019200382003899733999680100200800002002003820038118020110099100100800001000000000511031633200350800001002003920039200392003920039
802042003815500000004025801001008000010080000500560000020019200382003899733999680100200800002002003820038118020110099100100800001000000000511031633200350800001002003920039200392003920039
802042003815500000004025801001008000010080000500560000020019200382003899733999680100200800002002003820038118020110099100100800001000000030511031633200350800001002003920039200392003920039
802042003815502000004025801001008000010080000500560000020019200382003899733999680100200800002002003820038118020110099100100800001000000000511031633200350800001002003920039200392003920039
802042003815602000008225801001008000010080000500560000020019200382003899733999680100200800002002003820038118020110099100100800001000000000511031633200350800001002003920039200392003920039
802042003815502000004025801001008000010080000500560000020019200382003899733999680100200800002002003820038118020110099100100800001000000000511031633200350800001002003920039200392003920039

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)031e3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)accfd5map dispatch bubble (d6)d9dadbddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
8002420047155087425800101080000108000050560000020019200382003899963100188001020800002020038200381180021109101080000100050205160005520035080000102003920039200392003920039
800242003816106725800101080000108000050560000020019200382003899963100188001020800002020038200381180021109101080000100050204160004420035080000102003920039200392003920039
800242003815503925800101080000108000050560000020019200382003899963100188001020800002020038200381180021109101080000100350206160004420035080000102003920039200392003920039
800242003815503925800101080000108000050560000020019200382003899963100188001020800002020038200381180021109101080000100050205160007520035080000102003920039200392003920039
800242003815503925800101080000108000050560000020019200382003899963100188001020800002020038200381180021109101080000100050206160007620035080000102003920039200392003920039
800242003815503925800101080000108000050560000020019200382003899963100188001020800002020038200381180021109101080000100050206160008720035080000102003920039200392003920039
800242003815503925800101080000108000050560000020019200382003899963100188001020800002020038200381180021109101080000100050206160005520035080000102003920039200392003920039
8002420038155014425800101080000108000050560000020019200382003899963100188001020800002020038200381180021109101080000100050204160005520035080000102003920039200392003920039
8002420038155016925800101080000108000050560000020019200382003899963100188001020800002020038200381180021109101080000100050204160006620035080000102003920039200392003920039
8002420038156010225800101080000108000050560000020019200382003899963100188001020800002020038200381180021109101080000100050205160005620035080000102003920039200392003920039