Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

MOVI (vector, 8H)

Test 1: uops

Code:

  movi v0.8h, #3

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

retire uop (01)cycle (02)03mmu table walk data (08)1e3f51schedule uop (52)schedule simd uop (54)dispatch simd uop (57)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map simd uop (7e)8283flush restart other nonspec (84)85inst all (8c)inst simd alu (9a)ld unit uop (a6)l1d cache writeback (a8)a9accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)f5f6f7f8fd
10042882004025100010001000700002692882881233146100010002882881110011000050073316112851000289289289289289
10042882004025100010001000700002692882881233146100010002882881110011000030073116112851000289289289289289
10042882004025100010001000700002692882881233146100010002882881110011000000073116112851000289289289289289
10042882004025100010001000700002692882881233146100010002882881110011000000093120112851000289289289289289
10042883001052510931000100070000269288338123314610001096288288111001100030222073116113231000289289289289289
100428820023825100010001000700002692883371333146100010002902881110011000000073116112851000289289289289289
10042883004025100010001000700002692882881233146100010002882881110011000000073116112851000289289289289289
10042882004025100010001000700002692882881233146100010002882881110011000000073116112851000289289289289289
10042882004025100010001000700002692882881233146100010002882881110011000000073116112851000289289289289289
100428820214025100010001000700002692882881233146100010002882881110011000000073116112851000289289289289289

Test 2: throughput

Count: 8

Code:

  movi v0.8h, #3
  movi v1.8h, #3
  movi v2.8h, #3
  movi v3.8h, #3
  movi v4.8h, #3
  movi v5.8h, #3
  movi v6.8h, #3
  movi v7.8h, #3

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)031e3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)5e60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d tlb miss (a1)l1d cache writeback (a8)acst memory order violation nonspec (c4)branch mispred nonspec (cb)cdcfd5map dispatch bubble (d6)ddfetch restart (de)e0eb? simd retires (ee)? int retires (ef)f5f6f7f8fd
8020420058155045258010010080000100800005005600000020019200382003899733999680100200800002002003820038118020110099100100800001000000000511021622200350800001002003920039200392003920039
8020420038155055258010010080000100800005005600000020019200382003899733999680100200800002002003820038118020110099100100800001000000000511021622200350800001002003920039200392003920039
80204200381550150258010010080000100800005005600000020019200382003899733999680100200800002002003820038118020110099100100800001000000000511021622200350800001002003920039200392003920039
8020420038155042258010010080000100800005005600000020019200382003899733999680100200800002002003820038118020110099100100800001000010000511021622200350800001002003920039200392003920039
80204200381551771118258010010080000100800005005600000020019200382003899733999680100200800002002003820038118020110099100100800001000000000511021622200350800001002003920039200392003920039
80204200381550705258010010080000100800005005600000020019200382003899733999680100200800002002003820038118020110099100100800001000000000511021622200350800001002003920039200392003920039
80204200381551242258010010080000100800005005600000020019200382003899733999680100200800002002003820038118020110099100100800001000000000511021622200350800001002003920039200392003920039
8020420038155042258010010080000100800005005600000020019200382003899733999680100200800002002003820038118020110099100100800001000000000511021622200350800001002003920039200392003920039
8020420038155042258010010080000100800005005600000020019200382003899733999680100200800002002003820038118020110099100100800001000000000511021622200350800001002003920039200392003920039
8020420038155040258010010080000100800005005600000020019200382003899733999680100200800002002003820038118020110099100100800001000000000511021622200350800001002003920039200392003920039

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)03181e3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)a9acc2branch cond mispred nonspec (c5)cfd0d5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)eaeb? simd retires (ee)? int retires (ef)f5f6f7f8fd
80024200471550039258001010800001080000505600000200192003820038999631001880010208000020200382003811800211091010800001000000502001161120035001480000102003920039200392003920039
8002420038155003925800101080000108000050560000020019200382003899963100188001020800002020038200381180021109101080000100030050200116112003500080000102003920039200392003920039
8002420038155003925800101080000108000050560000020019200382003899963100188001020800002020038200381180021109101080000103090050200116112003500080000102003920039200392003920039
8002420038156003925800101080000108000050560000020019200382003899963100188001020800002020038200381180021109101080000100004050200116112003500080000102003920039200392003920039
80024200381550153925800101080000108000050560000020019200382003899963100188001020800002020038200381180021109101080000100000050200116112003500080000102003920039200392003920039
80024200381550037525800101080000108000050560000020019200382003899963100188001020800002020038200381180021109101080000100090050200116112003500080000102003920039200392003920039
8002420038155003925800101080000108000050560000020019200382003899963100188001020800002020038200381180021109101080000100000050200116112003500080000102003920039200392003920039
80024200381550039258001010800001080000505600000200192003820038999631001880010208000020200382003811800211091010800001004120050200116112003500080000102003920039200392003920039
80024200381550062258001010800001080000505601840200192003820038999631001880010208000020200382003811800211091010800001050000502001161120035001480000102003920039200392003920039
8002420038156003925800101080000108000050560000020019200382003899963100188001020800002020038200381180021109101080000100000050200116112003500080000102003920039200392003920039