Firestorm: MOVI (vector, 8H, zero) measurements

Code:

  movi v0.8h, #0

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 0.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 0.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	51	60	69	6d	6e	map rewind (75)	map stall (76)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst simd alu (9a)	a9	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	f5	f6	f7	f8	fd
1004	152	1	0	27	150	0	134	152	152	3	10	152	152	1	1	1001	1000	0	0	75	2	15	2	2	149	1000	153	153	153	153	153
1004	152	1	0	50	150	0	134	152	152	3	10	152	152	1	1	1001	1000	0	0	75	2	15	2	2	149	1000	153	153	153	153	153
1004	152	1	0	27	150	0	134	152	152	3	10	152	152	1	1	1001	1000	0	0	75	2	15	2	2	149	1000	153	153	153	153	153
1004	152	1	0	27	150	0	134	152	152	3	10	152	152	1	1	1001	1000	0	0	75	2	15	2	2	149	1000	153	153	153	153	153
1004	152	1	0	27	150	0	134	152	152	3	10	152	152	1	1	1001	1000	0	0	75	2	15	2	2	149	1000	153	153	153	153	153
1004	152	1	0	27	150	0	134	152	152	3	10	152	152	1	1	1001	1000	0	0	75	2	15	2	2	149	1000	153	153	153	153	153
1004	152	1	0	27	150	1	134	152	152	3	10	152	152	1	1	1001	1000	0	0	75	2	15	2	2	149	1000	153	153	153	153	153
1004	152	1	0	27	150	1	134	152	152	3	10	152	152	1	1	1001	1000	0	0	75	2	15	2	2	149	1000	153	153	153	153	153
1004	152	1	0	27	150	0	134	152	152	3	10	152	152	1	1	1001	1000	0	0	75	2	15	2	2	149	1000	153	153	153	153	153
1004	152	1	0	27	150	0	134	152	152	3	10	152	152	1	1	1001	1000	0	0	75	2	15	2	2	149	1000	153	153	153	153	153

Count: 8

Code:

  movi v0.8h, #0
  movi v1.8h, #0
  movi v2.8h, #0
  movi v3.8h, #0
  movi v4.8h, #0
  movi v5.8h, #0
  movi v6.8h, #0
  movi v7.8h, #0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.1258

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	l2 tlb miss instruction (0a)	l2 tlb miss data (0b)	18	19	1e	1f	3a	3f	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	69	6d	6e	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	c2	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
80204	10077	78	0	0	0	0	0	42	0	0	35	9554	100	100	100	500	0	10034	10060	10060	3	18	100	200	200	10250	10060	1	1	80201	100	99	100	100	80000	100	0	0	0	0	0	0	0	0	0	0	5112	2	16	2	2	10057	0	80000	100	10061	10061	10061	10061	10061
80204	10060	78	0	0	0	0	0	6	0	0	35	9554	100	100	100	500	0	10034	10060	10060	3	18	100	200	200	10060	10060	1	1	80201	100	99	100	100	80000	100	0	0	0	0	0	0	0	0	0	0	5112	2	16	2	2	10057	0	80000	100	10061	10061	10061	10061	10061
80204	10060	77	0	0	0	0	0	24	0	0	35	9554	100	100	100	500	0	10034	10060	10060	3	18	100	200	200	10060	10060	1	1	80201	100	99	100	100	80000	100	0	0	0	0	0	0	0	0	0	0	5112	2	16	2	2	10057	0	80000	100	10061	10061	10061	10061	10061
80204	10060	78	0	0	0	0	0	24	0	0	35	9554	100	100	100	500	0	10034	10060	10060	3	18	100	200	200	10060	10060	1	1	80201	100	99	100	100	80000	100	0	0	0	0	0	0	0	0	0	0	5112	2	16	2	2	10057	0	80000	100	10061	10061	10061	10061	10061
80204	10060	78	0	0	0	0	0	0	0	0	35	9554	100	100	100	500	0	10034	10060	10060	3	18	100	200	200	10060	10060	1	1	80201	100	99	100	100	80000	100	0	0	0	0	0	0	0	0	0	0	5112	2	16	2	2	10057	0	80000	100	10061	10061	10061	10061	10061
80204	10060	81	0	0	0	0	0	6	0	0	175	9554	100	100	100	500	0	10034	10060	10060	3	18	100	200	200	10060	10060	1	1	80201	100	99	100	100	80000	100	0	0	0	0	0	0	0	0	0	0	5128	2	16	2	2	10057	0	80000	100	10061	10061	10061	10061	10061
80204	10060	78	0	0	0	0	0	0	0	0	35	9554	100	100	100	500	0	10034	10060	10060	3	18	100	200	200	10060	10060	1	1	80201	100	99	100	100	80000	100	0	0	0	0	0	0	0	0	0	0	5112	2	16	2	2	10057	0	80000	100	10061	10061	10061	10061	10061
80204	10060	78	0	0	0	0	0	0	0	0	35	9554	100	100	100	500	0	10034	10060	10060	3	18	100	200	200	10060	10060	1	1	80201	100	99	100	100	80000	100	0	0	0	0	0	0	0	0	0	0	5112	2	16	2	2	10057	0	80000	100	10061	10061	10061	10061	10061
80204	10060	78	0	0	0	0	0	0	0	0	35	9554	100	100	100	500	1	10034	10060	10060	3	18	100	200	200	10060	10060	1	1	80201	100	99	100	100	80000	100	0	0	0	0	0	0	0	0	0	0	5112	2	16	2	2	10057	0	80000	100	10061	10061	10061	10061	10061
80204	10060	78	0	0	0	0	0	42	0	0	35	9554	100	100	100	500	1	10034	10060	10060	3	18	100	200	200	10060	10060	1	1	80201	100	99	100	100	80000	100	0	0	0	0	0	0	0	0	0	0	5112	2	16	2	2	10057	0	80000	100	10061	10061	10061	10061	10739

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.1255

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	69	6d	6e	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d cache writeback (a8)	ac	c2	cf	d0	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
80024	10044	78	30	35	9982	10	10	10	50	0	10012	10038	10038	3	18	10	20	20	10038	10038	1	1	80021	10	9	10	10	80000	10	0	0	0	5024	0	6	16	3	4	10035	80000	10	10039	10039	10039	10039	10039
80024	10038	78	12	35	9982	10	10	10	50	0	10012	10038	10038	3	18	10	20	20	10038	10038	1	1	80021	10	9	10	10	80000	10	0	0	0	5028	0	4	16	4	3	10035	80000	10	10039	10039	10039	10039	10039
80024	10038	78	0	35	9982	10	10	10	50	0	10012	10038	10038	3	18	10	20	20	10038	10038	1	1	80021	10	9	10	10	80000	10	0	3	0	5023	0	4	16	3	4	10035	80000	10	10039	10039	10039	10039	10039
80024	10038	77	9	35	9982	10	10	10	50	0	10012	10038	10038	3	18	10	20	20	10038	10038	1	1	80021	10	9	10	10	80000	10	0	0	0	5026	0	7	16	7	7	10035	80000	10	10039	10039	10039	10039	10039
80024	10038	77	0	35	9982	10	10	10	50	1	10012	10038	10038	3	18	10	20	20	10038	10038	1	1	80021	10	9	10	10	80000	10	0	0	0	5027	0	4	16	4	3	10035	80000	10	10039	10039	10039	10039	10039
80024	10038	78	0	35	9982	10	10	10	50	0	10012	10038	10038	3	18	10	20	20	10038	10038	1	1	80021	10	9	10	10	80000	10	0	0	0	5024	0	7	16	4	7	10035	80000	10	10039	10039	10039	10039	10039
80024	10038	78	6	35	9982	10	10	10	50	0	10012	10038	10038	3	18	10	20	20	10038	10038	1	1	80021	10	9	10	10	80000	10	0	0	0	5026	0	6	16	4	4	10035	80000	10	10039	10039	10039	10039	10039
80024	10038	78	0	63	9982	10	10	10	50	0	10012	10038	10038	3	18	10	20	20	10038	10038	1	1	80021	10	9	10	10	80000	10	0	0	0	5024	0	4	16	4	7	10035	80000	10	10039	10039	10039	10039	10039
80024	10038	78	6	35	9982	10	10	10	50	0	10012	10038	10038	3	18	10	20	20	10038	10038	1	1	80021	10	9	10	10	80000	10	0	0	0	5024	0	4	16	6	7	10035	80000	10	10039	10039	10039	10039	10039
80024	10038	78	0	35	9982	10	10	10	50	0	10012	10038	10038	17	18	10	20	20	10038	10038	1	1	80021	10	9	10	10	80000	10	0	0	0	5027	0	4	16	4	3	10035	80000	10	10039	10039	10039	10039	10039

MOVI (vector, 8H, zero)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations