Firestorm: MOV (vector, 16B) measurements

Code:

  mov v0.16b, v1.16b
  nop ; nop ; nop ; nop ; nop ; nop ; nop

Initialization

  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires (minus 7 nops): 1.000

Issues: 0.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 0.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	51	60	69	6d	6e	map rewind (75)	map stall (76)	map simd uop (7e)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst simd alu (9a)	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	f5	f6	f7	f8	fd
8004	1027	7	0	27	1025	0	1009	1027	1027	3	10	1000	2000	1027	1027	1	1	8001	1000	0	3	512	3	15	1	1	1024	1000	1028	1028	1028	1028	1028
8004	1027	8	0	27	1025	1	1009	1027	1027	3	10	1000	2000	1027	1027	1	1	8001	1000	0	0	512	1	15	1	1	1024	1000	1028	1028	1028	1028	1028
8004	1027	7	0	27	1025	0	1009	1027	1027	3	10	1000	2000	1027	1027	1	1	8001	1000	0	0	512	1	15	1	1	1024	1000	1028	1028	1028	1028	1028
8004	1027	8	0	27	1025	0	1009	1027	1027	3	10	1000	2000	1027	1027	1	1	8001	1000	0	0	513	2	15	1	1	1024	1000	1028	1028	1028	1028	1028
8004	1027	8	0	27	1025	0	1009	1027	1027	3	10	1000	2000	1027	1027	1	1	8001	1000	0	0	513	1	15	1	1	1050	1000	1028	1028	1028	1028	1028
8004	1027	8	0	27	1025	0	1009	1027	1027	3	10	1000	2000	1027	1027	1	1	8001	1000	0	0	512	1	15	1	1	1024	1000	1028	1028	1028	1028	1028
8004	1027	7	0	27	1025	0	1009	1027	1027	3	10	1000	2000	1027	1027	1	1	8001	1000	0	15	512	1	15	1	1	1024	1000	1028	1028	1028	1028	1028
8004	1027	7	0	27	1025	0	1009	1027	1027	3	10	1000	2000	1027	1027	1	1	8001	1000	0	0	512	1	15	1	1	1024	1000	1028	1028	1028	1028	1028
8004	1027	7	0	27	1025	0	1009	1027	1027	3	10	1000	2000	1027	1027	1	1	8001	1000	0	0	512	1	15	1	1	1024	1000	1028	1028	1028	1028	1028
8004	1027	7	0	27	1025	0	1009	1027	1027	3	10	1000	2000	1027	1027	1	1	8001	1000	0	0	512	1	15	1	1	1024	1000	1028	1028	1028	1028	1028

Test 2: Latency 1->2

Chain cycles: 2

Code:

  mov v0.16b, v1.16b
  add v1.16b, v1.16b, v0.16b

Initialization

  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 2 chain cycles): 0.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3a	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d cache writeback (a8)	ac	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
20204	20037	150	0	0	688	19686	25	10100	100	10000	100	10000	500	2847506	0	20018	20037	20037	17178	6	17491	10100	200	20008	200	40016	20037	20037	1	1	20201	100	99	100	100	20000	100	0	0	1	1	1	1317	1	16	1	1	19842	20000	100	20038	20038	20038	20038	20038
20204	20037	158	0	0	1336	19686	25	10100	100	10000	100	10000	500	2847506	0	20018	20037	20037	17178	6	17491	10100	200	20008	200	40016	20037	20037	1	1	20201	100	99	100	100	20000	100	0	0	1	1	1	1317	1	16	1	1	19842	20000	100	20038	20038	20038	20038	20038
20204	20037	150	0	0	105	19686	25	10100	100	10000	100	10000	500	2847506	0	20018	20037	20037	17178	6	17491	10100	200	20008	200	40016	20037	20037	1	1	20201	100	99	100	100	20000	100	0	0	1	1	1	1317	1	16	1	1	19842	20000	100	20038	20038	20038	20038	20038
20204	20037	150	0	0	61	19686	25	10128	113	10000	100	10000	500	2847506	0	20018	20037	20037	17178	6	17491	10100	200	20008	200	40016	20037	20037	1	1	20201	100	99	100	100	20000	100	0	0	1	1	1	1317	1	16	1	1	19842	20000	100	20038	20038	20038	20038	20038
20204	20037	150	0	0	61	19686	25	10100	100	10000	100	10000	500	2847506	0	20018	20037	20037	17178	6	17491	10100	200	20008	200	40016	20037	20037	1	1	20201	100	99	100	100	20000	100	0	0	1	1	1	1317	1	16	1	1	19842	20000	100	20038	20038	20038	20038	20038
20204	20037	161	0	0	786	19686	25	10100	100	10000	100	10000	500	2847506	0	20018	20037	20037	17178	6	17491	10100	200	20008	200	40016	20037	20037	1	1	20201	100	99	100	100	20000	100	0	0	1	1	1	1317	1	16	1	1	19842	20000	100	20038	20038	20038	20038	20038
20204	20037	150	0	0	168	19686	25	10100	100	10000	100	10000	500	2847506	0	20018	20037	20037	17178	6	17491	10100	200	20008	200	40016	20037	20037	1	1	20201	100	99	100	100	20000	100	0	0	1	1	1	1317	1	16	2	1	19842	20000	100	20038	20038	20038	20038	20038
20204	20037	150	0	1	147	19686	25	10100	100	10000	100	10000	500	2847506	0	20018	20037	20037	17178	6	17491	10100	200	20008	200	40016	20037	20037	1	1	20201	100	99	100	100	20000	100	0	0	1	1	1	1317	1	16	1	1	19842	20000	100	20038	20038	20038	20038	20038
20204	20037	150	0	0	727	19686	25	10100	100	10000	100	10000	500	2847506	0	20018	20037	20037	17178	6	17491	10100	200	20008	200	40016	20037	20037	1	1	20201	100	99	100	100	20000	100	28	6	1	1	1	1317	1	16	1	2	19842	20000	100	20038	20038	20038	20038	20038
20204	20037	150	0	0	61	19686	25	10100	100	10000	100	10000	500	2847506	0	20018	20037	20037	17178	6	17491	10100	200	20008	200	40016	20037	20037	1	1	20201	100	99	100	100	20000	100	34	3	1	1	1	1317	1	16	1	1	19842	20000	100	20038	20038	20038	20038	20038

1000 unrolls and 10 iterations

Result (median cycles for code, minus 2 chain cycles): 0.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	l2 tlb miss data (0b)	18	19	1e	1f	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
20024	20037	150	0	0	0	0	0	0	1002	19686	25	10010	10	10000	10	10000	50	2847521	0	20018	20037	20037	17193	3	17517	10010	20	20000	20	40000	20037	20037	1	1	20021	10	9	10	10	20000	10	0	0	0	0	0	0	0	1270	1	16	1	1	19833	0	20000	10	20038	20038	20038	20038	20038
20024	20037	150	0	0	0	0	0	0	103	19686	25	10010	10	10000	10	10000	50	2847521	0	20018	20037	20037	17193	3	17517	10010	20	20000	20	40000	20037	20037	1	1	20021	10	9	10	10	20000	10	0	0	0	0	0	0	0	1270	1	16	1	1	19833	0	20000	10	20038	20100	20038	20038	20038
20024	20037	150	0	0	0	0	0	0	61	19686	25	10010	10	10000	10	10000	50	2847521	0	20018	20037	20037	17193	3	17517	10010	20	20000	20	40000	20037	20037	1	1	20021	10	9	10	10	20000	10	0	0	0	0	0	0	0	1270	1	16	1	1	19833	0	20000	10	20038	20038	20038	20038	20038
20024	20037	150	0	0	0	0	0	0	61	19686	25	10010	10	10000	10	10000	50	2847521	0	20018	20037	20037	17193	3	17517	10010	20	20000	20	40000	20037	20037	1	1	20021	10	9	10	10	20000	10	0	0	0	0	0	0	0	1270	1	16	1	1	19833	0	20000	10	20038	20038	20038	20038	20038
20024	20037	150	0	0	0	0	0	88	103	19686	25	10010	10	10000	10	10000	50	2847521	0	20018	20037	20037	17193	3	17517	10010	20	20000	20	40000	20037	20037	1	1	20021	10	9	10	10	20000	10	0	0	0	0	0	0	0	1270	1	16	1	1	19833	0	20000	10	20038	20038	20038	20038	20038
20024	20037	150	0	0	0	0	0	0	187	19686	25	10010	10	10000	10	10000	50	2847521	0	20018	20037	20037	17193	3	17517	10010	20	20000	20	40000	20037	20037	1	1	20021	10	9	10	10	20000	10	0	0	0	0	0	0	0	1270	1	16	1	1	19833	0	20000	10	20038	20038	20038	20038	20038
20024	20037	150	0	0	0	0	0	0	61	19686	25	10010	10	10000	10	10000	50	2847521	0	20018	20037	20037	17193	3	17517	10010	20	20000	20	40000	20037	20037	1	1	20021	10	9	10	10	20000	10	0	0	0	0	0	0	0	1270	1	16	1	1	19833	0	20000	10	20038	20038	20038	20038	20038
20024	20037	150	0	0	0	0	0	0	61	19686	25	10010	10	10000	10	10000	50	2847521	0	20018	20037	20037	17193	3	17517	10010	20	20000	20	40000	20037	20037	1	1	20021	10	9	10	10	20000	10	0	0	0	0	0	0	0	1270	2	16	1	1	19833	0	20000	10	20038	20038	20038	20038	20038
20024	20037	150	0	0	0	0	0	0	203	19686	25	10010	10	10000	10	10000	50	2847521	0	20018	20037	20037	17193	3	17517	10010	20	20000	20	40000	20037	20037	1	1	20021	10	9	10	10	20000	10	0	0	0	0	0	0	0	1270	1	16	1	2	19833	0	20000	10	20038	20038	20038	20038	20038
20024	20037	150	0	0	0	0	0	0	357	19686	25	10010	10	10000	10	10000	50	2847521	0	20018	20037	20098	17193	3	17517	10010	20	20000	20	40000	20037	20037	1	1	20021	10	9	10	10	20000	10	0	0	0	0	0	0	0	1270	1	16	1	1	19833	0	20000	10	20038	20038	20038	20038	20038

Test 3: throughput

Count: 8

Code:

  mov v0.16b, v8.16b
  mov v1.16b, v8.16b
  mov v2.16b, v8.16b
  mov v3.16b, v8.16b
  mov v4.16b, v8.16b
  mov v5.16b, v8.16b
  mov v6.16b, v8.16b
  mov v7.16b, v8.16b

Initialization

  movi v8.16b, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.1258

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	1e	3f	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	69	6d	6e	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d cache writeback (a8)	a9	aa	ac	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	dd	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
80204	10089	81	0	12	28	9561	100	100	100	500	1	10042	10064	10064	6	10	100	200	80056	200	160112	10064	10064	1	1	80201	100	99	100	100	80000	100	0	0	0	0	1	1	1	5119	0	16	0	10061	80000	100	10065	10065	10065	10065	10065
80204	10064	80	0	0	28	9561	100	100	100	500	1	10042	10064	10064	6	10	100	200	80056	200	160112	10064	10064	1	1	80201	100	99	100	100	80000	100	0	0	0	0	1	1	1	5120	0	16	0	10061	80000	100	10065	10065	10065	10065	10065
80204	10064	78	0	0	140	9561	100	100	100	500	1	10042	10064	10064	6	10	100	200	80056	200	160112	10064	10064	1	1	80201	100	99	100	100	80000	100	0	0	0	0	1	1	1	5119	0	16	0	10061	80000	100	10065	10065	10065	10065	10065
80204	10064	78	0	27	28	9561	100	100	100	500	1	10042	10064	10064	6	10	100	200	80056	200	160112	10064	10064	1	1	80201	100	99	100	100	80000	100	0	0	0	0	1	1	1	5119	0	16	0	10061	80000	100	10065	10065	10065	10065	10065
80204	10064	78	0	0	28	9561	100	100	100	500	1	10042	10064	10064	6	10	100	200	80056	200	160112	10064	10064	1	1	80201	100	99	100	100	80000	100	0	0	0	0	1	1	1	5119	0	16	0	10061	80000	100	10065	10065	10065	10065	10065
80204	10064	78	0	0	28	9561	100	100	100	500	1	10042	10064	10064	6	10	100	200	80056	200	160112	10064	10064	1	1	80201	100	99	100	100	80000	100	0	0	0	0	1	1	1	5119	0	16	0	10061	80000	100	10065	10065	10065	10065	10065
80204	10064	78	0	12	28	9561	100	100	100	500	1	10042	10064	10064	6	10	100	200	80056	200	160112	10064	10064	1	1	80201	100	99	100	100	80000	100	0	0	0	0	1	1	1	5119	0	16	0	10061	80000	100	10065	10065	10065	10065	10065
80204	10064	78	0	0	28	9561	100	100	100	500	1	10042	10064	10064	6	10	100	200	80056	200	160112	10064	10064	1	1	80201	100	99	100	100	80000	100	0	0	0	0	1	1	1	5119	0	16	0	10061	80000	100	10065	10065	10065	10065	10065
80204	10064	77	0	12	28	9561	100	100	100	500	1	10042	10064	10064	6	10	100	200	80056	200	160112	10064	10064	1	1	80201	100	99	100	100	80000	100	0	0	0	0	1	1	1	5119	0	16	0	10061	80000	100	10065	10065	10065	10065	10065
80204	10064	78	0	12	28	9561	100	100	100	500	1	10042	10064	10064	6	10	100	200	80056	200	160112	10064	10064	1	1	80201	100	99	100	100	80000	100	0	0	0	3	1	1	1	5119	0	16	0	10061	80000	100	10065	10065	10065	10065	10065

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.1255

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk instruction (07)	l2 tlb miss instruction (0a)	1e	3f	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	69	6d	6e	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d cache writeback (a8)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
80024	10055	78	2	2	0	89	9982	10	10	10	50	1	10012	10069	10038	3	18	10	20	80000	20	160000	10038	10038	1	1	80021	10	9	10	10	80000	10	0	0	5037	27	16	29	26	10035	80000	10	10039	10039	10039	10039	10039
80024	10038	77	2	2	0	89	9982	10	10	10	50	1	10012	10098	10038	3	18	10	20	80000	20	160000	10038	10038	1	1	80021	10	9	10	10	80000	10	0	2	5045	28	16	27	26	10035	80000	10	10039	10039	10039	10039	10039
80024	10038	78	2	2	33	47	9982	10	10	10	50	1	10012	10082	10038	3	18	10	20	80000	20	160000	10038	10038	1	1	80021	10	9	10	10	80000	10	0	0	5047	27	16	16	28	10035	80000	10	10039	10039	10039	10039	10039
80024	10038	78	2	2	15	47	9982	10	10	10	50	1	10012	10085	10038	3	18	10	20	80000	20	160000	10038	10038	1	1	80021	10	9	10	10	80000	10	0	0	5040	20	16	25	20	10035	80000	10	10039	10039	10039	10039	10039
80024	10038	78	2	2	6	522	9982	10	10	10	50	1	10012	10082	10038	3	18	10	20	80000	20	160000	10038	10038	1	1	80021	10	9	10	10	80000	10	0	0	5043	22	16	23	18	10035	80000	10	10039	10039	10039	10039	10039
80024	10038	78	2	2	12	47	9982	10	10	10	50	1	10012	10090	10038	3	18	10	20	80269	20	160000	10038	10038	1	1	80021	10	9	10	10	80000	10	0	0	5035	17	16	27	16	10035	80000	10	10039	10039	10039	10039	10039
80024	10038	78	2	2	0	47	9982	10	10	10	50	1	10012	10086	10038	3	18	10	20	80000	20	160000	10038	10038	1	1	80021	10	9	10	10	80000	10	0	1	5043	25	16	27	20	10035	80000	10	10039	10039	10039	10039	10039
80024	10038	78	2	2	0	47	9982	10	10	10	50	1	10090	10091	10038	3	18	10	20	80000	20	160000	10038	10038	1	1	80021	10	9	10	10	80000	10	0	0	5045	11	16	28	20	10035	80000	10	10039	10039	10039	10039	10039
80024	10038	78	2	2	0	41	9982	10	10	10	50	1	10012	10083	10038	3	18	10	20	80000	20	160000	10038	10038	1	1	80021	10	9	10	10	80000	10	0	0	5044	23	16	18	23	10035	80000	10	10039	10039	10039	10039	10039
80024	10038	78	2	2	0	47	9982	10	10	10	50	1	10012	10084	10038	3	18	10	20	80000	20	160000	10044	10038	1	1	80021	10	9	10	10	80000	10	0	0	5042	29	16	27	26	10035	80000	10	10039	10039	10039	10039	10039

MOV (vector, 16B)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->2

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations