Firestorm: MUL (by element, 8H) measurements

Code:

  mul v0.8h, v0.8h, v1.h[1]

Initialization

  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	4e	51	schedule uop (52)	schedule simd uop (54)	dispatch simd uop (57)	ldst uops in schedulers (5b)	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map simd uop (7e)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst simd alu (9a)	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	f5	f6	f7	f8	fd
1004	3037	23	0	82	2548	25	1000	1000	1000	398313	3018	3037	3037	2415	3	2895	1000	1000	2000	3037	3037	1	1	1001	1000	0	0	73	2	16	1	1	2630	1000	3038	3038	3038	3038	3038
1004	3037	23	0	61	2548	25	1000	1000	1000	398313	3018	3037	3037	2415	3	2895	1000	1000	2000	3037	3037	1	1	1001	1000	0	0	73	1	16	1	1	2630	1000	3038	3038	3038	3038	3038
1004	3037	23	0	84	2548	25	1000	1000	1000	398313	3018	3037	3037	2415	3	2895	1000	1000	2000	3037	3037	1	1	1001	1000	0	0	73	1	16	1	1	2630	1000	3038	3038	3038	3038	3038
1004	3037	22	0	61	2548	25	1000	1008	1000	398313	3018	3037	3037	2415	3	2895	1000	1000	2000	3037	3037	1	1	1001	1000	0	0	73	1	16	1	1	2630	1000	3038	3038	3038	3038	3038
1004	3037	23	0	61	2548	25	1000	1000	1000	398313	3018	3037	3037	2415	3	2895	1000	1000	2000	3037	3037	1	1	1001	1000	0	0	73	1	16	1	1	2630	1000	3038	3038	3038	3038	3038
1004	3037	23	0	61	2548	25	1000	1000	1000	398313	3018	3037	3037	2415	3	2895	1000	1000	2000	3037	3037	1	1	1001	1000	0	0	73	1	16	1	1	2630	1000	3038	3038	3038	3038	3038
1004	3037	23	0	82	2548	25	1000	1000	1000	398313	3018	3037	3037	2415	3	2895	1000	1000	2000	3037	3037	1	1	1001	1000	0	0	73	1	16	1	1	2630	1000	3038	3038	3038	3038	3038
1004	3037	23	0	82	2548	25	1000	1000	1000	398313	3018	3037	3037	2415	3	2895	1000	1000	2000	3037	3037	1	1	1001	1000	0	0	73	1	16	1	1	2630	1000	3038	3038	3038	3038	3038
1004	3037	22	0	61	2548	25	1000	1000	1000	398313	3018	3037	3037	2415	3	2895	1000	1000	2000	3037	3037	1	1	1001	1000	0	0	73	1	16	1	1	2630	1000	3038	3038	3038	3038	3038
1004	3037	23	0	61	2548	25	1000	1000	1000	398313	3018	3037	3037	2415	3	2895	1000	1000	2000	3037	3037	1	1	1001	1000	0	0	73	1	16	1	1	2630	1000	3038	3038	3038	3038	3038

Test 2: Latency 1->2

Code:

  mul v0.8h, v0.8h, v1.h[1]

Initialization

  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	18	19	1e	1f	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10204	30037	224	0	0	0	0	251	29548	25	10100	100	10000	100	10000	500	4277313	0	30018	30037	30037	28265	3	28745	10100	200	10161	200	20000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	710	1	16	1	1	29634	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	0	0	61	29548	25	10100	100	10000	100	10000	500	4277313	0	30018	30037	30037	28265	3	28745	10100	200	10000	200	20000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	710	1	16	1	1	29634	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	0	0	61	29548	25	10100	100	10000	100	10000	500	4277313	0	30018	30037	30037	28265	3	28745	10100	200	10000	200	20000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	3	710	1	16	1	1	29634	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	0	0	61	29548	25	10100	100	10000	100	10000	500	4277313	0	30018	30037	30037	28265	3	28745	10100	200	10000	200	20000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	72	710	1	16	1	1	29634	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	0	0	61	29548	25	10100	100	10000	100	10000	500	4277313	0	30065	30037	30037	28265	3	28745	10100	200	10000	200	20000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	710	1	16	1	1	29634	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	0	0	61	29548	25	10100	100	10000	100	10000	500	4277313	0	30018	30037	30037	28265	3	28745	10100	200	10000	200	20000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	710	1	16	1	1	29634	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	0	0	61	29548	25	10100	100	10000	100	10000	500	4277313	0	30018	30037	30037	28265	3	28745	10100	200	10000	200	20000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	27	710	1	16	1	1	29634	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	0	0	61	29548	25	10100	100	10000	100	10000	500	4277313	0	30018	30037	30037	28265	3	28745	10100	200	10000	200	20000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	710	1	16	1	1	29634	10000	100	30038	30038	30038	30038	30038
10204	30037	224	0	0	0	0	61	29548	25	10100	100	10000	100	10000	500	4278672	0	30018	30037	30037	28265	3	28745	10100	200	10000	200	20000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	710	1	16	1	1	29634	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	0	0	61	29548	25	10100	100	10000	100	10000	500	4277313	0	30018	30037	30037	28265	3	28745	10100	200	10000	200	20000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	710	1	16	1	1	29634	10000	100	30038	30038	30038	30038	30038

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk instruction (07)	18	19	1e	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	ac	branch mispred nonspec (cb)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10024	30037	225	0	1	1	0	61	29548	25	10010	10	10000	10	10000	50	4277313	0	30018	30037	30037	28287	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	640	3	16	4	3	29632	0	10000	10	30038	30038	30038	30038	30038
10024	30037	225	1	0	0	0	61	29548	25	10010	10	10000	10	10000	50	4277313	0	30018	30037	30037	28287	3	28767	10012	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	8269	0	642	3	16	2	2	29630	0	10000	10	30038	30038	30038	30038	30038
10024	30037	225	1	0	0	0	103	29548	25	10010	10	10000	12	10000	60	4277313	0	30018	30037	30037	28287	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	2845	0	640	2	16	2	2	29630	0	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	0	0	61	29548	25	10010	10	10000	10	10000	50	4277313	0	30018	30037	30037	28287	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	640	2	16	3	3	29632	0	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	0	0	61	29548	25	10010	10	10000	10	10000	50	4277313	0	30018	30037	30037	28287	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	640	2	16	2	2	29630	0	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	0	0	61	29548	25	10010	10	10000	10	10000	50	4277313	0	30018	30037	30037	28287	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	640	2	16	2	2	29630	0	10000	10	30038	30038	30038	30038	30038
10024	30037	224	0	0	0	0	61	29548	25	10010	10	10000	10	10000	50	4277313	0	30018	30037	30037	28287	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	640	2	16	2	2	29630	0	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	0	0	61	29548	25	10010	10	10000	10	10000	50	4277313	0	30018	30037	30037	28287	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	640	2	16	2	2	29630	0	10000	10	30038	30038	30038	30038	30038
10024	30037	225	1	0	0	0	61	29548	25	10010	10	10000	12	10000	60	4277313	0	30018	30037	30037	28287	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	640	2	16	2	2	29630	0	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	0	0	61	29548	25	10010	10	10000	10	10000	50	4277313	0	30018	30037	30037	28287	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	640	4	16	2	2	29630	0	10000	10	30038	30038	30038	30038	30038

Test 3: Latency 1->3

Code:

  mul v0.8h, v1.8h, v0.h[1]

Initialization

  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10204	30037	225	0	61	29548	25	10100	100	10000	100	10000	500	4277313	1	30018	0	30037	30037	28265	3	28745	10100	200	10000	200	20000	30037	30037	1	1	10201	100	99	100	100	10000	100	16	0	710	1	16	1	1	29634	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	61	29548	25	10100	100	10000	100	10000	500	4277313	1	30018	0	30037	30037	28265	3	28745	10100	200	10000	200	20000	30037	30085	2	1	10201	100	99	100	100	10000	100	0	9	710	1	16	1	1	29634	10000	100	30038	30038	30038	30038	30038
10204	30037	225	12	61	29548	25	10100	100	10000	100	10000	500	4277313	0	30018	0	30037	30037	28265	3	28745	10100	200	10000	200	20000	30037	30037	1	1	10201	100	99	100	100	10000	100	37	0	710	1	16	1	1	29634	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	61	29548	25	10100	100	10000	100	10000	500	4277313	1	30018	0	30037	30037	28265	3	28745	10100	200	10000	200	20000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	18	710	1	16	1	1	29634	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	61	29548	25	10100	100	10000	100	10000	500	4277313	1	30018	0	30037	30037	28265	3	28745	10100	200	10000	200	20000	30037	30037	1	1	10201	100	99	100	100	10000	100	41	0	710	1	16	1	1	29634	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	61	29548	25	10100	100	10000	100	10000	500	4277313	0	30018	0	30037	30037	28265	3	28745	10100	200	10000	200	20000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	9	710	1	16	1	1	29634	10000	100	30038	30038	30038	30038	30038
10204	30037	225	15	61	29548	25	10100	100	10000	100	10000	500	4277313	1	30018	0	30037	30037	28265	3	28745	10100	200	10000	200	20000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	9	710	1	16	1	1	29634	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	920	29548	25	10100	100	10000	100	10000	500	4277313	1	30018	0	30037	30037	28265	3	28745	10100	200	10000	200	20000	30037	30037	1	1	10201	100	99	100	100	10000	100	33	0	710	1	16	1	1	29634	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	61	29548	25	10100	100	10000	100	10032	500	4277313	0	30018	0	30037	30037	28265	3	28745	10100	200	10000	200	20000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	9	710	1	16	1	1	29634	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	61	29548	25	10100	100	10000	100	10000	500	4277313	1	30018	0	30037	30037	28265	3	28745	10100	200	10000	200	20000	30037	30037	1	1	10201	100	99	100	100	10000	100	44	0	710	1	16	1	1	29634	10000	100	30038	30038	30038	30038	30038

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	69	6d	6e	map stall dispatch (70)	simd prf full (72)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10024	30037	225	61	29548	25	10010	10	10000	10	10000	50	4277313	30018	30037	30037	28287	0	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10022	10	9	10	10	10000	10	25	0	640	2	16	2	2	29630	10000	10	30038	30038	30038	30038	30038
10024	30037	225	726	29548	25	10010	10	10000	10	10000	50	4277313	30018	30037	30037	28287	0	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	9	640	2	16	2	2	29630	10000	10	30038	30038	30038	30038	30038
10024	30037	225	103	29548	25	10010	10	10000	10	10000	50	4277313	30018	30037	30037	28287	0	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	39	0	640	2	16	2	2	29630	10000	10	30038	30038	30038	30038	30038
10024	30037	225	61	29548	25	10010	10	10000	10	10000	50	4277313	30018	30037	30037	28287	0	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	49	0	640	2	16	2	2	29630	10000	10	30038	30038	30038	30038	30038
10024	30037	225	61	29548	25	10010	10	10000	10	10000	50	4277313	30018	30037	30037	28287	0	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	8	0	640	2	16	2	2	29630	10000	10	30038	30038	30038	30038	30038
10024	30037	225	61	29548	25	10010	10	10000	10	10000	50	4277313	30018	30037	30037	28287	0	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	39	0	640	2	16	2	2	29630	10000	10	30038	30038	30038	30038	30038
10024	30037	225	61	29548	25	10010	10	10000	10	10000	50	4277313	30018	30037	30037	28287	0	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	41	0	640	2	16	2	2	29630	10000	10	30038	30038	30038	30038	30038
10024	30037	225	61	29548	25	10010	10	10000	10	10000	50	4277313	30018	30037	30037	28287	0	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	50	0	640	2	16	2	2	29630	10000	10	30038	30038	30038	30038	30038
10024	30037	225	61	29548	25	10010	10	10000	10	10000	50	4277313	30018	30037	30037	28287	0	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	36	0	640	2	16	2	2	29630	10000	10	30038	30038	30038	30038	30038
10024	30037	224	61	29548	25	10010	10	10000	10	10298	50	4277313	30018	30037	30037	28287	0	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	1	3	640	2	16	2	2	29630	10000	10	30038	30038	30038	30038	30038

Test 4: throughput

Count: 8

Code:

  mul v0.8h, v8.8h, v9.h[1]
  mul v1.8h, v8.8h, v9.h[1]
  mul v2.8h, v8.8h, v9.h[1]
  mul v3.8h, v8.8h, v9.h[1]
  mul v4.8h, v8.8h, v9.h[1]
  mul v5.8h, v8.8h, v9.h[1]
  mul v6.8h, v8.8h, v9.h[1]
  mul v7.8h, v8.8h, v9.h[1]

Initialization

  movi v8.16b, 9
  movi v9.16b, 10

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2505

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
80204	20039	150	41	25	80100	100	80000	100	80000	541	640000	0	20020	20039	20039	9973	3	9997	80100	200	80000	200	160000	20039	20039	1	1	80201	100	99	100	100	80000	100	12	3	5110	3	16	1	1	20036	16	80000	100	20040	20040	20040	20040	20040
80204	20039	150	41	25	80100	100	80000	100	80000	500	640000	0	20020	20039	20039	9973	3	9997	80100	200	80000	200	160000	20039	20039	1	1	80201	100	99	100	100	80000	100	0	3	5110	1	16	1	1	20036	0	80000	100	20040	20040	20040	20040	20040
80204	20039	150	41	25	80100	100	80000	100	80000	500	640000	0	20020	20039	20039	9973	3	9997	80100	200	80000	200	160000	20039	20039	1	1	80201	100	99	100	100	80000	100	0	3	5110	1	16	1	1	20036	0	80000	100	20040	20040	20040	20040	20040
80204	20039	150	41	25	80100	100	80000	100	80000	500	640000	0	20020	20039	20039	9973	3	9997	80100	200	80000	200	160000	20039	20039	1	1	80201	100	99	100	100	80000	100	0	0	5110	1	16	1	1	20036	0	80000	100	20040	20040	20040	20040	20040
80204	20039	150	516	25	80100	100	80000	100	80000	500	640000	0	20020	20039	20039	9973	3	9997	80100	200	80000	200	160000	20039	20039	1	1	80201	100	99	100	100	80000	100	0	0	5110	1	16	1	1	20036	0	80000	100	20040	20040	20040	20040	20040
80204	20039	150	41	25	80100	100	80000	123	80000	500	640000	1	20020	20039	20039	9973	3	9997	80100	200	80000	200	160000	20039	20039	1	1	80201	100	99	100	100	80000	100	0	30	5110	1	16	1	1	20036	0	80000	100	20040	20040	20040	20040	20040
80204	20039	150	41	25	80100	100	80000	100	80000	500	640000	0	20020	20039	20039	9973	3	9997	80100	200	80000	200	160000	20039	20039	1	1	80201	100	99	100	100	80000	100	0	0	5110	1	16	1	1	20036	0	80000	100	20040	20040	20040	20040	20040
80204	20039	150	41	25	80100	100	80000	100	80000	500	640000	1	20020	20039	20039	9973	3	9997	80100	200	80000	200	160000	20039	20039	1	1	80201	100	99	100	100	80000	100	0	0	5110	1	16	1	1	20036	0	80000	100	20040	20040	20040	20040	20040
80204	20039	150	41	25	80100	100	80000	100	80000	500	640000	1	20020	20039	20039	9973	3	9997	80100	200	80000	200	160000	20039	20039	1	1	80201	100	99	100	100	80000	100	0	0	5110	1	16	1	1	20036	0	80000	100	20040	20040	20040	20040	20040
80204	20039	150	41	25	80100	100	80000	100	80000	500	640000	0	20020	20039	20039	9973	3	9997	80100	200	80000	200	160000	20039	20039	1	1	80201	100	99	100	100	80000	100	0	0	5110	1	16	1	1	20036	0	80000	100	20040	20040	20040	20040	20040

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2505

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	5f	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
80024	20048	150	0	40	25	80010	10	80000	10	80000	50	640000	0	1	20020	20039	20039	9996	3	10019	80010	20	80000	20	160000	20039	20039	1	1	80021	10	9	10	10	80000	10	0	35	0	0	5020	20	16	7	7	20036	80000	10	20040	20040	20040	20040	20040
80024	20039	150	0	40	25	80010	10	80000	10	80000	50	640000	0	0	20020	20039	20039	9996	3	10019	80010	20	80000	20	160000	20039	20039	1	1	80021	10	9	10	10	80000	10	0	38	0	3	5020	6	16	5	7	20036	80000	10	20040	20040	20040	20040	20040
80024	20039	150	0	325	25	80010	10	80000	10	80000	50	640000	0	0	20020	20039	20039	9996	3	10019	80010	20	80000	20	160000	20039	20039	1	1	80021	10	9	10	10	80000	10	0	0	0	0	5020	7	16	5	8	20036	80000	10	20040	20040	20040	20040	20040
80024	20039	150	0	40	25	80010	10	80000	10	80000	50	640000	0	0	20020	20039	20039	9996	3	10019	80010	20	80000	20	160000	20039	20039	1	1	80021	10	9	10	10	80000	10	0	0	0	0	5020	6	16	7	5	20036	80000	10	20040	20040	20040	20040	20040
80024	20039	150	0	40	25	80010	10	80000	10	80000	50	640000	0	0	20020	20039	20039	9996	3	10019	80010	20	80000	20	160000	20039	20039	1	1	80021	10	9	10	10	80000	10	0	0	0	0	5020	8	16	7	8	20036	80000	10	20040	20040	20040	20040	20040
80024	20039	150	0	155	25	80010	10	80000	10	80000	50	640000	0	0	20020	20039	20039	9996	3	10019	80010	20	80000	20	160000	20039	20039	1	1	80021	10	9	10	10	80000	10	0	1	0	18	5020	6	16	8	6	20036	80000	10	20040	20040	20040	20040	20040
80024	20039	150	0	40	25	80010	10	80000	10	80000	50	640000	0	0	20020	20039	20039	9996	3	10019	80010	20	80000	20	160000	20039	20039	1	1	80021	10	9	10	10	80000	10	0	0	0	0	5020	8	16	9	6	20036	80000	10	20040	20040	20040	20040	20040
80024	20039	150	0	40	25	80010	10	80000	10	80000	50	640000	0	0	20020	20039	20039	9996	3	10019	80010	20	80000	20	160000	20039	20039	1	1	80021	10	9	10	10	80000	10	0	58	0	3	5020	11	16	8	4	20036	80000	10	20040	20040	20040	20040	20040
80024	20039	150	0	40	25	80010	10	80000	10	80000	50	640000	0	1	20020	20039	20039	9996	3	10019	80010	20	80000	20	160000	20039	20039	1	1	80021	10	9	10	10	80000	10	0	23	0	3	5020	7	16	7	5	20036	80000	10	20040	20040	20040	20040	20040
80024	20039	150	0	40	25	80010	10	80000	10	80000	50	640000	0	0	20020	20039	20039	9996	3	10019	80010	20	80000	20	160000	20039	20039	1	1	80021	10	9	10	10	80000	10	0	43	0	90	5020	8	16	5	8	20036	80000	10	20040	20040	20040	20040	20040

MUL (by element, 8H)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->2

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: Latency 1->3

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 4: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations