Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

MUL (vector, 4H)

Test 1: uops

Code:

  mul v0.4h, v0.4h, v1.4h
  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

retire uop (01)cycle (02)03mmu table walk data (08)181e1f3f4e51schedule uop (52)schedule simd uop (54)dispatch simd uop (57)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map simd uop (7e)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst simd alu (9a)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)f5f6f7f8fd
100430372400006125482510001000100039831313018303730372415328951000100020003037303711100110000073116112630100030383038303830383038
100430372300006125482510001000100039831313018303730372415328951000100020003037303711100110000673116112630100030383038303830383038
100430372200006125482510001000100039831313018303730372415328951000100020003037303711100110001073116112630100030383038303830383038
100430372300006125482510001000100039831313018303730372415328951000100020003037303711100110000073116112630100030383038303830383038
1004303723009012825482510001000114939831313018303730372415328951000100020003037303711100110000073140112630100030383038303830383038
100430372300006125482510001000100039831313018303730372415328951000100020003037303711100110000073116112630100030383038303830383038
1004303722001206125482510001000100039831313018303730372415328951000100020003037303711100110001073116112630100030383038303830383038
100430372201906125482510081000100039831313018303730372415328951000100020003037303711100110001073116112646100030383038303830383038
100430372200006125482510001000100039831313018303730372415328951000100020003037303711100110000073116112630100030383038303830383038
100430372200006125482510001000100039831313018303730372415328951000100020003037303711100110000073116112630100030383038303830383038

Test 2: Latency 1->2

Code:

  mul v0.4h, v0.4h, v1.4h
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)03l2 tlb miss instruction (0a)191e1f3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
1020430037225000014729548251010010010000100100005004277313130018300373003728265328733101002001000020020000300373003711102011009910010010000100007102162229634100001003003830038300383003830038
102043003722500008229548251010010010000100100005004277313130018300373003728265328745101002001000020020000300373003711102011009910010010000100007102162229634100001003003830038300383003830038
1020430037224010021029548251010010010000100100005004277313130018300373003728265328745101002001000020020000300373003711102011009910010010000100007102162229634100001003003830038300383003830038
1020430037225000019329548251010010010000100100005004277313130018300373003728265328745101002001000020020000300373003711102011009910010010000100007102162229634100001003003830038300383003830038
1020430037224000014729548251010010010000100100005004277313130018300373003728265328745101002001000020020000300373003711102011009910010010000100007102162229634100001003003830038300383003830038
102043003722500006129548251010010010000100100005004277313130018300373003728265328745101002001000020020000300843003711102011009910010010000100007102162229634100001003003830038300383003830038
1020430037225000012429548251010010010000100100005004277313130018300373003728265328745101002001000020020000300373003711102011009910010010000100007102162229634100001003003830038300383003830038
102043003722500006129548251010010010000100100005004277313130018300373003728265328745101002001000020020000300373003711102011009910010010000100007102162229634100001003003830038300383003830038
1020430037225000012429548251010010010000100100005004277313130018300373003728265328745101002001000020020000300373003711102011009910010010000100007102162229634100001003003830038300383008330038
1020430037225000012429548251010010010000100100005004277313130018300373003728265328745101002001000020020000300373003711102011009910010010000100007102162229634100001003003830038300383003830038

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)03mmu table walk data (08)1e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)acc2cfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
1002430037224004282954825100101010000101000050427731303001830037300372828732876710010201000020200003003730037111002110910101000010000640216222963010000103003830038300383003830038
10024300372250011622954825100101010000101000050427731313001830037300372828732876710010201000020200003003730037111002110910101000010000640216222963010000103003830038300383003830038
100243003722500612954825100101010000101000050427731303001830037300372828732876710010201000020200003003730037111002110910101000010000640216222963010000103003830038300383003830038
1002430037225001662954825100101010000101000050427731303001830037300372828732876710010201000020200003003730037111002110910101000010000640216222963010000103003830038300383003830038
1002430037225006412954825100101010000101000050427731303001830037300372828732876710010201000020200003003730037111002110910101000010000640217222963010000103003830038300383003830038
100243003722500612954825100101010000101000050427731303001830037300372828732876710010201000020200003003730037111002110910101000010000640216222963010000103003830038300383003830038
1002430037225001662954825100101010000101000050427731303001830037300372828732876710010201000020200003003730037111002110910101000010000640216222963010000103003830038300383003830038
1002430037224001242954825100101010000101000050427731303001830037300372828732876710010201000020200003003730037111002110910101000010000640216222963010000103003830038300383003830038
100243003722500822954825100101010000101000050427731303001830037300372828732876710010201000020200003003730037111002110910101000010000640216222963010000103003830038300383003830038
1002430037225001662954825100101010000101000050427731303001830037300372828732876710010201000020200003003730037111002110910101000010000640216222963010000103003830038300383003830038

Test 3: Latency 1->3

Code:

  mul v0.4h, v1.4h, v0.4h
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)03mmu table walk data (08)18191e1f3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)ld unit uop (a6)st unit uop (a7)l1d cache writeback (a8)a9acc2cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
102043003722500000145329548251010010010000100100005004277313030018300373003728265328745101002001000020020000300373003711102011009910010010000100000000071011611296340100001003003830038300383003830038
1020430037225000006129548251010010010000100100005004277313030018300373003728265328745101002001000020020000300373003711102011009910010010000100000000071011611296340100001003003830038300383003830038
1020430037224000006129548251010010010000100100005004277313030018300373003728265828745101002001000020020330300373003711102011009910010010000100000000071012511296340100001003003830038300383003830038
10204300372250007925284032294851651018713710056137110436144286812030270303583038128289312886911182228111602222202430371303728110201100991001001000010020112196684858295132988636100001003037030425303733037230370
10204303702270779276165320294761661020114510056135110437034286905030270303683037028291382886711333218110142262233430405303758110201100991001001000010003012195700710116112963410100001003042030372303703037230323
102043003722510000450329485178101921431005613611043714428677503027030410303742829336288911133822711158230226563046630502101102011009910010010000100000020071011611296340100001003003830038300383003830038
1020430037225000006129548251010010010000100100005004277313030018300373003728265328745101002001000020020000300373003711102011009910010010000100000000071011611296340100001003003830038300383003830038
1020430037225000006129548251010010010000100100005004277313030018300373003728265328745101002001000020020000300373003711102011009910010010000100000000071011611296340100001003003830038300383003830038
1020430037225000006129548451010010010000100100005004277313030018300373003728265328745101002001000020020000300373003711102011009910010010000100000000071011611296340100001003003830038300383003830038
1020430037225000006129548251010010010000100100005004277313030018300373003728265328745101002001000020020000300373003711102011009910010010000100000000071011611296340100001003003830038300383003830038

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)03l2 tlb miss data (0b)1e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb miss (a1)ld unit uop (a6)l1d cache writeback (a8)a9branch cond mispred nonspec (c5)cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
1002430037225091872954825100101010000101000050427731313001830037300372828732876710010201000020200003003730037111002110910101000010000006402162229630010000103003830038300383003830038
100243003722400612954825100101010000101000050427731313001830037300372828732876710010201000020200003003730037111002110910101000010000006402162229630010000103003830038300383003830038
100243003722500612954825100101010000101000050427731313001830037300372828732876710010201000020200003003730037111002110910101000010000006402162229630010000103003830038300383003830038
100243003722500612954825100101010000101000050427731313001830037300372828732876710010201000020200003003730037111002110910101000010000006402162329630010000103003830038300383003830038
100243003722500612954825100101010000101000050427731313001830037300372828732876710010201000020200003003730037111002110910101000010000006402162329630010000103003830038300383003830038
100243003722500662954825100101010000101000050427731313001830037300372828732876710010201000020200003003730037111002110910101000010000006402162229630010000103003830038300383003830038
100243003722500612954825100101010000101000050427731313001830037300372828732876710010201000020200003003730037111002110910101000010000006402162229630010000103003830038300383003830038
10024300372250561822953025100101010000101000050427731303001830037300372828732876710010201000020200003003730037111002110910101000010000006402162329630010000103003830038300383003830038
100243003722400612954825100101010000101000050427731313001830037300372828732876710010201000020200003003730037111002110910101000010000006402162229630010000103003830038300383003830038
100243003722500612954825100101010000101000050427731313001830037300372828732876710010201000020200003003730037111002110910101000010000006402162229630010000103003830038300383003830038

Test 4: throughput

Count: 8

Code:

  mul v0.4h, v8.4h, v9.4h
  mul v1.4h, v8.4h, v9.4h
  mul v2.4h, v8.4h, v9.4h
  mul v3.4h, v8.4h, v9.4h
  mul v4.4h, v8.4h, v9.4h
  mul v5.4h, v8.4h, v9.4h
  mul v6.4h, v8.4h, v9.4h
  mul v7.4h, v8.4h, v9.4h
  movi v8.16b, 9
  movi v9.16b, 10

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)03mmu table walk data (08)18191e1f3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)ld unit uop (a6)a9acc2branch cond mispred nonspec (c5)cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
80204200601500000041258010010080000100800005006400002002020039200399973399978010020080000200160000200392003911802011009910010080000100000000511031611200360800001002004020040200402004020040
80204200391500000041258010010080000100800005006400002002020039200399973399978010020080000200160000200392003911802011009910010080000100000000511011611200360800001002004020040200402004020040
80204200391500000041258010010080000100800005006400002002020039200399973399978010020080000200160000200392003911802011009910010080000100000000511011611200360800001002004020040200402004020040
80204200391500000041258010010080000100800005006400002002020039200399973399978010020080000200160000200392003911802011009910010080000100000000511011611200360800001002004020040200402004020040
80204200391500000041258010010080000100800005006400002002020039200399973399978010020080000200160000200392003911802011009910010080000100000000511011611200360800001002004020040200402004020040
802042003915000012041258010010080000100800005006400002002020039200399973399978010020080000200160000200392003941802011009910010080000100000000511011611200360800001002004020040200402004020040
802042003915000000412580100100800001008000050064000020020200392003999733999780100200800002001600002003920039118020110099100100800001000000005110116112003612800001002004020040200402004020040
802042003915000000125258010010080000100800005006400002002020039200399973399978010020080000200160000200392003911802011009910010080000100000000511011611200360800001002004020040200402004020040
802042003915000000104258010010080000100800005006400002002020039200399973399978010020080000200160000200392003911802011009910010080000100000000511011611200360800001002004020040200402004020040
80204200391500000041258010010080000100800005006400002002020039200399973399978010020080000200160000200392003911802011009910010080000100000300511011611200360800001002004020040200402004020040

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)03mmu table walk instruction (07)18191e1f3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)simd prf full (72)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d cache writeback (a8)a9accfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
8002420040150000604025800101080000108000050640000120020200392003999960310019800102080000201600002003920039118002110910108000010000050207167520036080000102004020040200402004020040
800242003915000000402580010108000010800005064000002002020039200399996031001980010208000020160000200392003911800211091010800001000058050207167520036080000102004020040200402004020040
800242003915010096040258001010800001080000506400001200202003920039999603100198001020800002016000020039200391180021109101080000100000502051671120036080000102004020040200402004020040
80024200391500000014725800101080000108000050640000020020200392003999960310019800102080000201600002003920039118002110910108000010000050207167520036080000102004020040200402004020040
8002420039150000004025800101080000108000050640000020020200392003999960310019800102080000201600002003920039118002110910108000010000050205167520036080000102004020040200402004020040
80024200391500001804025800101080000108000050640000020020200392003999960310019800122080000201600002003920039118002110910108000010000050205165720036080000102004020040200402004020040
8002420039150000004025800101080000108000050640000020020200392003999960310019800102080000201600002003920039118002110910108000010000050205167520036080000102004020040200402004020040
8002420039150000004025800101080000128000060640000020020200392003999960310019800122080000201600002003920039118002110910108000010000050207165720036080000102004020040200402004020040
8002420039150000004025800101080000108000050640000020020200392003999960310019800102080000201600002003920039118002110910108000010000050205167720036080000102004020040200402004020040
8002420039150000004025800101080000108000050640000120020200392003999960310019800102080000201600002003920039118002110910108000010000050207167620036080000102004020040200402004020040