Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

MUL (vector, 4S)

Test 1: uops

Code:

  mul v0.4s, v0.4s, v1.4s
  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

retire uop (01)cycle (02)031e3f4e51schedule uop (52)schedule simd uop (54)dispatch simd uop (57)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map simd uop (7e)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst simd alu (9a)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)f5f6f7f8fd
100430372306125482510001000100039831313018303730372415328951000100020003037303711100110000073116112630100030383038303830383038
100430372306125482510001000100039831313018303730372415328951000100020003037303711100110000073116112630100030383038303830383038
100430372206125482510001000100039831313018303730372415328951000100020003037303711100110000073116112630100030383038303830383038
100430372306125482510001000100039831313018303730372415328951000100020003037303711100110000073116112630100030383038303830383038
100430372406125482510001000100039831313018303730372415328951000100020003037303711100110000073116112630100030383038303830383038
100430852306125482510001000100039831313018303730372415328951000100020003037303711100110000073116112630100030383038303830383038
1004303722015625482510001000100039831313018303730372415328951000100020003037303711100110000073116112630100030383038303830383038
1004303723029125482510001000100039831313018303730372415328951000100020003037303711100110000373116112630100030383038303830383038
100430372306125482510001000100039831313018303730372415328951000100020003037303711100110000073116112630100030383038303830383038
100430372206125482510001000100039831313018303730372415328951000100020003037303711100110000073116112630100030383038303830383038

Test 2: Latency 1->2

Code:

  mul v0.4s, v0.4s, v1.4s
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)03mmu table walk data (08)l2 tlb miss data (0b)181e1f3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb miss (a1)l1d cache writeback (a8)acc2cfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
102043003722500000612954825101001001000010010000500427731313001830037300372826532874510100200100002002000030037300371110201100991001001000010000007101161129634100001003003830038300383003830038
1020430037225000001452954825101001001000010010000500427731313001830037300372826532874510100200100002002000030037300371110201100991001001000010000007101161129634100001003003830038300383003830038
1020430037225000001262954825101001001000010010000500427731313001830037300372826532874510100200100002002000030037300372110201100991001001000010001007101161129634100001003003830038300383003830038
1020430037225000001872954825101001001000010010000500427731313001830037300372826532874510100200100002002000030037300371110201100991001001000010000007101161129634100001003003830038300383003830038
1020430037225000001662954825101001001000010010000500427731313001830037300372826532874510100200100002002000030037300371110201100991001001000010000007101161129634100001003003830038300383003830038
1020430037224000001452953925101001001000010010000500427731313001830037300372826532874510100200100002002000030037300371110201100991001001000010000007101161129634100001003003830038300383003830038
1020430037225000001242954825101001001000010010000500427731313001830037300372826532874510100200100002002000030037300371110201100991001001000010000007511161129634100001003003830038300383003830038
1020430037225000001702954825101001001000010010000500427731313001830037300372826532874510100200100002002000030037300371110201100991001001000010000007101161129634100001003003830038300383003830038
1020430037225010001662954825101001001000010010000500427731313001830037300372826532874510100200100002002000030037300371110201100991001001000010000007101161129634100001003003830038300383003830038
1020430037225000001282954825101001001000010010000500427731313001830037300372826532874510100200100002002000030037300371110201100991001001000010000007101161129634100001003003830038300383003830038

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)03mmu table walk data (08)l2 tlb miss data (0b)18191e1f3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d tlb miss (a1)ld unit uop (a6)l1d cache writeback (a8)a9acc2branch cond mispred nonspec (c5)cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
100243003722500002406752954825100101010000101000050427731303001830037300372828732876710010201000020200003003730037111002110910101000010000000006403164329630010000103003830038300383003830038
10024300372250000001242953925100101010000101000050427731313001830037300372828732876710010201000020200003003730037111002110910101000010000000006403163329630010000103003830038300383003830038
10024300372250000001242954825100101010000101000050427731303001830037300372828732876710010201000020200003003730037111002110910101000010000000006403163329630010000103003830038300383003830038
10024300372250000001492954825100101010000101000050427731303001830037300372828732876710010201000020200003003730037111002110910101000010000000006403163329630010000103003830038300383003830038
10024300372240000001892954825100101010000101000050427731313001830037300372828732876710010201000020200003003730037111002110910101000010000000006403163329630010000103003830038300383003830038
100243003722500000056562954825100101010000101000050427731303001830037300372828732876710010201000020200003003730037111002110910101000010000000006403163329630010000103003830038300383003830038
10024300372250000001032954825100101010000101000050427731303001830037300372828732876710010201000020200003003730037111002110910101000010000000006403163329630010000103003830038300383003830038
10024300372250000001242954825100101010000101000050427731303001830037300372828732876710010201000020200003003730037111002110910101000010000000006403163329630010000103003830038300383003830038
10024300372250000001242954825100101010000101000050427731303001830037300842828732876710010201000020200003003730037111002110910101000010000000006403163329630010000103003830038300383003830038
10024300372240000001662954825100101010000101000050427731303001830037300372829932876710010201000020200003003730037111002110910101000010000000006403163329630010000103003830038300383003830038

Test 3: Latency 1->3

Code:

  mul v0.4s, v1.4s, v0.4s
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)03181e3a3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)6061696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9faccdcfd0d5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
102043003722500057029548251010010010000100100005004277313133001830037300372826532874510100200100002002000030037300371110201100991001001000010000710311611296340100001003003830038300383003830038
102043003722500061295482510100100100001001000050042773131030018300373003728265328745101002001000020020000300373003711102011009910010010000100007103116112963423100001003003830038300383003830038
102043003722500016629548251010010010000100100005004277313103001830037300372826532874510100200100002002000030037300371110201100991001001000010000710311611296340100001003003830038300383003830038
102043003722500010329548251010010010000100100005004277313033001830037300372826532874510100200100002002000030037300371110201100991001001000010000710311611296340100001003003830038300383003830038
102043003722500012429548251010010010000100100005004277313133001830037300372826532874510100200100002002000030037300371110201100991001001000010000710301611296340100001003003830038300383003830038
1020430037225054012429548251010010010000100100005004277313103001830037300372826532874510100200100002002000030037300371110201100991001001000010000710011611296340100001003003830038300383003830038
10204300372250008229548251010010010000100100005004277313103001830037300372826532874510100200100002002000030037300371110201100991001001000010000710011611296340100001003003830038300383003830038
102043003722500010329548251010010010000100100005004277313003001830037300372826532874510100200100002002000030037300371110201100991001001000010000710011611296340100001003003830038300383003830038
102043003722500012429548251010010010000100100005004277313003001830037300372826532874510100200100002002000030037300371110201100991001001000010000710011611296340100001003003830038300383003830038
102043003722500016629548251010010010000100100005004277313103001830037300372826532874510100200100002002000030037300371110201100991001001000010000710011611296340100001003003830038300383003830038

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)03l2 tlb miss data (0b)18191e1f3a3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb miss (a1)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
100243003722400000018929548251001010100001010000504277313130018300373003728287328767100102010000202000030037300371110021109101010000100006402162329630010000103003830038300383003830038
100243003722500000044929548251001010100001010000504277313130018300373003728287328767100102010000202000030037300371110021109101010000100006402162329630010000103003830038300383003830038
10024300372250000006129548251001010100001010000504277313130018300373003728287328767100102010000202000030037300371110021109101010000100006402162329630010000103003830038300383003830038
100243003722500000016829539441001010100001010000504277313030018300373003728287328767100102010000202000030037300371110021109101010000100106402162329668010000103003830038300383003830038
10024300372250000008229548251001010100001010000504277313130018300373003728287328767100102010000202000030037300371110021109101010000100136402162229630010000103003830038300383003830038
100243003722500000018729548251001010100001010000504277313030018300373003728287328767100102010000202000030080300371110021109101010000100006402162229630010000103003830038300383003830038
10024300372250009006129548251001010100001010000504277313130018300373003728287328767100102010000202000030037300371110021109101010000100006402162229737010000103003830038300383003830038
100243003722510000025229548251001010100001010000504277313130018300373003728287328767100102010000202000030037300371110021109101010000100006402162329630010000103003830038300383003830038
100243003722500012006129548251001010100001010000504277313030018300373003728287328767100102010000202000030037300371110021109101010000100006402162329630010000103003830038300383003830038
10024300852250000006129548251001010100001010000504277313130018300373003728287328767100102010000202000030037300371110021109101010000100006402162329630010000103003830038300383003830038

Test 4: throughput

Count: 8

Code:

  mul v0.4s, v8.4s, v9.4s
  mul v1.4s, v8.4s, v9.4s
  mul v2.4s, v8.4s, v9.4s
  mul v3.4s, v8.4s, v9.4s
  mul v4.4s, v8.4s, v9.4s
  mul v5.4s, v8.4s, v9.4s
  mul v6.4s, v8.4s, v9.4s
  mul v7.4s, v8.4s, v9.4s
  movi v8.16b, 9
  movi v9.16b, 10

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)03mmu table walk data (08)l2 tlb miss data (0b)181e3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fld unit uop (a6)l1d cache writeback (a8)acc2cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
80204200391500000642580100100800001008000050064000020020200392003999733999780100200800002001600002003920039118020110099100100800001000000511031611200360800001002004020040200402004020040
802042003915000001502580100100800001008000050064000020020200392003999733999780100200800002001600002003920039118020110099100100800001000000511011612200360800001002004020040200402004020040
80204200391500000852580100100800001008000050064000020020200392003999733999780100200800002001600002003920039118020110099100100800001000000511011611200360800001002004020040200402004020040
802042003915000004125801001008000010080000500640000200202003920039997339997801002008000020016000020039200391180201100991001008000010000005110116122003618800001002004020040200402004020040
80204200911510000622580100100800001008000050064000020020200392011599823999780100200800002001600002003920039118020110099100100800001000000511011612200360800001002004020040200402004020040
802042003915000001062580100100800001008000050064000020020200392003999733999780100200800002001600002003920039118020110099100100800001000000511011611200360800001002004020040200402004020040
80204200391500000852580100100800001008000050064000020020200392003999733999780100200800002001600002003920039118020110099100100800001000000511011611200360800001002004020040200402004020040
802042003915000001312580100100800001008000050064000020020200392003999733999780100200800002001600002003920039118020110099100100800001000000511011612200360800001002004020040200402004020040
80204200391500000642580100100800001008000050064000020020200392003999733999780100200800002001600002003920039118020110099100100800001000000511011612200360800001002004020040200402004020040
80204200391500000412580100100800001008000050064000020020200392003999733999780100200800002001600002003920039118020110099100100800001000000511011611200360800001002004020040200402004020040

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)033f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)5f60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fcfd0d2d5map dispatch bubble (d6)d9ddfetch restart (de)e0eb? simd retires (ee)? int retires (ef)f5f6f7f8fd
80024200981501452580010108000010800005064000000200202003920039999631001980010208000020160000200392003911800211091010800001050200011601120036080000102004020040200402004020040
8002420039150402580010108000010800005064000000200202003920039999631001980010208000020160000200392003911800211091010800001050200011601220036080000102004020040200402004020040
8002420039150402580010108000010800005064000000200202003920039999631001980010208000020160000200392003911800211091010800001050200011601120036080000102004020040200402004020040
8002420039150402580010108000010800005064000000200202003920039999631001980010208000020160000200392003911800211091010800001050200011602120036080000102004020040200402004020040
8002420039150402580010108000010800005064000000200202003920039999631001980010208000020160000200392003911800211091010800001050200011601220036080000102004020040200402004020040
800242003915010525800101080000108000050640000002002020039200391000531001980010208000020160000200392003911800211091010800001050200011601120036080000102004020040200402004020040
80024200391501282580010108000010800005064000000200202003920039999631001980010208000020160000200392003911800211091010800001050200011601120036080000102004020040200402004020040
80024200391502995080010108000010800005064000000200202003920039999631001980010208000020160000200392003911800211091010800001050200011601120036080000102004020040200402004020040
8002420039150402580010108000010800005064000000200202003920039999631001980010208000020160000200392003911800211091010800001050200011601120036080000102004020040200402004020040
8002420039150402580010108000010800005064000000200202003920039999631001980010208000020160000200392003911800211091010800001050200011601120036080000102004020040200402004020040