Firestorm: MVNI (vector, 2S, msl) measurements

Code:

  mvni v0.2s, #3, msl #8

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	51	schedule uop (52)	schedule simd uop (54)	dispatch simd uop (57)	ldst uops in schedulers (5b)	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map simd uop (7e)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst simd alu (9a)	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	f5	f6	f7	f8	fd
1004	288	2	0	40	25	1000	1000	1000	7000	269	288	288	123	3	146	1000	1000	288	288	1	1	1001	1000	0	0	73	1	16	1	1	285	1000	289	289	289	289	289
1004	288	2	0	40	25	1000	1000	1000	7000	269	288	288	123	3	146	1000	1000	288	288	1	1	1001	1000	0	0	73	1	16	1	1	285	1000	289	289	289	289	289
1004	288	2	0	40	25	1000	1000	1000	7000	269	288	288	123	3	146	1000	1000	288	288	1	1	1001	1000	0	0	73	1	16	1	1	285	1000	289	289	289	289	289
1004	288	2	0	40	25	1000	1000	1000	7000	269	288	288	123	3	146	1000	1000	288	288	1	1	1001	1000	0	0	73	1	16	1	1	285	1000	289	289	289	289	289
1004	288	2	0	40	25	1000	1000	1000	7000	269	288	288	123	3	146	1000	1000	288	288	1	1	1001	1000	0	0	73	1	16	1	1	285	1000	289	289	289	289	289
1004	288	2	6	40	25	1000	1000	1000	7000	269	288	288	123	3	146	1000	1000	288	288	1	1	1001	1000	0	0	73	1	16	1	1	285	1000	289	289	289	289	289
1004	288	2	0	40	25	1000	1000	1000	7000	269	288	288	123	3	146	1000	1000	288	288	1	1	1001	1000	0	0	73	1	16	1	1	285	1000	289	289	289	289	289
1004	288	2	0	40	25	1000	1000	1000	7000	269	288	288	123	3	146	1000	1000	288	288	1	1	1001	1000	0	0	73	1	16	1	1	285	1000	289	289	289	289	289
1004	288	2	0	82	25	1000	1000	1000	7000	269	288	288	123	3	146	1000	1000	288	288	1	1	1001	1000	0	0	73	1	16	1	1	285	1000	289	289	289	289	289
1004	288	2	0	40	25	1000	1000	1000	7000	269	288	288	123	3	146	1000	1000	288	288	1	1	1001	1000	0	0	73	1	16	1	1	285	1000	289	289	289	289	289

Count: 8

Code:

  mvni v0.2s, #3, msl #8
  mvni v1.2s, #3, msl #8
  mvni v2.2s, #3, msl #8
  mvni v3.2s, #3, msl #8
  mvni v4.2s, #3, msl #8
  mvni v5.2s, #3, msl #8
  mvni v6.2s, #3, msl #8
  mvni v7.2s, #3, msl #8

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2505

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk instruction (07)	mmu table walk data (08)	l2 tlb miss data (0b)	18	19	1e	1f	3a	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
80204	20038	155	0	0	0	0	0	0	0	0	591	25	80100	100	80000	100	80000	500	560000	20019	20038	20038	9973	3	9996	80100	200	80000	200	20038	20038	1	1	80201	100	99	100	100	80000	100	0	0	0	0	0	5110	3	16	2	2	20035	0	80000	100	20039	20039	20039	20039	20039
80204	20038	155	0	0	0	0	0	0	0	0	811	25	80100	100	80000	100	80000	500	560000	20019	20038	20038	9973	3	9996	80100	200	80000	200	20038	20038	1	1	80201	100	99	100	100	80000	100	0	0	0	0	0	5110	2	16	2	2	20035	0	80000	100	20039	20039	20039	20039	20039
80204	20038	156	0	0	0	0	0	0	0	0	40	25	80100	100	80084	100	80000	500	560000	20019	20038	20038	9973	3	9996	80100	200	80000	200	20038	20038	1	1	80201	100	99	100	100	80000	100	0	20	0	0	0	5110	2	16	2	2	20035	0	80000	100	20039	20039	20039	20039	20039
80204	20038	155	0	0	0	0	0	0	0	0	168	25	80100	100	80000	100	80000	500	560000	20019	20038	20038	9973	3	9996	80100	200	80000	200	20038	20038	1	1	80201	100	99	100	100	80000	100	0	0	0	0	0	5110	2	16	2	2	20035	0	80000	100	20039	20039	20039	20039	20039
80204	20038	155	0	0	0	0	0	0	0	0	105	25	80100	100	80000	100	80000	500	560000	20019	20038	20038	9973	3	9996	80100	200	80000	200	20038	20038	1	1	80201	100	99	100	100	80000	100	0	1	0	0	0	5110	2	16	2	2	20035	0	80000	100	20039	20039	20039	20039	20039
80204	20038	155	0	0	0	0	0	0	0	0	55	25	80100	100	80000	100	80000	500	560000	20019	20038	20038	9973	6	10022	80100	200	80000	200	20038	20038	1	1	80201	100	99	100	100	80000	100	0	0	0	0	0	5127	2	16	1	2	20035	0	80000	100	20039	20039	20039	20039	20039
80204	20038	155	0	0	0	0	0	132	108	0	40	25	80100	100	80000	100	80000	500	560000	20019	20038	20038	9982	3	10021	80100	200	80000	200	20038	20038	1	1	80201	100	99	100	100	80000	100	0	0	0	0	0	5110	3	35	2	5	20193	21	80000	100	20343	20246	20241	20293	20194
80204	20343	158	0	1	0	5	4	663	440	0	2049	122	80685	121	80000	121	80488	586	564056	20215	20293	20291	10023	25	10154	80705	202	80199	200	20344	20291	7	1	80201	100	99	100	100	80000	100	0	1	0	2355	4	5189	2	71	2	3	20237	20	80000	100	20300	20298	20302	20287	20296
80204	20299	157	0	0	0	5	6	672	440	0	2104	141	80595	122	80468	118	80099	595	563375	20252	20292	20291	10026	27	10132	80709	200	80486	202	20285	20291	6	1	80201	100	99	100	100	80000	100	2	0	2	2810	0	5195	2	80	2	2	20238	21	80000	100	20346	20398	20303	20345	20393
80204	20356	156	3	1	0	6	6	1044	616	2	1960	159	80680	115	80466	126	80592	596	564108	20103	20396	20400	10040	34	10152	80705	200	80298	200	20398	20390	7	1	80201	100	99	100	100	80000	100	0	5	2	3040	9	5209	4	32	4	4	20282	22	80000	100	20189	20292	20191	20289	20194

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2505

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	5f	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	st unit uop (a7)	l1d cache writeback (a8)	ac	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	ea	eb	ec	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
80024	20040	155	0	39	25	80010	10	80000	10	80000	50	560000	0	0	20019	20038	20038	9996	3	10018	80010	20	80000	20	20038	20038	1	1	80021	10	9	10	10	80000	10	0	0	66	0	5020	8	16	17	6	20035	0	0	0	80000	10	20039	20039	20039	20039	20039
80024	20038	155	0	39	25	80010	10	80000	10	80000	50	560000	0	0	20019	20038	20038	9996	3	10018	80010	20	80000	20	20038	20038	1	1	80021	10	9	10	10	80000	10	0	0	84	0	5020	7	16	8	17	20035	0	0	0	80000	10	20039	20039	20039	20039	20039
80024	20038	155	0	39	25	80010	10	80000	10	80000	50	560000	0	0	20019	20038	20038	9996	3	10018	80010	20	80000	20	20038	20038	1	1	80021	10	9	10	10	80000	10	0	0	75	0	5020	17	16	17	8	20035	0	0	0	80000	10	20039	20039	20039	20039	20039
80024	20038	155	0	109	25	80010	10	80000	10	80000	50	560000	0	0	20019	20038	20038	9996	3	10018	80010	20	80000	20	20038	20038	1	1	80021	10	9	10	10	80000	10	0	0	72	0	5020	5	16	5	17	20035	0	0	0	80000	10	20039	20039	20039	20039	20039
80024	20038	155	0	67	25	80010	10	80000	10	80000	50	560000	0	1	20019	20038	20038	9996	3	10018	80010	20	80000	20	20038	20038	1	1	80021	10	9	10	10	80000	10	0	0	90	0	5020	7	16	17	8	20035	0	0	0	80000	10	20039	20039	20039	20039	20039
80024	20038	156	0	39	25	80010	10	80000	10	80000	56	560000	0	0	20019	20038	20038	9996	3	10018	80010	20	80000	20	20038	20038	1	1	80021	10	9	10	10	80000	10	0	0	96	0	5020	16	16	16	8	20035	0	0	0	80000	10	20039	20039	20039	20039	20039
80024	20038	161	0	39	25	80010	10	80000	10	80000	50	560000	0	0	20019	20038	20038	9996	3	10018	80010	20	80000	20	20038	20038	1	1	80021	10	9	10	10	80000	10	0	0	81	0	5020	17	16	14	17	20035	0	0	0	80000	10	20039	20039	20039	20039	20039
80024	20038	155	0	39	25	80010	10	80000	10	80000	50	560000	0	1	20019	20038	20038	9996	3	10018	80010	20	80000	20	20038	20038	1	1	80021	10	9	10	10	80000	10	0	0	6	0	5020	17	16	16	7	20035	0	0	0	80000	10	20039	20039	20039	20039	20039
80024	20038	155	0	39	25	80010	10	80000	10	80000	50	560000	0	0	20019	20038	20038	9996	3	10018	80010	20	80000	20	20038	20038	1	1	80021	10	9	10	10	80000	10	0	0	81	0	5020	17	16	16	17	20035	0	0	0	80000	10	20039	20039	20039	20039	20039
80024	20038	156	0	39	25	80010	10	80000	10	80000	50	560000	0	0	20019	20038	20038	9996	3	10018	80010	20	80000	20	20038	20038	1	1	80021	10	9	10	10	80000	10	0	0	3	0	5020	16	16	16	6	20035	0	0	0	80000	10	20039	20039	20039	20039	20039

MVNI (vector, 2S, msl)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations