Firestorm: MVNI (vector, 4S, msl) measurements

Code:

  mvni v0.4s, #3, msl #8

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	51	schedule uop (52)	schedule simd uop (54)	dispatch simd uop (57)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map simd uop (7e)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst simd alu (9a)	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	f5	f6	f7	f8	fd
1004	288	2	0	40	25	1000	1000	1000	7000	0	269	288	288	123	3	146	1000	1000	288	288	1	1	1001	1000	0	0	73	3	16	1	1	285	1000	289	289	289	289	289
1004	288	2	0	40	25	1000	1000	1000	7000	0	269	288	288	123	3	146	1000	1000	288	288	1	1	1001	1000	0	0	73	1	16	1	1	285	1000	289	289	289	289	289
1004	288	2	0	40	25	1000	1000	1000	7000	0	269	288	288	123	3	146	1000	1000	288	288	1	1	1001	1000	0	0	73	1	16	1	1	285	1000	289	289	289	289	289
1004	288	2	0	40	25	1000	1000	1000	7000	0	269	288	288	123	3	146	1000	1000	288	288	1	1	1001	1000	0	0	73	1	16	1	1	285	1000	289	289	289	289	289
1004	288	2	0	40	25	1000	1000	1000	7000	0	269	288	288	123	3	146	1000	1000	288	288	1	1	1001	1000	0	0	73	1	16	1	1	285	1000	289	289	289	289	289
1004	288	2	0	40	25	1000	1000	1000	7000	0	269	288	288	123	3	146	1000	1000	288	288	1	1	1001	1000	0	0	73	1	16	1	1	285	1000	289	289	289	289	289
1004	288	2	0	40	25	1000	1000	1000	7000	0	269	288	288	123	3	146	1000	1000	288	288	1	1	1001	1000	0	0	73	1	16	1	1	285	1000	289	289	289	289	289
1004	288	2	0	40	25	1000	1000	1000	7000	0	269	288	288	123	3	146	1000	1000	288	288	1	1	1001	1000	1	0	73	1	16	1	1	285	1000	289	289	289	289	289
1004	288	2	0	40	25	1000	1000	1000	7000	0	269	288	288	123	3	146	1000	1000	288	288	1	1	1001	1000	0	0	73	1	16	1	1	285	1000	289	289	289	289	289
1004	288	2	0	40	25	1000	1000	1000	7000	0	269	288	288	123	3	146	1000	1000	288	288	1	1	1001	1000	0	0	73	1	16	1	1	285	1000	289	289	289	289	289

Count: 8

Code:

  mvni v0.4s, #3, msl #8
  mvni v1.4s, #3, msl #8
  mvni v2.4s, #3, msl #8
  mvni v3.4s, #3, msl #8
  mvni v4.4s, #3, msl #8
  mvni v5.4s, #3, msl #8
  mvni v6.4s, #3, msl #8
  mvni v7.4s, #3, msl #8

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2505

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	ac	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
80204	20056	155	0	61	25	80100	100	80000	100	80000	500	560000	1	20019	20038	20038	9973	3	9996	80100	200	80000	200	20038	20038	1	1	80201	100	99	100	100	80000	100	0	0	5110	2	16	2	2	20035	80000	100	20039	20039	20039	20039	20039
80204	20038	156	0	40	25	80100	100	80000	100	80000	500	560000	1	20019	20038	20038	9973	3	9996	80100	200	80000	200	20038	20038	1	1	80201	100	99	100	100	80000	100	3	0	5110	2	16	2	2	20035	80000	100	20039	20039	20039	20039	20039
80204	20038	155	0	40	25	80100	100	80000	100	80000	500	560000	1	20019	20038	20038	9973	3	9996	80100	200	80000	200	20038	20038	1	1	80201	100	99	100	100	80000	100	0	0	5110	2	16	2	2	20035	80000	100	20039	20039	20039	20039	20039
80204	20038	156	0	82	25	80100	100	80000	100	80000	500	560000	1	20019	20038	20038	9973	3	9996	80100	200	80000	200	20038	20038	1	1	80201	100	99	100	100	80000	100	0	0	5110	2	16	2	2	20035	80000	100	20039	20039	20039	20039	20039
80204	20038	155	0	40	25	80100	100	80000	100	80000	500	560000	0	20019	20038	20038	9973	3	9996	80100	200	80000	200	20038	20038	1	1	80201	100	99	100	100	80000	100	0	0	5110	2	16	2	2	20035	80000	100	20039	20039	20039	20039	20039
80204	20038	155	0	40	25	80100	100	80000	100	80000	500	560000	0	20019	20038	20038	9973	3	9996	80100	200	80000	200	20038	20038	1	1	80201	100	99	100	100	80000	100	0	0	5110	2	16	2	2	20035	80000	100	20039	20039	20039	20039	20039
80204	20038	155	3	40	25	80100	100	80000	100	80000	500	560000	0	20019	20038	20038	9973	3	9996	80100	200	80000	200	20038	20038	1	1	80201	100	99	100	100	80000	100	0	0	5110	2	16	2	2	20035	80000	100	20039	20039	20039	20039	20039
80204	20038	155	0	40	25	80100	100	80000	100	80000	500	560000	1	20019	20038	20038	9973	3	9996	80100	200	80000	200	20038	20038	1	1	80201	100	99	100	100	80000	100	0	0	5110	2	16	2	2	20035	80000	100	20039	20039	20039	20039	20039
80204	20038	155	0	40	25	80100	100	80000	100	80000	500	560000	0	20019	20038	20038	9973	3	9996	80100	200	80000	200	20038	20038	1	1	80201	100	99	100	100	80000	100	0	0	5110	2	16	2	2	20035	80000	100	20039	20039	20039	20039	20039
80204	20038	155	0	126	25	80100	100	80000	100	80000	500	560000	1	20019	20038	20038	9973	3	9996	80100	200	80000	200	20038	20038	1	1	80201	100	99	100	100	80000	100	0	0	5110	2	16	2	2	20035	80000	100	20039	20039	20039	20039	20039

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2505

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l2 tlb miss data (0b)	19	1e	1f	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
80024	20039	156	0	0	0	0	608	25	80010	10	80000	10	80000	50	560000	1	20019	20038	20038	9996	3	10018	80010	20	80000	20	20038	20038	1	1	80021	10	9	10	10	80000	10	0	0	5020	5	16	4	5	20035	80000	10	20039	20039	20039	20039	20039
80024	20097	161	0	1	0	88	62	25	80010	10	80000	10	80000	50	560000	1	20019	20038	20038	9996	3	10018	80010	20	80000	20	20038	20038	1	1	80021	10	9	10	10	80000	10	1	0	5020	5	16	5	5	20035	80000	10	20039	20039	20039	20039	20039
80024	20038	155	0	0	0	0	39	25	80010	10	80000	10	80000	50	560000	1	20019	20038	20038	9996	3	10018	80010	20	80000	20	20038	20038	1	1	80021	10	9	10	10	80000	10	0	3	5020	6	16	7	5	20035	80000	10	20039	20039	20039	20039	20039
80024	20038	155	0	0	0	0	39	25	80010	10	80000	10	80000	50	560000	1	20019	20038	20038	9996	3	10018	80010	20	80000	20	20089	20038	1	1	80021	10	9	10	10	80000	10	0	0	5020	6	16	5	5	20035	80000	10	20039	20039	20039	20039	20039
80024	20038	155	0	0	0	0	618	25	80010	10	80000	10	80000	50	560000	1	20019	20038	20038	9996	3	10018	80010	20	80000	20	20038	20038	1	1	80021	10	9	10	10	80000	10	0	0	5020	6	16	5	5	20035	80000	10	20039	20039	20039	20039	20039
80024	20038	155	0	0	0	0	610	25	80010	10	80000	10	80000	50	560000	1	20019	20038	20038	9996	3	10018	80010	20	80000	20	20038	20038	1	1	80021	10	9	10	10	80000	10	0	0	5020	5	16	5	5	20035	80000	10	20039	20039	20039	20039	20039
80024	20038	156	0	0	0	0	104	25	80010	10	80000	10	80000	50	560000	1	20019	20038	20086	9996	3	10044	80111	20	80000	20	20038	20086	1	1	80021	10	9	10	10	80000	10	0	0	5040	6	16	5	6	20035	80000	10	20039	20039	20039	20039	20088
80024	20038	156	1	0	12	0	81	25	80010	10	80000	10	80000	50	560000	1	20019	20038	20038	9996	3	10018	80010	20	80000	20	20038	20038	1	1	80021	10	9	10	10	80000	10	0	0	5020	6	16	6	7	20035	80000	10	20039	20039	20039	20039	20039
80024	20038	155	0	0	0	0	317	25	80010	10	80000	10	80000	50	560000	1	20019	20038	20038	9996	3	10018	80010	20	80000	20	20038	20038	1	1	80021	10	9	10	10	80000	10	0	0	5020	6	16	6	5	20035	80000	10	20039	20039	20039	20039	20039
80024	20038	155	0	0	0	0	268	25	80010	10	80000	10	80000	50	560000	1	20019	20038	20038	9996	3	10018	80010	20	80000	20	20038	20038	1	1	80021	10	9	10	10	80000	10	0	0	5020	5	16	5	5	20035	80000	10	20039	20039	20039	20039	20039

MVNI (vector, 4S, msl)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations