Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

NEG (vector, 8H)

Test 1: uops

Code:

  neg v0.8h, v0.8h
  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

retire uop (01)cycle (02)03mmu table walk data (08)1e3f4e51schedule uop (52)schedule simd uop (54)dispatch simd uop (57)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map simd uop (7e)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst simd alu (9a)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)f5f6f7f8fd
100420371500611686251000100010002645211201820372037157131895100010001000203720371110011000073116111786100020382038203820382038
100420371500611686251000100010002645211201820372037157131895100010001000203720371110011000073116111786100020382038203820382038
100420371600611686251000100010002645211201820372037157131895100010001000203720371110011000073116111786100020382038203820382038
100420371500611686251000100010002645211201820372037157131895100010001000203720371110011000073116111786100020382038203820382038
100420371500611686251000100010002645211201820372037157131895100010001000203720371110011000073116111786100020382038203820382038
100420371500611686251000100010002645211201820372037157131895100010001000203720371110011000073116111786100020382038203820382038
100420371500611686251000100010002645211201820372037157131895100010001000203720371110011000073116111786100020382038203820382038
100420371500611686251000100010002645211201820372037157131895100010001000203720371110011000073116111786100020382038203820382038
100420371500611686251000100010002645211201820372037157131895100010001000203720371110011000073116111786100020382038203820382038
100420371510611686251000100010002645211201820372037157131895100010001000203720371110011000073116111786100020382038203820382038

Test 2: Latency 1->2

Code:

  neg v0.8h, v0.8h
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)031e1f3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
10204200371500061196862510100100100001001000050028475211200182003720037184213187451010020010000200100002003720037111020110099100100100001000607102162219791100001002003820038200382003820038
1020420037150006119686251010010010000100100005002847521020018200372003718421318745101002001000020010000200372003711102011009910010010000100007102162219791100001002003820038200382003820038
1020420037149006119686251010010010000100100005002847521020018200372003718421318745101002001000020010000200372003711102011009910010010000100007102162219791100001002003820038200382003820038
1020420037150006119686251010010010000100100005002847521020018200372003718421318745101002001000020010000200372003711102011009910010010000100007102162219791100001002003820038200382003820038
102042003715000611968625101001001000010010000500284752112001820037200371842131874510100200100002001000020037200371110201100991001001000010001627102162219791100001002003820038200382003820038
1020420037150006119686251010010010000100100005002847521120018200372003718421318745101002001000020010000200372003711102011009910010010000100007102162219791100001002003820038200382003820038
1020420037150006119686251010010010000100100005002847521120018200372003718421318745101002001000020010000200372003711102011009910010010000100007102162219791100001002003820038200382003820038
1020420037150006119686251010010010000100100005002847521120018200372003718421318745101002001000020010000200372003711102011009910010010000100007102162219791100001002003820038200382003820038
1020420037150006119686251010010010000100100005002847521120018200372003718421318745101002001000020010000200372003711102011009910010010000100007102162219791100001002003820038200382003820038
1020420037150006119686251010010010000100100005002847521120018200372003718421318745101002001000020010000200372003711102011009910010010000100007102162219791100001002003820038200382003820038

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)03mmu table walk data (08)l2 tlb miss data (0b)181e1f3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d tlb miss (a1)ld unit uop (a6)l1d cache writeback (a8)acc2cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
100242003715000021061196862510010101000010100005028475211200182003720037184433187671001020100002010000200372003711100211091010100001000052006403162219786010000102003820038200382003820038
1002420037150000906119686251001010100001010000502847521120018200372003718443318767100102010000201000020037200371110021109101010000100000006402162219786010000102003820038200382003820038
1002420037150000006119686251001010100001010000502847521120018200372003718443318767100102010000201000020037200371110021109101010000100000006402162219786010000102003820038200382003820038
1002420037150000006119686251001010100001010000502847521120018200372003718443318767100102010000201000020037200371110021109101010000100000006402162219786010000102003820038200382003820038
10024200371500000025119686251001010100001010000502847521120018200372008518443318767100102010000201000020037200371110021109101010000100000006402162219786010000102003820038200382003820038
1002420037150000006119686251001010100001010000502847521020018200372003718443318767100102010000201000020037200371110021109101010000100000006402162219786010000102003820038200382003820038
1002420037150000006119686251001010100001010000502847521120018200372003718443318767100102010000201000020037200371110021109101010000100000792306402162219786010000102003820038200382003820038
10024200371500000061196862510010101000010100005028475211200182003720037184433187671001020100002010000200372003711100211091010100001000055006402162219786010000102003820038200382003820038
100242003715000000611968625100101010000101000050284752102001820037200371844331876710010201000020100002003720037111002110910101000010000691506402162219786010000102003820038200382003820038
1002420037150000006119686251001010100001010000502847521120018200372003718443318767100102010000201000020037200371110021109101010000100000006402162219786010000102003820038200382003820038

Test 3: throughput

Count: 8

Code:

  neg v0.8h, v8.8h
  neg v1.8h, v8.8h
  neg v2.8h, v8.8h
  neg v3.8h, v8.8h
  neg v4.8h, v8.8h
  neg v5.8h, v8.8h
  neg v6.8h, v8.8h
  neg v7.8h, v8.8h
  movi v8.16b, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)03l2 tlb miss data (0b)181e3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fld unit uop (a6)l1d cache writeback (a8)a9acc2branch cond mispred nonspec (c5)branch mispred nonspec (cb)cdcfd5map dispatch bubble (d6)dde0? simd retires (ee)? int retires (ef)f5f6f7f8fd
8020420059150000504258010810080008100800205006401322001920038200389977699898012020080032200800322003820038118020110099100100800001000450001115118116020035800001002003920039200392003920039
8020420038150000292580108100800081008002050064013220019200382003899776998980120200800322008003220038200381180201100991001008000010000015601115118016020035800001002003920039200392003920039
80204200381500002925801081008000810080020500640132200192003820038997769989801202008003220080032200382003811802011009910010080000100000901115118016020079800001002003920039200392003920039
80204200381510002925801081008000810080020500640132200192003820038997769989801202008003220080032200382003811802011009910010080000100050601115118016020035800001002003920039200392003920039
802042003815000029258010810080008100800205006401322001920038200389977699898012020080032200800322003820038218020110099100100800001000430301115118016020035800001002003920039200392003920039
80204200381500002925801081008000810080020500640132200192003820038997769989801202008003220080032200382003811802011009910010080000100000001115118016020035800001002003920039200392003920039
8020420038150000292580108100800081008002050064013220019200382003899776998980120200800322008003220038200381180201100991001008000010000011101115118016020035800001002003920039200392003920039
80204200381500002925801081008000810080020500640132200192003820038997769989801202008003220080032200382003811802011009910010080000100000301115118016020035800001002003920039200392003920039
80204200381500002925801081008000810080020500640132200192003820038997769989801202008003220080032200382003811802011009910010080000100000001115118016020035800001002003920039200392003920039
80204200381500002925801081008000810080020500640132200192003820038997769989801202008003220080032200382003811802011009910010080000100000301115118016020035800001002003920039200392003920039

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)03mmu table walk data (08)l2 tlb miss instruction (0a)l2 tlb miss data (0b)191e1f3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d tlb miss (a1)ld unit uop (a6)l1d cache writeback (a8)a9accfd0d2d5map dispatch bubble (d6)d9dadbddfetch restart (de)e0eaeb? simd retires (ee)? int retires (ef)f5f6f7f8fd
80024200511500000003925800101080000108000050640000020019200382003899963100188001020800002080000200382003811800211091010800001000020050200022160002514200350080000102003920039200392003920039
80024200381500100003925800101080000108000050640000020019200382009099963100188001020800002080000200382003811800211091010800001000020050200021160002621200350080000102003920039200392003920039
80024200381500000003925800101080000108000050640000020019200382003899963100188001020800002080000200382003811800211091010800001000000050200020170002519200350080000102003920039200392003920039
80024200381500000003925800101080000108000050640000020019200382003899963100188001020800002080000200382003811800211091010800001000010050200013160002412200350080000102003920039200392003920039
80024200381500000003925800101080000108000050640000020019200382003899963100188001020800002080000200382003821800211091010800001000000050223016160002716200350080000102003920039200392003920039
80024200381510000008125800101080000108000050640000020019200382003899963100188001020800002080000200382003811800211091010800001000012950200013160002715200350080000102003920039200392003920089
80024200381500010003925800101080000108000050640000020019200382003899963100188001020800002080000200382003811800211091010800001000010350200015160002526200350080000102003920039200392003920039
80024200381500000003925800101080000108000050640000020019200382003899963100188001020800002080000200382003811800211091010800001000050350200027160002727200350080000102008720090200392003920039
80024200381500000003925800101080000108000050640000020019200382003899963100188001020800002080000200382003811800211091010800001000000050200016160002714200350080000102003920039200392003920039
8002420038150000000392580010108000010800005064000002001920038200389996310018800102080000208000020038200381180021109101080000100004019250560026160001427200350080000102003920039200392003920039