Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

NOT (vector, 8B)

Test 1: uops

Code:

  not v0.8b, v0.8b
  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

retire uop (01)cycle (02)031e3f4e51schedule uop (52)schedule simd uop (54)dispatch simd uop (57)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map simd uop (7e)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst simd alu (9a)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)f5f6f7f8fd
100420371506116862510001000100026452112018203720371571318951000100010002037203711100110000073116111786100020382038203820382038
1004203715030116862510001000100026452112018203720371571318951000100010002037203711100110000073116111786100020382038203820382038
100420371506116862510001000100026452112018203720371571318951000100010002037203711100110000073116111786100020382038203820382038
100420371506116862510001000100026452112018203720371571318951000100010002037203711100110000073116111786100020382038203820382038
100420371606116862510001000100026452112018203720371571318951000100010002037203711100110000073116111786100020382038203820382038
1004203715018016862510001000100026452102018203720371571318951000100010002037203711100110000073116111786100020382038203820382038
100420371506116862510001000100026452102018203720371571318951000100010002037203711100110009073116111786100020382038203820382038
100420371506116862510001000100026452102018203720371571318951000100010002037203711100110000199573116111786100020382038203820382038
100420371506116862510001000100026452112018203720371571318951000100010002037203711100110000073116111786100020382038203820382038
1004203715018316862510001000100026452102018203720371571318951000100010002037203711100110000073116111786100020382038203820382038

Test 2: Latency 1->2

Code:

  not v0.8b, v0.8b
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)031e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9faccfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
10204200371500821968625101001001000010010000500284752102001820037200371842131874510100200100002001000020037200371110201100991001001000010007101161119791100001002003820038200382003820038
10204200371500611968625101001001000010010000500284752102001820037200371842131874510100200100002001000020037200371110201100991001001000010007101161119791100001002003820038200382003820038
102042003715002511968625101001001000010010000500284752112001820037200371842131874510100200100002001000020037200371110201100991001001000010007101161119791100001002003820038200382003820038
102042003715027611968625101001001000010010000500284752112001820037200371842131874510100200100002001000020037200371110201100991001001000010007101161119791100001002003820038200382003820038
10204200371500611968625101001001000010010000500284752102001820037200371842131874510100200100002001000020037200371110201100991001001000010007101161119791100001002003820038200382003820038
10204200371500611968625101001001000010010000500284752112001820037200371842131874510100200100002001000020037200371110201100991001001000010007101161119791100001002003820038200382003820038
10204200371500611968625101001001000010010000500284752102001820037200371842131874510100200100002001000020037200371110201100991001001000010007101161119791100001002003820038200382003820038
102042003715001031968625101001001000010010000500284752112001820037200371842131874510100200100002001000020037200371110201100991001001000010007101161119791100001002003820038200382003820038
10204200371500611968625101001001000010010000500284752102001820037200371842131874510100200100002001000020037200371110201100991001001000010007101161119791100001002003820038200382003820038
10204200371500611968625101001001000010010000500284752102001820037200371842131874510100200100002001000020037200371110201100991001001000010007101161119791100001002003820038200382003820038

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)03mmu table walk data (08)l2 tlb miss instruction (0a)l2 tlb miss data (0b)18191e1f3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d tlb miss (a1)ld unit uop (a6)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
10024200371500000024061196862510010101000010100005028475211200182003720037184433187671001020100002010000200372003711100211091010100001000006402162219786010000102003820038200382003820038
10024200371500000000611968625100101010000101000050284752112001820037200371844325187671001020100002010000200372003711100211091010100001000006402162219786010000102003820038200382003820038
10024200371500000018061196862510010101000010100005028475211200182003720037184433187671001020100002010000200372003711100211091010100001000006402162219786010000102003820038200382003820038
100242003715000000017661196862510010101000010100005028475211200182003720037184433187671001020100002010000200372003711100211091010100001000006402162219786010000102003820038200382003820038
1002420037150000000061196862510010101000010100005028475210200182003720037184433187671001020100002010000200372003711100211091010100001000006402162219786010000102003820038200382003820038
10024200371500000000102196862510010101000010100005028475210200182003720037184433187671001020100002010000200372003721100211091010100001004006402162219786010000102003820038200382003820038
1002420037150000000061196862510010101000010100005028475210200182003720037184433187671001020100002010000200372003711100211091010100001000006402162219786010000102003820038200382003820038
1002420037150000000061196862510010101000010100005028475210200182003720037184433187671001020100002010000200372003711100211091010100001000006402162219786010000102003820038200382003820038
1002420037150000026061196862510010101000010100005028475210200182003720037184433187671001020100002010000200372003711100211091010100001000006402162219786010000102003820038200382003820038
1002420037150000000061196862510010101000010100005028475210200182003720037184433187671001020100002010000200372003711100211091010100001000006402162219786010000102003820038200382003820038

Test 3: throughput

Count: 8

Code:

  not v0.8b, v8.8b
  not v1.8b, v8.8b
  not v2.8b, v8.8b
  not v3.8b, v8.8b
  not v4.8b, v8.8b
  not v5.8b, v8.8b
  not v6.8b, v8.8b
  not v7.8b, v8.8b
  movi v8.16b, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2506

retire uop (01)cycle (02)03mmu table walk data (08)l2 tlb miss data (0b)18191e3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d tlb miss (a1)ld unit uop (a6)l1d cache writeback (a8)a9acbranch cond mispred nonspec (c5)branch mispred nonspec (cb)cdcfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
80204200571500000152925801081008000810080020500640132020019200382003899776998980120200800322008003220038200381180201100991001008000010000000011151182163420035800001002003920039200392003920039
8020420038150000002925801081008000810080020500640132120019200382003899776998980120200800322008003220038200381180201100991001008000010000000011151184163420035800001002003920039200392003920039
80204200381500100020025801081008000810080020500640132020019200382003899776998980120200800322008003220038200381180201100991001008000010000000011151183163420035800001002003920039200392003920039
80204200381500000156427801161008001610080028500640196120028200482004899769998680128200800382008003820048200481180201100991001008000010000000022251295235520045800001002005020049200492005020050
8020420048150000106426801161008001610080028500640196020028200482004999769998680128200800382008003820125200994180201100991001008000010000000022251284235420045800001002004920050200492004920049
8020420048150000006426801161008001610080028500640196120028200482004999769998680128200800382008003820049200481180201100991001008000010000000022251284234420045800001002004920049200502004920049
802042004915000004264268011610080016100800285006401960200332004920048997610998680128200800382008003820048200481180201100991001008000010000100022251285235420046800001002005020049200492004920049
8020420048150000006426801161008001610080028500640196020028200482004899769998680128200800382008003820048200491180201100991001008000010000000022251283234420045800001002005020049200492004920049
8020420049150000006426801161008001610080028500640196020028200482004899769998680128200800382008003820049200481180201100991001008000010000000022251285235420045800001002004920049200492004920050
8020420048150000023764268011610080016100800285006401961200282004820049997610998680128200800382008003820049200481180201100991001008000010000000322251294234520045800001002004920049200502004920050

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)03l2 tlb miss data (0b)18191e1f3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)a9accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
8002420050150000210392580010108000010800005064000012001920038200389996310018800102080000208000020038200381180021109101080000100035020516322003580000102003920039200392003920039
800242003815000000392580010108000010800005064000012001920038200389996310018800102080000208000020038200381180021109101080000100005020316322003580000102003920039200392003920039
800242003815000000812580010108000010800005064000012001920038200389996310018800102080000208000020038200381180021109101080000100005020316322003580000102003920039200392003920039
800242003815000000392580010108000010800005064000012001920038200389996310018800102080000208000020038200381180021109101080000100005020316432003580000102003920039200392003920039
800242003815000030392580010108000010800005064232412001920038200389996310018800102080000208000020038200381180021109101080000100005020316322003580000102003920039200392003920039
800242003815000000392580010108000010800005064000012001920038200389996310018800102080000208000020038200381180021109101080000100005020316232003580000102003920039200392003920039
8002420038150000306092580010108000010800005064000012001920038200389996310018800102080000208000020038200381180021109101080000100005020316342003580000102003920039200392003920039
800242003815000000392580010108000010800005064000012001920038200389996310018800102080000208000020038200381180021109101080000100035020316332003580000102003920039200392003920039
800242003815000000392580010108000010800005064000012001920038200389996310018800102080000208000020038200381180021109101080000100005020316232003580000102003920039200392003920039
800242003815000000812580010108000010800005064000012001920038200389996310018800102080000208000020038200381180021109101080000100005020316332003580000102003920039200392003920039