Firestorm: ORR (vector, immediate, 4H) measurements

Code:

  orr v0.4h, #1

Initialization

  movi v0.16b, 1

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	4e	51	schedule uop (52)	schedule simd uop (54)	dispatch simd uop (57)	ldst uops in schedulers (5b)	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map simd uop (7e)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst simd alu (9a)	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	f5	f6	f7	f8	fd
1004	2037	15	0	61	1686	25	1000	1000	1000	264521	2018	2037	2037	1571	3	1895	1000	1000	1000	2037	2037	1	1	1001	1000	0	0	73	1	16	1	1	1786	1000	2038	2038	2038	2038	2038
1004	2037	15	0	61	1686	25	1000	1000	1000	264521	2018	2037	2037	1571	3	1895	1000	1000	1000	2037	2037	1	1	1001	1000	0	0	73	1	16	1	1	1786	1000	2038	2038	2038	2038	2038
1004	2037	15	0	61	1686	25	1000	1000	1000	264521	2018	2037	2037	1571	3	1895	1000	1000	1000	2037	2037	1	1	1001	1000	0	0	73	1	16	1	1	1786	1000	2038	2038	2038	2038	2038
1004	2037	15	0	61	1686	25	1000	1000	1000	264521	2018	2037	2037	1571	3	1895	1000	1000	1000	2037	2037	1	1	1001	1000	0	0	73	1	16	1	1	1786	1000	2038	2038	2038	2038	2038
1004	2037	15	0	61	1686	25	1000	1000	1000	264521	2018	2037	2037	1571	3	1895	1000	1000	1000	2037	2037	1	1	1001	1000	0	3	73	1	16	1	1	1786	1000	2038	2038	2038	2038	2038
1004	2037	16	0	61	1686	25	1000	1000	1000	264521	2018	2037	2037	1571	3	1895	1000	1000	1000	2037	2037	1	1	1001	1000	0	0	73	1	16	1	1	1786	1000	2038	2038	2038	2038	2038
1004	2037	15	0	61	1686	25	1000	1000	1000	264521	2018	2037	2037	1571	3	1895	1000	1000	1000	2037	2037	1	1	1001	1000	0	0	73	1	16	1	1	1786	1000	2038	2038	2038	2038	2038
1004	2037	15	0	61	1686	25	1000	1000	1000	264521	2018	2037	2037	1571	3	1895	1000	1000	1000	2037	2037	1	1	1001	1000	0	0	73	1	16	1	1	1786	1000	2038	2038	2038	2038	2038
1004	2037	15	0	61	1686	25	1000	1000	1000	264521	2018	2037	2037	1571	3	1895	1000	1000	1000	2037	2037	1	1	1001	1000	1	0	73	1	16	1	1	1786	1000	2038	2038	2038	2038	2038
1004	2037	15	0	61	1686	25	1000	1000	1000	264521	2018	2037	2037	1571	3	1895	1000	1000	1000	2037	2037	1	1	1001	1000	0	0	73	1	16	1	1	1786	1000	2038	2038	2038	2038	2038

Test 2: Latency 1->1

Code:

  orr v0.4h, #1

Initialization

  movi v0.16b, 1

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l2 tlb miss data (0b)	1e	3a	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	61	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d cache writeback (a8)	ac	c2	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d0	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10204	20037	150	0	0	0	686	19686	25	10100	100	10000	100	10000	500	2847521	0	0	20018	20037	20037	18428	6	18740	10100	200	10008	200	10008	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	1	1	1	717	0	0	16	0	0	19801	10000	100	20038	20038	20038	20038	20038
10204	20037	150	1	0	0	61	19686	25	10100	100	10012	104	10000	500	2847521	0	0	20018	20037	20037	18428	6	18733	10100	204	10008	200	10008	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	1	1	1	718	0	0	16	0	0	19801	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	3	0	1042	19686	25	10100	100	10000	104	10000	500	2847521	0	5	20018	20037	20037	18428	6	18741	10100	200	10008	200	10008	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	1	1	1	718	5	0	16	0	0	19800	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	0	0	726	19686	25	10100	100	10000	100	10000	500	2847521	1	0	20018	20037	20037	18428	7	18741	10100	200	10008	200	10008	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	1	1	1	718	5	0	16	0	0	19800	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	0	0	61	19686	25	10100	100	10000	100	10000	500	2847521	1	0	20018	20037	20037	18428	7	18741	10100	200	10008	200	10008	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	1	1	1	717	0	0	16	0	0	19800	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	0	0	103	19686	25	10100	100	10000	100	10000	500	2847521	1	0	20018	20037	20084	18428	14	18759	10100	200	10008	200	10008	20085	20037	1	1	10201	100	99	100	100	10000	100	2	0	3	2	1	1	1	743	0	0	32	0	0	19800	10000	100	20038	20038	20038	20086	20038
10204	20037	150	0	0	0	61	19686	25	10100	100	10000	100	10000	500	2847521	1	0	20018	20037	20037	18428	6	18741	10100	200	10008	200	10008	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	1	1	1	718	0	0	16	0	0	19800	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	0	0	61	19686	25	10100	100	10000	100	10000	500	2847521	0	5	20018	20037	20037	18428	7	18740	10100	200	10008	200	10008	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	1	1	1	717	0	0	16	0	0	19800	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	18	0	61	19686	25	10100	100	10000	100	10000	500	2847521	0	5	20018	20037	20037	18428	7	18741	10100	200	10008	200	10008	20037	20037	1	1	10201	100	99	100	100	10000	100	0	1	0	0	1	1	1	718	5	0	16	0	0	19800	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	0	0	61	19686	25	10100	100	10000	100	10000	500	2847521	0	5	20018	20037	20037	18439	7	18795	10100	200	10008	200	10008	20037	20037	1	1	10201	100	99	100	100	10000	100	0	1	0	0	1	1	1	717	5	0	16	0	0	19800	10000	100	20038	20038	20038	20038	20038

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	l2 tlb miss data (0b)	18	19	1e	1f	3a	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10024	20037	150	0	0	0	0	0	0	0	61	19686	25	10010	10	10000	10	10000	50	2847521	1	20018	20037	20037	18443	3	18767	10010	20	10000	20	10000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	640	2	16	2	2	19786	0	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	0	0	0	0	0	0	61	19686	25	10010	10	10000	10	10000	50	2847521	1	20018	20037	20037	18443	3	18767	10010	20	10000	20	10000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	640	2	16	2	2	19786	0	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	0	0	0	0	0	0	147	19686	25	10010	10	10000	10	10000	50	2847521	1	20018	20037	20037	18443	3	18767	10010	20	10000	20	10000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	640	2	16	2	2	19786	0	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	0	0	0	0	0	0	61	19686	25	10010	10	10000	10	10000	50	2847521	1	20018	20037	20037	18443	3	18767	10010	20	10000	20	10000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	669	2	16	2	2	19786	0	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	0	0	0	0	0	0	61	19686	25	10010	10	10000	10	10000	50	2847521	1	20018	20037	20037	18443	3	18767	10010	20	10000	20	10000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	640	2	16	2	2	19786	0	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	0	0	0	0	0	0	61	19686	25	10010	10	10000	10	10000	50	2847521	0	20018	20037	20037	18443	3	18767	10010	20	10000	20	10000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	640	2	16	2	2	19786	0	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	0	0	0	0	0	0	61	19686	25	10010	10	10000	10	10000	50	2847521	1	20018	20037	20037	18443	3	18767	10010	20	10000	20	10000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	640	2	16	2	2	19786	0	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	0	0	0	0	0	0	61	19686	25	10010	10	10000	10	10000	50	2847521	1	20018	20037	20037	18443	3	18767	10010	20	10000	20	10000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	640	2	16	2	2	19786	0	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	0	0	0	0	0	0	61	19686	25	10010	10	10000	10	10000	50	2847521	1	20018	20037	20037	18443	3	18767	10010	20	10000	20	10000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	640	2	16	2	2	19786	0	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	0	0	0	0	0	0	61	19686	25	10010	10	10000	10	10000	50	2847521	0	20018	20037	20037	18443	3	18767	10010	20	10000	20	10000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	640	2	16	2	2	19786	0	10000	10	20038	20038	20038	20038	20038

Test 3: throughput

Count: 8

Code:

  movi v0.16b, 0
  orr v0.4h, #1
  movi v1.16b, 0
  orr v1.4h, #1
  movi v2.16b, 0
  orr v2.4h, #1
  movi v3.16b, 0
  orr v3.4h, #1
  movi v4.16b, 0
  orr v4.4h, #1
  movi v5.16b, 0
  orr v5.4h, #1
  movi v6.16b, 0
  orr v6.4h, #1
  movi v7.16b, 0
  orr v7.4h, #1

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2508

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d cache writeback (a8)	a9	c2	cf	d5	map dispatch bubble (d6)	da	dd	fetch restart (de)	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160204	20088	150	330	38	25	80100	100	80000	100	80000	500	640000	1	20044	20063	20063	3	21	80100	200	80000	200	80000	20063	20132	1	1	160201	100	99	100	100	160000	100	0	0	0	10111	1	16	0	1	1	20060	160000	100	20064	20064	20064	20064	20064
160204	20063	150	351	38	25	80100	100	80000	100	80000	500	640000	1	20044	20063	20063	3	21	80100	200	80000	200	80000	20063	20063	1	1	160201	100	99	100	100	160000	100	0	0	0	10111	1	16	0	1	1	20060	160000	100	20064	20064	20064	20064	20064
160204	20063	150	0	58	25	80100	100	80000	100	80000	500	640000	1	20044	20063	20063	3	21	80100	200	80000	200	80000	20063	20063	1	1	160201	100	99	100	100	160000	100	0	0	0	10111	1	16	0	1	1	20060	160000	100	20064	20064	20064	20064	20064
160204	20063	150	27	38	25	80100	100	80000	100	80000	500	640000	1	20044	20063	20063	3	21	80100	200	80000	200	80000	20063	20063	1	1	160201	100	99	100	100	160000	100	0	0	0	10111	1	16	0	1	1	20060	160000	100	20064	20064	20064	20064	20064
160204	20063	150	0	38	25	80100	100	80000	100	80000	500	640000	1	20044	20063	20063	3	21	80100	200	80000	200	80000	20063	20063	1	1	160201	100	99	100	100	160000	100	0	0	0	10111	1	16	0	1	1	20060	160000	100	20064	20064	20064	20064	20064
160204	20063	150	0	38	25	80100	100	80000	100	80000	500	640000	1	20044	20063	20063	3	21	80100	200	80000	200	80000	20063	20063	1	1	160201	100	99	100	100	160000	100	0	0	0	10111	1	16	0	1	1	20060	160000	100	20064	20064	20064	20064	20064
160204	20063	150	369	38	25	80100	100	80000	100	80000	500	640000	1	20044	20063	20063	3	21	80100	200	80000	200	80000	20063	20063	2	1	160201	100	99	100	100	160000	100	0	0	0	10111	1	16	0	1	1	20060	160000	100	20064	20064	20064	20064	20064
160204	20063	151	0	38	25	80100	100	80000	100	80000	500	640000	1	20044	20063	20063	3	21	80100	200	80000	200	80000	20063	20063	1	1	160201	100	99	100	100	160000	100	0	0	0	10113	1	16	0	1	1	20060	160000	100	20064	20064	20064	20064	20064
160204	20063	150	0	38	25	80100	100	80000	100	80000	500	640000	1	20044	20063	20063	3	21	80100	200	80000	200	80000	20063	20063	1	1	160201	100	99	100	100	160000	100	0	0	0	10111	1	16	0	1	1	20060	160000	100	20064	20064	20064	20064	20064
160204	20063	150	420	38	25	80100	100	80000	100	80000	500	640000	1	20044	20063	20063	3	21	80100	200	80000	200	80000	20063	20063	1	1	160201	100	99	100	100	160000	100	0	0	0	10111	1	16	0	1	1	20060	160000	100	20064	20064	20064	20064	20064

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2507

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l2 tlb miss data (0b)	18	19	1e	1f	3a	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	5f	60	61	69	6b	6d	6e	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache writeback (a8)	a9	ac	c2	cf	d0	d2	l1i cache miss demand (d3)	d5	map dispatch bubble (d6)	d9	da	db	dd	fetch restart (de)	e0	? int output thing (e9)	ea	ec	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160024	20082	150	0	0	0	360	0	0	44	27	80012	12	80000	12	80000	62	640000	1	1	5	20031	0	20050	20050	3	21	80012	20	80000	20	80000	20059	20059	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	0	10029	11	6	2	3	34	4	2	2	2	3	20056	2	40	2	160000	10	20060	20051	20060	20060	20060
160024	20059	150	0	0	0	0	0	0	50	29	80012	12	80000	12	80000	62	640000	0	1	5	20040	0	20059	20059	3	21	80012	20	80000	20	80000	20059	20059	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	0	10029	11	6	2	2	34	4	2	2	3	3	20056	2	40	2	160000	10	20060	20060	20060	20060	20060
160024	20059	150	0	0	0	249	0	0	50	29	80012	12	80000	12	80000	62	640000	0	1	5	20040	0	20059	20059	3	21	80012	20	80000	20	80000	20059	20059	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	0	10029	11	6	2	3	34	4	2	2	3	2	20056	2	40	2	160000	10	20060	20060	20060	20060	20060
160024	20059	150	0	0	0	282	0	0	50	29	80012	12	80000	12	80000	62	640000	0	1	5	20040	0	20059	20059	3	21	80012	20	80000	20	80000	20059	20059	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	0	10028	11	6	2	3	34	4	2	2	2	3	20056	2	40	2	160000	10	20060	20060	20060	20060	20060
160024	20059	150	0	0	0	0	0	0	50	29	80012	12	80000	12	80000	62	640000	0	1	5	20040	0	20059	20059	3	21	80012	20	80000	20	80000	20059	20059	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	0	10029	11	6	2	3	34	4	2	2	3	3	20056	2	40	2	160000	10	20060	20060	20060	20060	20060
160024	20059	150	0	0	0	369	0	0	50	29	80012	12	80000	12	80000	62	640000	0	1	5	20040	0	20059	20059	3	21	80012	20	80000	20	80000	20059	20059	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	0	10029	11	6	2	2	34	4	2	2	3	2	20056	2	40	2	160000	10	20060	20060	20060	20060	20060
160024	20059	150	0	0	0	312	0	0	50	29	80012	12	80000	12	80000	62	640000	0	1	5	20040	0	20059	20059	3	21	80012	20	80000	20	80000	20059	20059	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	0	10028	11	6	2	3	34	4	2	2	4	3	20056	2	40	2	160000	10	20060	20060	20060	20060	20060
160024	20059	150	0	0	0	0	0	0	60	29	80012	12	80000	12	80000	62	640000	0	1	5	20040	0	20059	20059	3	21	80012	20	80000	20	80000	20059	20050	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	0	10028	8	2	2	3	34	4	2	2	3	3	20047	2	40	2	160000	10	20051	20060	20060	20051	20060
160024	20050	150	0	0	0	0	0	0	50	29	80012	12	80000	12	80000	62	640000	0	1	5	20040	0	20059	20059	3	21	80012	20	80000	20	80000	20059	20059	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	0	10029	11	6	2	3	34	4	2	2	3	2	20047	2	40	2	160000	10	20051	20060	20051	20060	20051
160024	20050	150	0	0	0	372	0	0	50	29	80012	12	80000	12	80000	62	640000	0	0	5	20031	0	20059	20059	3	21	80012	20	80000	20	80000	20059	20059	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	0	10029	11	2	2	3	34	4	1	2	3	3	20056	2	20	1	160000	10	20060	20051	20060	20060	20060

Test 4: throughput

Count: 16

Code:

  orr v0.4h, #1
  orr v1.4h, #1
  orr v2.4h, #1
  orr v3.4h, #1
  orr v4.4h, #1
  orr v5.4h, #1
  orr v6.4h, #1
  orr v7.4h, #1
  orr v8.4h, #1
  orr v9.4h, #1
  orr v10.4h, #1
  orr v11.4h, #1
  orr v12.4h, #1
  orr v13.4h, #1
  orr v14.4h, #1
  orr v15.4h, #1

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2502

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	l2 tlb miss instruction (0a)	1e	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6b	6d	6e	map stall dispatch (70)	simd prf full (72)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160204	40049	300	0	0	0	40	25	160100	100	160000	100	160000	500	1120016	0	40019	0	40038	40088	19973	0	3	19996	160100	200	160000	200	160000	40038	40038	1	1	160201	100	99	100	100	160000	100	10110	5	16	3	5	40035	160000	100	40039	40039	40039	40039	40039
160204	40038	300	0	0	0	135	25	160100	100	160000	100	160000	500	1120016	0	40019	0	40038	40038	19973	0	3	19996	160100	200	160000	200	160000	40038	40038	1	1	160201	100	99	100	100	160000	100	10110	5	16	5	5	40035	160000	100	40039	40039	40039	40039	40039
160204	40038	299	0	0	0	40	25	160100	100	160000	100	160000	500	1120016	0	40019	0	40038	40038	19973	0	3	19996	160100	200	160000	200	160000	40038	40038	1	1	160201	100	99	100	100	160000	100	10110	5	16	5	5	40035	160000	100	40039	40039	40039	40039	40039
160204	40038	299	0	0	0	40	25	160100	100	160000	100	160000	500	1120016	0	40019	0	40038	40038	19973	0	3	19996	160100	200	160000	200	160000	40038	40038	1	1	160201	100	99	100	100	160000	100	10110	3	16	5	5	40035	160000	100	40087	40039	40039	40039	40039
160204	40038	300	0	0	0	40	25	160100	100	160000	100	160000	500	1120016	0	40019	0	40038	40038	19973	0	3	19996	160100	200	160000	200	160000	40038	40038	1	1	160201	100	99	100	100	160000	100	10110	5	16	5	5	40035	160000	100	40039	40039	40039	40039	40039
160204	40038	299	0	0	0	40	25	160100	100	160000	100	160000	500	1120016	0	40019	0	40038	40038	19973	0	3	19996	160100	200	160000	200	160000	40038	40038	1	1	160201	100	99	100	100	160000	100	10110	5	16	5	5	40035	160000	100	40039	40039	40039	40039	40039
160204	40038	299	0	0	0	40	25	160100	100	160000	100	160000	500	1120016	0	40019	0	40038	40038	19973	0	3	19996	160100	200	160000	200	160000	40038	40038	1	1	160201	100	99	100	100	160000	100	10110	5	16	5	3	40035	160000	100	40039	40039	40039	40039	40039
160204	40038	300	0	0	0	40	25	160100	100	160000	100	160000	500	1120016	1	40019	0	40038	40038	19973	0	3	19996	160100	200	160000	200	160000	40038	40038	1	1	160201	100	99	100	100	160000	100	10110	5	16	5	5	40035	160000	100	40039	40039	40039	40039	40039
160204	40038	300	0	0	0	40	25	160100	100	160000	100	160000	500	1120016	1	40019	0	40038	40038	19973	0	3	19996	160100	200	160000	200	160000	40038	40038	1	1	160201	100	99	100	100	160000	100	10110	5	16	5	5	40035	160000	100	40039	40039	40039	40039	40039
160204	40038	299	0	0	0	40	25	160100	100	160000	100	160000	500	1120016	1	40019	0	40038	40038	19973	0	3	19996	160100	200	160000	200	160000	40038	40038	1	1	160201	100	99	100	100	160000	100	10110	5	16	5	5	40035	160000	100	40039	40039	40039	40039	40039

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2502

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	09	l2 tlb miss data (0b)	18	1e	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	5f	60	61	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache writeback (a8)	ac	c2	cf	d0	d2	l1i cache miss demand (d3)	d5	map dispatch bubble (d6)	d9	da	db	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160024	40039	300	0	0	0	9	45	25	160010	10	160000	10	160000	60	1120016	1	1	5	40019	40038	40038	19996	3	20018	160010	20	160000	20	160000	40038	40038	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	10024	11	3	2	7	16	4	2	1	6	7	40035	0	20	8	160000	10	40039	40039	40039	40039	40039
160024	40038	300	0	0	0	12	45	25	160010	10	160000	10	160096	60	1120016	1	1	5	40019	40038	40038	19996	3	20018	160010	20	160000	20	160000	40038	40038	1	1	160021	10	9	10	10	160000	10	0	0	1	9	0	10022	8	2	1	6	16	2	1	1	7	6	40035	0	40	16	160000	10	40039	40039	40039	40039	40039
160024	40038	300	0	0	0	0	45	25	160010	10	160000	10	160000	60	1120016	2	1	5	40019	40038	40038	19996	3	20018	160010	20	160000	20	160000	40038	40038	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	10022	8	2	1	8	16	2	1	1	6	9	40035	0	20	8	160000	10	40039	40039	40039	40039	40039
160024	40038	299	0	0	0	0	45	25	160010	10	160000	10	160000	60	1120016	0	1	5	40019	40038	40038	19996	3	20018	160010	20	160000	20	160000	40038	40038	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	10022	8	2	1	7	16	2	1	1	7	7	40035	0	20	8	160000	10	40039	40039	40039	40039	40039
160024	40038	300	0	0	0	0	45	44	160104	10	160000	10	160000	60	1120016	1	1	5	40019	40038	40038	19996	3	20018	160010	20	160000	20	160000	40038	40089	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	10022	8	2	1	7	16	2	1	2	6	7	40035	0	20	16	160000	10	40039	40039	40039	40039	40039
160024	40038	300	0	0	0	0	45	25	160010	10	160000	10	160000	60	1120016	2	1	5	40019	40038	40038	19996	3	20018	160010	20	160000	20	160000	40038	40038	1	1	160021	10	9	10	10	160000	10	4	2	1	0	0	10022	8	2	1	8	16	2	1	1	5	8	40035	0	20	8	160000	10	40039	40039	40039	40039	40039
160024	40038	300	0	0	0	0	45	25	160010	10	160000	10	160000	60	1120016	2	1	5	40019	40038	40038	19996	3	20018	160010	20	160000	20	160000	40038	40038	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	10024	11	3	2	6	16	4	2	1	6	6	40035	0	20	8	160000	10	40039	40039	40039	40039	40039
160024	40038	299	0	0	0	0	215	25	160010	10	160000	10	160000	60	1120016	1	1	5	40019	40038	40038	19996	3	20018	160010	20	160000	20	160000	40038	40038	1	1	160021	10	9	10	10	160000	10	0	0	2	0	0	10024	11	3	1	7	16	2	1	2	7	8	40035	0	20	16	160000	10	40039	40039	40039	40039	40039
160024	40038	300	0	0	0	0	45	25	160010	10	160000	10	160000	60	1120016	1	1	5	40019	40038	40038	19996	3	20018	160010	20	160000	20	160000	40038	40038	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	10022	8	2	1	6	16	2	2	2	6	6	40035	0	40	16	160000	10	40039	40039	40039	40039	40039
160024	40038	300	0	0	0	0	45	25	160010	10	160000	10	160000	60	1120016	1	1	5	40019	40038	40038	19996	3	20018	160010	20	160000	20	160000	40038	40038	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	10022	8	2	1	8	16	3	2	1	6	9	40035	0	20	8	160000	10	40039	40039	40039	40039	40039

ORR (vector, immediate, 4H)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->1

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 4: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations