Firestorm: ORR (vector, immediate, 8H) measurements

Code:

  orr v0.8h, #1

Initialization

  movi v0.16b, 1

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	09	18	1e	3f	4e	51	schedule uop (52)	schedule simd uop (54)	dispatch simd uop (57)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map simd uop (7e)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst simd alu (9a)	l1d cache writeback (a8)	ac	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	f5	f6	f7	f8	fd
1004	2037	15	0	0	0	342	1686	25	1000	1000	1000	264521	1	2018	2037	2037	1571	3	1895	1000	1000	1000	2037	2037	1	1	1001	1000	0	0	0	73	1	16	1	1	1786	1000	2038	2038	2038	2038	2038
1004	2037	15	0	0	0	99	1686	25	1000	1000	1000	264521	1	2018	2037	2037	1571	3	1895	1000	1000	1000	2037	2037	1	1	1001	1000	0	0	0	73	1	16	1	1	1786	1000	2038	2038	2038	2038	2038
1004	2037	15	0	0	0	187	1686	25	1000	1000	1000	264521	1	2018	2037	2037	1571	3	1895	1000	1000	1000	2037	2037	1	1	1001	1000	0	0	0	73	1	16	1	1	1786	1000	2038	2038	2038	2038	2038
1004	2037	16	0	0	0	505	1686	25	1000	1000	1000	264521	1	2018	2037	2037	1571	3	1895	1000	1000	1000	2037	2037	1	1	1001	1000	0	0	0	73	1	16	1	1	1786	1000	2038	2038	2038	2038	2038
1004	2037	15	0	0	0	195	1686	25	1000	1000	1000	264521	1	2018	2037	2037	1571	3	1895	1000	1000	1000	2037	2037	1	1	1001	1000	0	0	0	73	1	16	1	1	1786	1000	2038	2038	2038	2038	2038
1004	2037	16	0	0	0	82	1686	25	1000	1000	1000	264521	1	2018	2037	2037	1571	3	1895	1000	1000	1000	2037	2037	1	1	1001	1000	0	0	0	73	1	16	1	1	1786	1000	2038	2038	2038	2038	2038
1004	2037	15	0	0	0	84	1686	25	1000	1000	1000	264521	1	2018	2037	2037	1571	3	1895	1000	1000	1000	2037	2037	1	1	1001	1000	1	0	0	73	1	16	1	1	1786	1000	2038	2038	2038	2038	2038
1004	2037	15	0	0	0	82	1686	25	1000	1000	1000	264521	1	2018	2037	2037	1571	3	1895	1000	1000	1000	2037	2037	1	1	1001	1000	1	0	0	73	1	16	1	1	1786	1000	2038	2038	2038	2038	2038
1004	2037	16	0	0	0	143	1686	25	1000	1000	1000	264521	1	2018	2037	2037	1571	3	1895	1000	1000	1000	2037	2037	1	1	1001	1000	6	0	0	73	1	16	1	1	1786	1000	2038	2038	2038	2038	2038
1004	2037	16	0	0	0	61	1686	25	1000	1000	1000	264521	1	2018	2037	2037	1571	3	1895	1000	1000	1000	2037	2037	1	1	1001	1000	5	0	0	73	1	16	1	1	1820	1000	2038	2038	2038	2038	2038

Test 2: Latency 1->1

Code:

  orr v0.8h, #1

Initialization

  movi v0.16b, 1

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l2 tlb miss data (0b)	1e	1f	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb miss (a1)	l1d cache writeback (a8)	a9	ac	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10204	20037	150	0	0	0	61	19686	25	10100	100	10000	100	10000	500	2847521	0	20018	20037	20037	18428	7	18741	10100	200	10008	200	10008	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	0	6	1	1	1	718	0	16	0	0	19800	0	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	0	0	61	19686	25	10100	100	10000	100	10000	500	2847521	0	20018	20037	20037	18428	6	18741	10100	200	10008	200	10008	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	1	1	1	717	0	16	0	0	19800	0	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	420	0	61	19686	25	10100	100	10000	100	10000	500	2847521	0	20018	20037	20037	18428	6	18740	10100	200	10008	200	10008	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	1	1	1	717	0	16	0	0	19800	0	10000	100	20038	20038	20038	20038	20038
10204	20085	150	0	0	0	61	19686	25	10100	100	10000	100	10000	500	2847521	0	20018	20037	20037	18428	6	18740	10100	200	10008	200	10008	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	1	1	1	717	0	16	0	0	19800	0	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	0	0	61	19686	25	10100	100	10000	100	10000	500	2847521	0	20018	20037	20037	18428	6	18741	10100	200	10008	200	10008	20037	20086	1	1	10201	100	99	100	100	10000	100	0	0	0	0	1	1	1	722	2	24	2	2	19787	0	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	162	108	97	19686	25	10114	102	10000	100	10000	500	2849896	0	20018	20037	20037	18409	6	18733	10100	200	10000	200	10000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	1	1	1	722	2	24	2	2	19787	0	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	0	0	97	19686	25	10100	100	10000	100	10000	500	2847521	0	20018	20037	20037	18409	6	18733	10100	200	10000	200	10000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	5	0	0	1	1	1	722	2	24	2	2	19787	0	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	0	0	97	19686	25	10100	100	10000	100	10000	517	2847521	0	20018	20037	20037	18428	7	18740	10100	200	10008	200	10008	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	1	1	1	717	0	16	0	0	19801	0	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	0	0	61	19686	25	10100	100	10000	100	10000	500	2847521	0	20018	20037	20037	18428	7	18741	10100	200	10008	200	10008	20037	20037	1	1	10201	100	99	100	100	10000	100	0	1	0	0	1	1	1	718	0	16	0	0	19801	0	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	12	0	61	19686	25	10100	100	10000	100	10000	500	2847521	0	20018	20037	20037	18428	6	18740	10100	200	10008	200	10008	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	1	1	1	718	0	16	0	0	19801	0	10000	100	20038	20038	20038	20038	20038

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	18	1e	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10024	20037	150	0	0	0	61	19686	25	10010	10	10000	10	10000	50	2847521	0	20018	20037	20037	18443	3	18767	10010	20	10000	20	10000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	150	640	3	16	3	3	19786	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	0	0	61	19686	25	10010	10	10000	10	10000	50	2847521	0	20018	20037	20037	18443	3	18767	10010	20	10000	20	10000	20037	20037	1	1	10021	10	9	10	10	10000	10	38	0	640	3	16	3	3	19786	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	0	0	61	19686	25	10010	10	10000	10	10000	50	2847521	0	20018	20037	20037	18443	3	18767	10010	20	10000	20	10000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	640	3	16	3	3	19786	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	0	0	61	19686	25	10010	10	10000	10	10000	50	2847521	0	20018	20037	20037	18455	3	18767	10010	20	10000	20	10000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	156	640	3	16	3	3	19786	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	0	0	103	19686	25	10010	10	10000	10	10000	50	2847521	0	20018	20037	20037	18443	3	18767	10010	20	10000	20	10000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	640	3	16	3	3	19786	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	0	0	61	19686	25	10010	10	10000	10	10000	50	2847521	0	20018	20037	20037	18443	3	18767	10010	20	10000	20	10000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	640	3	16	3	3	19786	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	0	24	61	19686	25	10010	10	10000	10	10000	50	2847521	0	20018	20037	20037	18443	3	18767	10010	20	10000	20	10000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	640	3	16	3	3	19786	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	0	0	61	19686	25	10010	10	10000	10	10000	50	2847521	0	20018	20037	20037	18443	3	18767	10010	20	10000	20	10000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	72	640	3	16	3	3	19786	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	0	0	61	19686	25	10010	10	10000	10	10000	50	2847521	0	20018	20037	20037	18443	3	18767	10010	20	10000	20	10000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	640	3	16	3	3	19786	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	0	0	61	19686	25	10010	10	10000	10	10000	50	2847521	0	20018	20037	20037	18443	3	18767	10010	20	10000	20	10000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	9	640	3	16	3	3	19786	10000	10	20038	20038	20038	20038	20038

Test 3: throughput

Count: 8

Code:

  movi v0.16b, 0
  orr v0.8h, #1
  movi v1.16b, 0
  orr v1.8h, #1
  movi v2.16b, 0
  orr v2.8h, #1
  movi v3.16b, 0
  orr v3.8h, #1
  movi v4.16b, 0
  orr v4.8h, #1
  movi v5.16b, 0
  orr v5.8h, #1
  movi v6.16b, 0
  orr v6.8h, #1
  movi v7.16b, 0
  orr v7.8h, #1

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2508

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	19	1e	1f	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	69	6d	6e	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160204	20090	151	0	0	0	38	25	80100	100	80000	100	80000	500	640000	20044	20063	20063	3	21	80100	200	80000	200	80000	20063	20063	1	1	160201	100	99	100	100	160000	100	0	6	10111	1	16	1	1	20060	160000	100	20064	20064	20064	20064	20064
160204	20063	150	0	0	0	38	25	80100	100	80000	100	80000	500	640000	20044	20063	20063	3	21	80100	200	80000	200	80000	20063	20063	1	1	160201	100	99	100	100	160000	100	0	99	10111	1	16	1	1	20060	160000	100	20064	20064	20064	20064	20064
160204	20063	150	0	15	0	38	25	80100	100	80000	100	80000	500	640000	20044	20063	20063	3	21	80228	200	80000	200	80000	20063	20063	1	1	160201	100	99	100	100	160000	100	0	0	10111	1	16	1	1	20060	160000	100	20064	20064	20064	20064	20064
160204	20063	150	0	0	0	80	25	80100	100	80000	100	80000	500	640000	20044	20063	20063	3	21	80100	200	80000	200	80000	20063	20063	1	1	160201	100	99	100	100	160000	100	0	117	10111	1	16	1	1	20060	160000	100	20064	20064	20064	20064	20064
160204	20063	150	0	36	0	38	25	80100	100	80000	100	80000	500	640000	20044	20063	20063	3	21	80100	200	80000	200	80000	20063	20063	1	1	160201	100	99	100	100	160000	100	0	0	10111	1	16	1	1	20060	160000	100	20064	20064	20064	20064	20064
160204	20063	150	0	0	0	38	25	80214	100	80000	100	80000	500	640000	20044	20063	20063	3	21	80100	200	80000	200	80000	20063	20063	1	1	160201	100	99	100	100	160000	100	0	0	10111	1	16	1	1	20060	160000	100	20064	20064	20064	20064	20064
160204	20063	150	0	0	0	38	25	80100	100	80000	100	80000	500	640000	20044	20063	20063	3	21	80100	200	80000	200	80000	20063	20063	1	1	160201	100	99	100	100	160000	100	0	0	10111	1	16	1	1	20060	160000	100	20064	20064	20064	20064	20064
160204	20063	150	0	0	0	38	25	80100	100	80000	100	80000	500	640000	20044	20063	20063	3	21	80100	200	80000	200	80000	20063	20063	1	1	160201	100	99	100	100	160000	100	0	0	10111	1	16	1	1	20060	160000	100	20064	20064	20064	20064	20064
160204	20063	150	0	0	0	38	25	80100	100	80000	100	80000	500	640000	20044	20063	20063	3	21	80100	200	80000	200	80000	20063	20063	1	1	160201	100	99	100	100	160000	100	0	9	10111	1	16	1	1	20060	160000	100	20064	20064	20064	20064	20064
160204	20063	150	0	21	0	38	25	80100	100	80000	100	80000	500	640000	20044	20063	20063	3	21	80100	200	80000	200	80000	20063	20063	1	1	160201	100	99	100	100	160000	100	0	0	10111	1	16	1	1	20060	160000	100	20064	20064	20064	20064	20064

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2506

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk instruction (07)	l2 tlb miss instruction (0a)	l2 tlb miss data (0b)	18	19	1e	3a	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	5f	60	61	69	6d	6e	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache writeback (a8)	ac	cf	d0	d2	l1i cache miss demand (d3)	d5	map dispatch bubble (d6)	d9	da	db	dd	fetch restart (de)	e0	? int output thing (e9)	ea	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160024	20068	151	2	2	0	0	0	72	0	157	25	80012	12	80000	12	80000	62	640000	1	1	0	20026	20045	20045	3	21	80012	20	80000	20	80000	20045	20045	1	1	160021	10	9	10	10	160000	10	0	0	1	1928	10047	8	2	1	27	24	2	1	1	23	24	20042	2	15	160000	10	20046	20050	20046	20046	20046
160024	20045	150	0	0	0	0	0	6	0	44	25	80012	12	80000	12	80000	62	640000	1	1	5	20030	20049	20049	3	21	80012	20	80000	20	80000	20049	20049	1	1	160021	10	9	10	10	160000	10	0	0	1	3	10048	11	3	1	21	24	4	2	2	23	22	20046	2	30	160000	10	20046	20046	20046	20046	20046
160024	20045	151	0	1	0	0	0	0	1	866	25	80012	12	80000	12	80000	62	640000	1	1	5	20026	20045	20045	3	21	80012	20	80000	20	80000	20045	20045	1	1	160021	10	9	10	10	160000	10	0	4	1	2398	10046	8	2	1	25	20	2	1	1	23	24	20132	2	15	160000	10	20046	20046	20050	20046	20046
160024	20045	150	1	1	0	0	0	0	1	710	25	80012	12	80000	12	80000	62	640000	1	1	5	20026	20045	20045	3	21	80012	20	80000	20	80000	20045	20045	1	1	160021	10	9	10	10	160000	10	0	0	0	0	10046	8	2	1	23	20	2	1	1	22	23	20042	2	15	160000	10	20046	20046	20046	20046	20046
160024	20045	150	2	2	0	0	0	0	0	44	25	80012	12	80000	12	80000	62	640000	1	1	5	20026	20045	20045	3	21	80012	20	80000	20	80000	20045	20045	1	1	160021	10	9	10	10	160000	10	0	0	0	0	10048	8	2	1	23	20	2	1	1	23	22	20042	2	15	160000	10	20046	20046	20050	20048	20046
160024	20045	150	1	0	0	0	0	0	0	50	25	80012	12	80000	12	80000	62	640000	1	1	5	20026	20045	20045	3	21	80012	20	80000	20	80000	20045	20045	1	1	160021	10	9	10	10	160000	10	0	0	0	3	10046	8	2	1	22	20	2	1	1	17	25	20042	2	15	160000	10	20046	20046	20046	20046	20046
160024	20045	150	3	2	0	0	0	0	0	50	25	80012	12	80000	12	80000	62	640000	1	1	5	20026	20045	20045	3	21	80012	20	80000	20	80000	20045	20045	1	1	160021	10	9	10	10	160000	10	0	0	2	0	10046	8	2	1	23	20	2	1	1	23	25	20042	2	15	160000	10	20046	20046	20046	20046	20046
160024	20045	150	1	2	0	0	0	0	0	56	25	80012	12	80000	12	80000	62	640000	1	1	5	20026	20045	20045	3	21	80012	20	80000	20	80000	20045	20045	1	1	160021	10	9	10	10	160000	10	0	0	2	0	10048	8	2	1	22	20	2	1	1	21	22	20042	2	15	160000	10	20046	20046	20046	20046	20046
160024	20045	150	0	1	0	0	0	0	0	50	25	80012	12	80000	12	80000	62	640000	1	1	5	20026	20045	20045	3	21	80012	20	80000	20	80000	20045	20045	1	1	160021	10	9	10	10	160000	10	0	0	0	0	10046	8	2	1	23	20	2	1	1	23	23	20042	2	15	160000	10	20046	20046	20046	20046	20046
160024	20045	150	2	1	0	0	0	0	0	50	25	80012	12	80000	12	80000	62	640000	1	1	5	20026	20045	20045	3	21	80012	20	80000	20	80000	20045	20045	1	1	160021	10	9	10	10	160000	10	0	0	0	0	10047	8	2	1	24	20	2	1	1	23	24	20042	2	15	160000	10	20046	20046	20046	20046	20046

Test 4: throughput

Count: 16

Code:

  orr v0.8h, #1
  orr v1.8h, #1
  orr v2.8h, #1
  orr v3.8h, #1
  orr v4.8h, #1
  orr v5.8h, #1
  orr v6.8h, #1
  orr v7.8h, #1
  orr v8.8h, #1
  orr v9.8h, #1
  orr v10.8h, #1
  orr v11.8h, #1
  orr v12.8h, #1
  orr v13.8h, #1
  orr v14.8h, #1
  orr v15.8h, #1

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2502

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d cache writeback (a8)	ac	branch mispred nonspec (cb)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160204	40057	300	0	40	25	160100	100	160000	100	160000	500	1120016	1	40019	40038	40038	19973	3	19996	160100	200	160000	200	160000	40038	40087	1	1	160201	100	99	100	100	160000	100	0	0	0	10110	1	16	1	1	40035	160000	100	40039	40039	40039	40039	40039
160204	40038	301	0	40	44	160219	100	160000	100	160000	500	1120016	0	40019	40038	40038	19973	3	19996	160100	200	160000	200	160000	40038	40038	1	1	160201	100	99	100	100	160000	100	0	0	0	10110	1	16	1	1	40035	160000	100	40039	40039	40039	40039	40039
160204	40038	299	0	40	25	160100	100	160000	100	160000	500	1120016	0	40019	40038	40038	19973	3	19996	160100	200	160000	200	160000	40038	40038	1	1	160201	100	99	100	100	160000	100	0	0	0	10110	1	16	1	1	40035	160000	100	40039	40039	40039	40039	40039
160204	40038	300	0	40	25	160100	100	160000	100	160000	500	1120016	0	40019	40038	40038	19973	3	19996	160100	200	160000	200	160000	40038	40038	1	1	160201	100	99	100	100	160000	100	0	0	0	10110	1	16	1	1	40035	160000	100	40039	40039	40039	40039	40039
160204	40038	299	0	40	25	160100	100	160000	100	160000	500	1120016	1	40019	40038	40038	19973	3	19996	160100	200	160000	200	160000	40038	40038	1	1	160201	100	99	100	100	160000	100	0	0	0	10110	1	16	1	1	40035	160000	100	40039	40039	40039	40039	40039
160204	40038	300	0	40	51	160100	100	160000	100	160000	500	1120016	1	40019	40038	40038	19973	3	19996	160100	200	160000	200	160000	40038	40038	1	1	160201	100	99	100	100	160000	100	0	0	0	10110	1	16	1	1	40035	160000	100	40039	40039	40039	40039	40039
160204	40038	300	0	40	25	160100	100	160000	100	160000	500	1120016	0	40019	40038	40038	19973	3	19996	160100	200	160000	200	160000	40038	40038	1	1	160201	100	99	100	100	160000	100	0	0	0	10110	1	16	1	1	40035	160000	100	40039	40039	40039	40039	40039
160204	40038	300	414	40	25	160100	100	160000	100	160000	500	1120016	1	40019	40038	40038	19973	3	19996	160100	200	160000	200	160000	40038	40038	1	1	160201	100	99	100	100	160000	100	0	0	0	10110	1	16	1	1	40035	160000	100	40039	40039	40039	40039	40039
160204	40038	300	0	40	25	160100	100	160000	100	160000	500	1120016	1	40019	40038	40038	19973	3	19996	160100	200	160000	200	160000	40038	40038	1	1	160201	100	99	100	100	160000	100	0	0	0	10110	1	16	1	1	40035	160000	100	40039	40039	40039	40039	40039
160204	40038	300	0	705	25	160100	100	160000	100	160000	500	1120016	0	40019	40038	40038	19973	3	19996	160100	200	160000	200	160000	40038	40038	1	1	160201	100	99	100	100	160000	100	0	0	0	10110	1	16	1	1	40035	160000	100	40039	40039	40039	40039	40039

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2502

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	5f	60	61	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d cache writeback (a8)	ac	cf	d0	d2	l1i cache miss demand (d3)	d5	map dispatch bubble (d6)	d9	da	db	dd	fetch restart (de)	e0	ea	eb	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160024	40048	300	0	45	25	160010	10	160000	10	160000	50	1120016	0	1	0	40019	40038	40038	19996	3	20018	160010	20	160000	20	160000	40038	40038	1	1	160021	10	9	10	10	160000	10	0	6	10024	3	1	1	39	16	2	1	1	14	16	40035	20	8	160000	10	40039	40039	40039	40039	40039
160024	40038	300	0	51	25	160010	10	160000	10	160000	50	1120016	1	0	0	40019	40038	40038	19996	3	20018	160010	20	160000	20	160000	40038	40038	1	1	160021	10	9	10	10	160000	10	0	0	10022	8	4	1	19	16	2	1	1	13	11	40035	20	8	160000	10	40039	40039	40039	40039	40039
160024	40038	300	0	45	25	160010	10	160000	10	160000	50	1120016	1	0	5	40019	40038	40038	19996	3	20018	160010	20	160000	20	160000	40038	40038	1	1	160021	10	9	10	10	160000	10	0	9	10022	3	1	1	13	16	2	1	1	13	17	40035	20	8	160000	10	40039	40039	40039	40039	40039
160024	40038	300	0	45	25	160010	10	160000	10	160000	50	1120016	1	1	0	40019	40038	40038	19996	3	20018	160010	20	160000	20	160000	40038	40038	1	1	160021	10	9	10	10	160000	10	0	0	10022	8	1	1	13	16	2	1	1	18	14	40035	20	8	160000	10	40039	40039	40039	40039	40039
160024	40038	300	0	78	25	160010	10	160000	10	160000	50	1120016	1	0	5	40019	40038	40038	19996	3	20018	160010	20	160000	20	160000	40038	40038	1	1	160021	10	9	10	10	160000	10	0	0	10022	8	4	1	13	16	2	1	1	14	12	40035	20	8	160000	10	40039	40039	40039	40039	40039
160024	40038	300	0	55	25	160010	10	160000	10	160000	50	1120016	1	1	0	40019	40038	40038	19996	3	20018	160010	20	160000	20	160000	40038	40038	1	1	160021	10	9	10	10	160000	10	0	0	10022	3	5	1	13	16	2	1	1	13	11	40035	20	8	160000	10	40039	40039	40039	40039	40039
160024	40038	300	0	45	25	160010	10	160000	10	160000	50	1120016	1	0	5	40019	40038	40038	19996	3	20018	160010	20	160000	20	160000	40038	40038	1	1	160021	10	9	10	10	160000	10	0	0	10022	8	4	1	13	16	2	1	1	20	15	40035	20	8	160000	10	40039	40039	40039	40039	40039
160024	40038	300	0	45	25	160010	10	160000	10	160000	50	1120016	1	1	5	40019	40038	40038	19996	3	20018	160010	20	160000	20	160000	40038	40038	1	1	160021	10	9	10	10	160000	10	0	0	10022	8	4	1	11	16	2	1	1	13	12	40035	20	8	160000	10	40039	40039	40039	40039	40039
160024	40038	300	0	45	25	160010	10	160000	10	160000	50	1120016	1	1	5	40019	40038	40088	19996	3	20018	160010	20	160000	20	160000	40038	40038	1	1	160021	10	9	10	10	160000	10	0	0	10022	3	4	1	13	16	2	1	1	11	13	40035	20	8	160000	10	40039	40039	40039	40039	40039
160024	40038	300	0	45	25	160010	10	160000	10	160000	50	1120016	1	1	5	40019	40038	40038	19996	3	20018	160010	20	160000	20	160000	40038	40038	1	1	160021	10	9	10	10	160000	10	0	0	10022	8	4	1	16	16	2	1	1	11	20	40035	20	8	160000	10	40039	40039	40039	40039	40039

ORR (vector, immediate, 8H)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->1

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 4: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations